1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ 14 #define ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_TPC0_CFG 19 * (Prototype: TPC) 20 ***************************************** 21 */ 22 23 /* DCORE0_TPC0_CFG_TPC_COUNT */ 24 #define DCORE0_TPC0_CFG_TPC_COUNT_V_SHIFT 0 25 #define DCORE0_TPC0_CFG_TPC_COUNT_V_MASK 0xFFFFFFFF 26 27 /* DCORE0_TPC0_CFG_TPC_ID */ 28 #define DCORE0_TPC0_CFG_TPC_ID_V_SHIFT 0 29 #define DCORE0_TPC0_CFG_TPC_ID_V_MASK 0xFFFFFFFF 30 31 /* DCORE0_TPC0_CFG_STALL_ON_ERR */ 32 #define DCORE0_TPC0_CFG_STALL_ON_ERR_V_SHIFT 0 33 #define DCORE0_TPC0_CFG_STALL_ON_ERR_V_MASK 0x1 34 35 /* DCORE0_TPC0_CFG_CLK_EN */ 36 #define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_SHIFT 0 37 #define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_MASK 0x1 38 #define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_SHIFT 4 39 #define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_MASK 0x10 40 41 /* DCORE0_TPC0_CFG_IQ_RL_EN */ 42 #define DCORE0_TPC0_CFG_IQ_RL_EN_V_SHIFT 0 43 #define DCORE0_TPC0_CFG_IQ_RL_EN_V_MASK 0x1 44 45 /* DCORE0_TPC0_CFG_IQ_RL_SAT */ 46 #define DCORE0_TPC0_CFG_IQ_RL_SAT_V_SHIFT 0 47 #define DCORE0_TPC0_CFG_IQ_RL_SAT_V_MASK 0xFF 48 49 /* DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN */ 50 #define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_SHIFT 0 51 #define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_MASK 0xFF 52 53 /* DCORE0_TPC0_CFG_IQ_RL_TIMEOUT */ 54 #define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_SHIFT 0 55 #define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_MASK 0xFF 56 57 /* DCORE0_TPC0_CFG_TSB_CFG_MTRR_2 */ 58 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_SHIFT 0 59 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_MASK 0xFFFFFF 60 61 /* DCORE0_TPC0_CFG_IQ_LBW_CLK_EN */ 62 #define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_SHIFT 0 63 #define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_MASK 0x1 64 65 /* DCORE0_TPC0_CFG_TPC_LOCK_VALUE */ 66 #define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_SHIFT 0 67 #define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_MASK 0xFFFFFFFF 68 69 /* DCORE0_TPC0_CFG_TPC_LOCK */ 70 #define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_SHIFT 0 71 #define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_MASK 0x1 72 73 /* DCORE0_TPC0_CFG_CGU_SB */ 74 #define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_SHIFT 0 75 #define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_MASK 0x1 76 77 /* DCORE0_TPC0_CFG_CGU_CNT */ 78 #define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_SHIFT 0 79 #define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_MASK 0x1 80 #define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_SHIFT 1 81 #define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_MASK 0x2 82 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_SHIFT 2 83 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_MASK 0x4 84 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_SHIFT 3 85 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_MASK 0x8 86 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_SHIFT 4 87 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_MASK 0x10 88 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_SHIFT 5 89 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_MASK 0x20 90 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_SHIFT 6 91 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_MASK 0x40 92 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_SHIFT 7 93 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_MASK 0x80 94 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_SHIFT 8 95 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_MASK 0x100 96 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_SHIFT 9 97 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_MASK 0x200 98 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_SHIFT 10 99 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_MASK 0x400 100 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_SHIFT 11 101 #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_MASK 0x800 102 #define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_SHIFT 12 103 #define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_MASK 0x1000 104 #define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_SHIFT 13 105 #define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_MASK 0x2000 106 #define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_SHIFT 14 107 #define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_MASK 0x4000 108 #define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_SHIFT 15 109 #define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_MASK 0x8000 110 #define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_SHIFT 16 111 #define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_MASK 0x10000 112 #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_SHIFT 17 113 #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_MASK 0x20000 114 #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_SHIFT 18 115 #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_MASK 0x40000 116 #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_SHIFT 19 117 #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_MASK 0x80000 118 #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_SHIFT 20 119 #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_MASK 0x100000 120 #define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_SHIFT 21 121 #define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_MASK 0x200000 122 #define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_SHIFT 22 123 #define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_MASK 0x400000 124 #define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_SHIFT 23 125 #define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_MASK 0x800000 126 127 /* DCORE0_TPC0_CFG_CGU_CPE */ 128 #define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_SHIFT 0 129 #define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_MASK 0x1 130 #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_SHIFT 1 131 #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_MASK 0x2 132 #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_SHIFT 2 133 #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_MASK 0x4 134 #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_SHIFT 3 135 #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_MASK 0x8 136 #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_SHIFT 4 137 #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_MASK 0x10 138 #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_SHIFT 5 139 #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_MASK 0x20 140 #define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_SHIFT 6 141 #define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_MASK 0x40 142 #define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_SHIFT 7 143 #define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_MASK 0x80 144 #define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_SHIFT 8 145 #define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_MASK 0x100 146 #define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_SHIFT 9 147 #define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_MASK 0x200 148 #define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_SHIFT 10 149 #define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_MASK 0x400 150 #define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_SHIFT 11 151 #define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_MASK 0x800 152 #define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_SHIFT 12 153 #define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_MASK 0x1000 154 #define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_SHIFT 13 155 #define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_MASK 0x2000 156 #define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_SHIFT 14 157 #define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_MASK 0x4000 158 #define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_SHIFT 15 159 #define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_MASK 0x8000 160 #define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_SHIFT 16 161 #define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_MASK 0x10000 162 #define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_SHIFT 17 163 #define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_MASK 0x20000 164 #define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_SHIFT 18 165 #define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_MASK 0x40000 166 #define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_SHIFT 19 167 #define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 168 169 /* DCORE0_TPC0_CFG_FP16_FTZ_IN */ 170 #define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_SHIFT 0 171 #define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_MASK 0x1 172 173 /* DCORE0_TPC0_CFG_DCACHE_CFG */ 174 #define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_SHIFT 0 175 #define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_MASK 0x1 176 #define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_SHIFT 1 177 #define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_MASK 0x2 178 #define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_SHIFT 2 179 #define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_MASK 0x4 180 #define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_SHIFT 3 181 #define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_MASK 0x8 182 183 /* DCORE0_TPC0_CFG_E2E_CRDT_TOP */ 184 #define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_SHIFT 0 185 #define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_MASK 0x1 186 #define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_SHIFT 4 187 #define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_MASK 0x1FF0 188 189 /* DCORE0_TPC0_CFG_TPC_DCACHE_L0CD */ 190 #define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_SHIFT 0 191 #define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_MASK 0x1 192 193 /* DCORE0_TPC0_CFG_TPC_SB_L0CD */ 194 #define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_SHIFT 0 195 #define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_MASK 0x1 196 197 /* DCORE0_TPC0_CFG_CONV_ROUND_CSR */ 198 #define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_SHIFT 0 199 #define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_MASK 0x7 200 201 /* DCORE0_TPC0_CFG_TSB_OCCUPANCY */ 202 #define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_SHIFT 0 203 #define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_MASK 0xFFFFFFFF 204 205 /* DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT */ 206 #define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_SHIFT 0 207 #define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_MASK 0xFFF 208 #define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_SHIFT 12 209 #define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_MASK 0xFF000 210 211 /* DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT */ 212 #define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_SHIFT 0 213 #define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_MASK 0xFF 214 #define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_SHIFT 8 215 #define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_MASK 0xFF00 216 217 /* DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT */ 218 #define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_SHIFT 0 219 #define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_MASK 0xFFF 220 #define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_SHIFT 12 221 #define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_MASK 0xFFF000 222 223 /* DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT */ 224 #define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_SHIFT 0 225 #define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_MASK 0xFF 226 #define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_SHIFT 8 227 #define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_MASK 0xFFF00 228 229 /* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO */ 230 #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_SHIFT 0 231 #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF 232 233 /* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI */ 234 #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_SHIFT 0 235 #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF 236 237 /* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO */ 238 #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_SHIFT 0 239 #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF 240 241 /* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI */ 242 #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_SHIFT 0 243 #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF 244 245 /* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO */ 246 #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_SHIFT 0 247 #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF 248 249 /* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI */ 250 #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_SHIFT 0 251 #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF 252 253 /* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO */ 254 #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_SHIFT 0 255 #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF 256 257 /* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI */ 258 #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_SHIFT 0 259 #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF 260 261 /* DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM */ 262 #define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_SHIFT 0 263 #define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_MASK 0xFFFFFFFF 264 265 /* DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL */ 266 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_SHIFT 0 267 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_MASK 0x1 268 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_SHIFT 4 269 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_MASK 0x10 270 271 /* DCORE0_TPC0_CFG_TSB_CFG_MTRR */ 272 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_SHIFT 0 273 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_MASK 0x1 274 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_SHIFT 4 275 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_MASK 0x10 276 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_SHIFT 8 277 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_MASK 0xFFFF00 278 279 /* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO */ 280 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_SHIFT 0 281 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_MASK 0xFFFFFFFF 282 283 /* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI */ 284 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_SHIFT 0 285 #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_MASK 0xFF 286 287 /* DCORE0_TPC0_CFG_FP8_143_BIAS */ 288 #define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_SHIFT 0 289 #define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_MASK 0xF 290 291 /* DCORE0_TPC0_CFG_ROUND_CSR */ 292 #define DCORE0_TPC0_CFG_ROUND_CSR_MODE_SHIFT 0 293 #define DCORE0_TPC0_CFG_ROUND_CSR_MODE_MASK 0x7 294 295 /* DCORE0_TPC0_CFG_HB_PROT */ 296 #define DCORE0_TPC0_CFG_HB_PROT_AWPROT_SHIFT 0 297 #define DCORE0_TPC0_CFG_HB_PROT_AWPROT_MASK 0x7 298 #define DCORE0_TPC0_CFG_HB_PROT_ARPROT_SHIFT 3 299 #define DCORE0_TPC0_CFG_HB_PROT_ARPROT_MASK 0x38 300 301 /* DCORE0_TPC0_CFG_LB_PROT */ 302 #define DCORE0_TPC0_CFG_LB_PROT_AWPROT_SHIFT 0 303 #define DCORE0_TPC0_CFG_LB_PROT_AWPROT_MASK 0x7 304 #define DCORE0_TPC0_CFG_LB_PROT_ARPROT_SHIFT 3 305 #define DCORE0_TPC0_CFG_LB_PROT_ARPROT_MASK 0x38 306 307 /* DCORE0_TPC0_CFG_SEMAPHORE */ 308 #define DCORE0_TPC0_CFG_SEMAPHORE_V_SHIFT 0 309 #define DCORE0_TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF 310 311 /* DCORE0_TPC0_CFG_VFLAGS */ 312 #define DCORE0_TPC0_CFG_VFLAGS_V_SHIFT 0 313 #define DCORE0_TPC0_CFG_VFLAGS_V_MASK 0x7F 314 315 /* DCORE0_TPC0_CFG_SFLAGS */ 316 #define DCORE0_TPC0_CFG_SFLAGS_V_SHIFT 0 317 #define DCORE0_TPC0_CFG_SFLAGS_V_MASK 0x7F 318 319 /* DCORE0_TPC0_CFG_LFSR_POLYNOM */ 320 #define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0 321 #define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF 322 323 /* DCORE0_TPC0_CFG_STATUS */ 324 #define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 325 #define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 326 #define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 327 #define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 328 #define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3 329 #define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8 330 #define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_SHIFT 5 331 #define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK 0x20 332 #define DCORE0_TPC0_CFG_STATUS_QM_IDLE_SHIFT 6 333 #define DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK 0x40 334 #define DCORE0_TPC0_CFG_STATUS_QM_RDY_SHIFT 7 335 #define DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK 0x80 336 337 /* DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ 338 #define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 339 #define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF 340 341 /* DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE */ 342 #define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0 343 #define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF 344 345 /* DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH */ 346 #define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 347 #define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF 348 349 /* DCORE0_TPC0_CFG_TPC_CMD */ 350 #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 351 #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 352 #define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 353 #define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 354 #define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 355 #define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 356 #define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 357 #define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 358 #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 359 #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 360 #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 361 #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 362 #define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6 363 #define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40 364 365 /* DCORE0_TPC0_CFG_TPC_EXECUTE */ 366 #define DCORE0_TPC0_CFG_TPC_EXECUTE_V_SHIFT 0 367 #define DCORE0_TPC0_CFG_TPC_EXECUTE_V_MASK 0x1 368 369 /* DCORE0_TPC0_CFG_TPC_STALL */ 370 #define DCORE0_TPC0_CFG_TPC_STALL_V_SHIFT 0 371 #define DCORE0_TPC0_CFG_TPC_STALL_V_MASK 0x1 372 373 /* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ 374 #define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 375 #define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF 376 377 /* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ 378 #define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 379 #define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF 380 381 /* DCORE0_TPC0_CFG_RD_RATE_LIMIT */ 382 #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 0 383 #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x1 384 #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 1 385 #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE 386 #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 9 387 #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 388 389 /* DCORE0_TPC0_CFG_WR_RATE_LIMIT */ 390 #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 0 391 #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x1 392 #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 1 393 #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE 394 #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 9 395 #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 396 397 /* DCORE0_TPC0_CFG_MSS_CONFIG */ 398 #define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0 399 #define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF 400 #define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4 401 #define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0 402 #define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 403 #define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 404 #define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 405 #define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 406 #define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11 407 #define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800 408 409 /* DCORE0_TPC0_CFG_TPC_INTR_CAUSE */ 410 #define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0 411 #define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFFFFF 412 413 /* DCORE0_TPC0_CFG_TPC_INTR_MASK */ 414 #define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0 415 #define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFFFFF 416 417 /* DCORE0_TPC0_CFG_WQ_CREDITS */ 418 #define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 0 419 #define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF 420 #define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 4 421 #define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x70 422 423 /* DCORE0_TPC0_CFG_OPCODE_EXEC */ 424 #define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 0 425 #define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F 426 #define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 7 427 #define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x80 428 #define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 8 429 #define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F00 430 #define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 15 431 #define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x8000 432 #define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 16 433 #define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F0000 434 #define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 23 435 #define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x800000 436 #define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 24 437 #define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F000000 438 #define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 31 439 #define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x80000000 440 441 /* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */ 442 #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0 443 #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF 444 445 /* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */ 446 #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0 447 #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF 448 449 /* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */ 450 #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0 451 #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF 452 453 /* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */ 454 #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0 455 #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF 456 457 /* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */ 458 #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0 459 #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF 460 461 /* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */ 462 #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0 463 #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF 464 465 /* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */ 466 #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0 467 #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF 468 469 /* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */ 470 #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0 471 #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF 472 473 /* DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE */ 474 #define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 0 475 #define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF 476 #define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 16 477 #define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000 478 479 /* DCORE0_TPC0_CFG_TSB_CFG */ 480 #define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_SHIFT 0 481 #define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_MASK 0x1 482 #define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 1 483 #define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE 484 #define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_SHIFT 17 485 #define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_MASK 0x20000 486 487 /* DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR */ 488 #define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 0 489 #define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF 490 491 /* DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR */ 492 #define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 0 493 #define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF 494 #define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 16 495 #define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0x1FF0000 496 497 /* DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR */ 498 #define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 0 499 #define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF 500 501 /* DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR */ 502 #define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 0 503 #define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF 504 505 /* DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR */ 506 #define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 0 507 #define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF 508 509 #endif /* ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ */ 510