1 /* 2 * Copyright (C) 2005 - 2011 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 /********* Mailbox door bell *************/ 19 /* Used for driver communication with the FW. 20 * The software must write this register twice to post any command. First, 21 * it writes the register with hi=1 and the upper bits of the physical address 22 * for the MAILBOX structure. Software must poll the ready bit until this 23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower 24 * bits in the address. It must poll the ready bit until the command is 25 * complete. Upon completion, the MAILBOX will contain a valid completion 26 * queue entry. 27 */ 28 #define MPU_MAILBOX_DB_OFFSET 0x160 29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */ 30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */ 31 32 #define MPU_EP_CONTROL 0 33 34 /********** MPU semphore ******************/ 35 #define MPU_EP_SEMAPHORE_OFFSET 0xac 36 #define MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET 0x400 37 #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF 38 #define EP_SEMAPHORE_POST_ERR_MASK 0x1 39 #define EP_SEMAPHORE_POST_ERR_SHIFT 31 40 41 /* MPU semphore POST stage values */ 42 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */ 43 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */ 44 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */ 45 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */ 46 47 48 /* Lancer SLIPORT_CONTROL SLIPORT_STATUS registers */ 49 #define SLIPORT_STATUS_OFFSET 0x404 50 #define SLIPORT_CONTROL_OFFSET 0x408 51 #define SLIPORT_ERROR1_OFFSET 0x40C 52 #define SLIPORT_ERROR2_OFFSET 0x410 53 54 #define SLIPORT_STATUS_ERR_MASK 0x80000000 55 #define SLIPORT_STATUS_RN_MASK 0x01000000 56 #define SLIPORT_STATUS_RDY_MASK 0x00800000 57 58 59 #define SLI_PORT_CONTROL_IP_MASK 0x08000000 60 61 /********* Memory BAR register ************/ 62 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc 63 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt 64 * Disable" may still globally block interrupts in addition to individual 65 * interrupt masks; a mechanism for the device driver to block all interrupts 66 * atomically without having to arbitrate for the PCI Interrupt Disable bit 67 * with the OS. 68 */ 69 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ 70 71 /********* Power management (WOL) **********/ 72 #define PCICFG_PM_CONTROL_OFFSET 0x44 73 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */ 74 75 /********* Online Control Registers *******/ 76 #define PCICFG_ONLINE0 0xB0 77 #define PCICFG_ONLINE1 0xB4 78 79 /********* UE Status and Mask Registers ***/ 80 #define PCICFG_UE_STATUS_LOW 0xA0 81 #define PCICFG_UE_STATUS_HIGH 0xA4 82 #define PCICFG_UE_STATUS_LOW_MASK 0xA8 83 #define PCICFG_UE_STATUS_HI_MASK 0xAC 84 85 /******** SLI_INTF ***********************/ 86 #define SLI_INTF_REG_OFFSET 0x58 87 #define SLI_INTF_VALID_MASK 0xE0000000 88 #define SLI_INTF_VALID 0xC0000000 89 #define SLI_INTF_HINT2_MASK 0x1F000000 90 #define SLI_INTF_HINT2_SHIFT 24 91 #define SLI_INTF_HINT1_MASK 0x00FF0000 92 #define SLI_INTF_HINT1_SHIFT 16 93 #define SLI_INTF_FAMILY_MASK 0x00000F00 94 #define SLI_INTF_FAMILY_SHIFT 8 95 #define SLI_INTF_IF_TYPE_MASK 0x0000F000 96 #define SLI_INTF_IF_TYPE_SHIFT 12 97 #define SLI_INTF_REV_MASK 0x000000F0 98 #define SLI_INTF_REV_SHIFT 4 99 #define SLI_INTF_FT_MASK 0x00000001 100 101 102 /* SLI family */ 103 #define BE_SLI_FAMILY 0x0 104 #define LANCER_A0_SLI_FAMILY 0xA 105 106 107 /********* ISR0 Register offset **********/ 108 #define CEV_ISR0_OFFSET 0xC18 109 #define CEV_ISR_SIZE 4 110 111 /********* Event Q door bell *************/ 112 #define DB_EQ_OFFSET DB_CQ_OFFSET 113 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ 114 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */ 115 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */ 116 117 /* Clear the interrupt for this eq */ 118 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ 119 /* Must be 1 */ 120 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ 121 /* Number of event entries processed */ 122 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 123 /* Rearm bit */ 124 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ 125 126 /********* Compl Q door bell *************/ 127 #define DB_CQ_OFFSET 0x120 128 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 129 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */ 130 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14 131 placing at 11-15 */ 132 133 /* Number of event entries processed */ 134 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 135 /* Rearm bit */ 136 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ 137 138 /********** TX ULP door bell *************/ 139 #define DB_TXULP1_OFFSET 0x60 140 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */ 141 /* Number of tx entries posted */ 142 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ 143 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */ 144 145 /********** RQ(erx) door bell ************/ 146 #define DB_RQ_OFFSET 0x100 147 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 148 /* Number of rx frags posted */ 149 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */ 150 151 /********** MCC door bell ************/ 152 #define DB_MCCQ_OFFSET 0x140 153 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */ 154 /* Number of entries posted */ 155 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ 156 157 /********** SRIOV VF PCICFG OFFSET ********/ 158 #define SRIOV_VF_PCICFG_OFFSET (4096) 159 160 /********** FAT TABLE ********/ 161 #define RETRIEVE_FAT 0 162 #define QUERY_FAT 1 163 164 /* Flashrom related descriptors */ 165 #define IMAGE_TYPE_FIRMWARE 160 166 #define IMAGE_TYPE_BOOTCODE 224 167 #define IMAGE_TYPE_OPTIONROM 32 168 169 #define NUM_FLASHDIR_ENTRIES 32 170 171 #define IMG_TYPE_ISCSI_ACTIVE 0 172 #define IMG_TYPE_REDBOOT 1 173 #define IMG_TYPE_BIOS 2 174 #define IMG_TYPE_PXE_BIOS 3 175 #define IMG_TYPE_FCOE_BIOS 8 176 #define IMG_TYPE_ISCSI_BACKUP 9 177 #define IMG_TYPE_FCOE_FW_ACTIVE 10 178 #define IMG_TYPE_FCOE_FW_BACKUP 11 179 #define IMG_TYPE_NCSI_FW 13 180 #define IMG_TYPE_PHY_FW 99 181 #define TN_8022 13 182 183 #define ILLEGAL_IOCTL_REQ 2 184 #define FLASHROM_OPER_PHY_FLASH 9 185 #define FLASHROM_OPER_PHY_SAVE 10 186 #define FLASHROM_OPER_FLASH 1 187 #define FLASHROM_OPER_SAVE 2 188 #define FLASHROM_OPER_REPORT 4 189 190 #define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image size */ 191 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM image sz */ 192 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */ 193 #define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max firmware image size */ 194 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM image sz */ 195 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */ 196 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144) 197 #define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144 198 199 #define FLASH_NCSI_MAGIC (0x16032009) 200 #define FLASH_NCSI_DISABLED (0) 201 #define FLASH_NCSI_ENABLED (1) 202 203 #define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000) 204 205 /* Offsets for components on Flash. */ 206 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576) 207 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296) 208 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016) 209 #define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736) 210 #define FLASH_iSCSI_BIOS_START_g2 (7340032) 211 #define FLASH_PXE_BIOS_START_g2 (7864320) 212 #define FLASH_FCoE_BIOS_START_g2 (524288) 213 #define FLASH_REDBOOT_START_g2 (0) 214 215 #define FLASH_NCSI_START_g3 (15990784) 216 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152) 217 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304) 218 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456) 219 #define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608) 220 #define FLASH_iSCSI_BIOS_START_g3 (12582912) 221 #define FLASH_PXE_BIOS_START_g3 (13107200) 222 #define FLASH_FCoE_BIOS_START_g3 (13631488) 223 #define FLASH_REDBOOT_START_g3 (262144) 224 #define FLASH_PHY_FW_START_g3 1310720 225 226 /************* Rx Packet Type Encoding **************/ 227 #define BE_UNICAST_PACKET 0 228 #define BE_MULTICAST_PACKET 1 229 #define BE_BROADCAST_PACKET 2 230 #define BE_RSVD_PACKET 3 231 232 /* 233 * BE descriptors: host memory data structures whose formats 234 * are hardwired in BE silicon. 235 */ 236 /* Event Queue Descriptor */ 237 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */ 238 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */ 239 #define EQ_ENTRY_RES_ID_SHIFT 16 240 241 struct be_eq_entry { 242 u32 evt; 243 }; 244 245 /* TX Queue Descriptor */ 246 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF 247 struct be_eth_wrb { 248 u32 frag_pa_hi; /* dword 0 */ 249 u32 frag_pa_lo; /* dword 1 */ 250 u32 rsvd0; /* dword 2 */ 251 u32 frag_len; /* dword 3: bits 0 - 15 */ 252 } __packed; 253 254 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the 255 * actual structure is defined as a byte : used to calculate 256 * offset/shift/mask of each field */ 257 struct amap_eth_hdr_wrb { 258 u8 rsvd0[32]; /* dword 0 */ 259 u8 rsvd1[32]; /* dword 1 */ 260 u8 complete; /* dword 2 */ 261 u8 event; 262 u8 crc; 263 u8 forward; 264 u8 lso6; 265 u8 mgmt; 266 u8 ipcs; 267 u8 udpcs; 268 u8 tcpcs; 269 u8 lso; 270 u8 vlan; 271 u8 gso[2]; 272 u8 num_wrb[5]; 273 u8 lso_mss[14]; 274 u8 len[16]; /* dword 3 */ 275 u8 vlan_tag[16]; 276 } __packed; 277 278 struct be_eth_hdr_wrb { 279 u32 dw[4]; 280 }; 281 282 /* TX Compl Queue Descriptor */ 283 284 /* Pseudo amap definition for eth_tx_compl in which each bit of the 285 * actual structure is defined as a byte: used to calculate 286 * offset/shift/mask of each field */ 287 struct amap_eth_tx_compl { 288 u8 wrb_index[16]; /* dword 0 */ 289 u8 ct[2]; /* dword 0 */ 290 u8 port[2]; /* dword 0 */ 291 u8 rsvd0[8]; /* dword 0 */ 292 u8 status[4]; /* dword 0 */ 293 u8 user_bytes[16]; /* dword 1 */ 294 u8 nwh_bytes[8]; /* dword 1 */ 295 u8 lso; /* dword 1 */ 296 u8 cast_enc[2]; /* dword 1 */ 297 u8 rsvd1[5]; /* dword 1 */ 298 u8 rsvd2[32]; /* dword 2 */ 299 u8 pkts[16]; /* dword 3 */ 300 u8 ringid[11]; /* dword 3 */ 301 u8 hash_val[4]; /* dword 3 */ 302 u8 valid; /* dword 3 */ 303 } __packed; 304 305 struct be_eth_tx_compl { 306 u32 dw[4]; 307 }; 308 309 /* RX Queue Descriptor */ 310 struct be_eth_rx_d { 311 u32 fragpa_hi; 312 u32 fragpa_lo; 313 }; 314 315 /* RX Compl Queue Descriptor */ 316 317 /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which 318 * each bit of the actual structure is defined as a byte: used to calculate 319 * offset/shift/mask of each field */ 320 struct amap_eth_rx_compl_v0 { 321 u8 vlan_tag[16]; /* dword 0 */ 322 u8 pktsize[14]; /* dword 0 */ 323 u8 port; /* dword 0 */ 324 u8 ip_opt; /* dword 0 */ 325 u8 err; /* dword 1 */ 326 u8 rsshp; /* dword 1 */ 327 u8 ipf; /* dword 1 */ 328 u8 tcpf; /* dword 1 */ 329 u8 udpf; /* dword 1 */ 330 u8 ipcksm; /* dword 1 */ 331 u8 l4_cksm; /* dword 1 */ 332 u8 ip_version; /* dword 1 */ 333 u8 macdst[6]; /* dword 1 */ 334 u8 vtp; /* dword 1 */ 335 u8 rsvd0; /* dword 1 */ 336 u8 fragndx[10]; /* dword 1 */ 337 u8 ct[2]; /* dword 1 */ 338 u8 sw; /* dword 1 */ 339 u8 numfrags[3]; /* dword 1 */ 340 u8 rss_flush; /* dword 2 */ 341 u8 cast_enc[2]; /* dword 2 */ 342 u8 vtm; /* dword 2 */ 343 u8 rss_bank; /* dword 2 */ 344 u8 rsvd1[23]; /* dword 2 */ 345 u8 lro_pkt; /* dword 2 */ 346 u8 rsvd2[2]; /* dword 2 */ 347 u8 valid; /* dword 2 */ 348 u8 rsshash[32]; /* dword 3 */ 349 } __packed; 350 351 /* Pseudo amap definition for BE3 native mode eth_rx_compl in which 352 * each bit of the actual structure is defined as a byte: used to calculate 353 * offset/shift/mask of each field */ 354 struct amap_eth_rx_compl_v1 { 355 u8 vlan_tag[16]; /* dword 0 */ 356 u8 pktsize[14]; /* dword 0 */ 357 u8 vtp; /* dword 0 */ 358 u8 ip_opt; /* dword 0 */ 359 u8 err; /* dword 1 */ 360 u8 rsshp; /* dword 1 */ 361 u8 ipf; /* dword 1 */ 362 u8 tcpf; /* dword 1 */ 363 u8 udpf; /* dword 1 */ 364 u8 ipcksm; /* dword 1 */ 365 u8 l4_cksm; /* dword 1 */ 366 u8 ip_version; /* dword 1 */ 367 u8 macdst[7]; /* dword 1 */ 368 u8 rsvd0; /* dword 1 */ 369 u8 fragndx[10]; /* dword 1 */ 370 u8 ct[2]; /* dword 1 */ 371 u8 sw; /* dword 1 */ 372 u8 numfrags[3]; /* dword 1 */ 373 u8 rss_flush; /* dword 2 */ 374 u8 cast_enc[2]; /* dword 2 */ 375 u8 vtm; /* dword 2 */ 376 u8 rss_bank; /* dword 2 */ 377 u8 port[2]; /* dword 2 */ 378 u8 vntagp; /* dword 2 */ 379 u8 header_len[8]; /* dword 2 */ 380 u8 header_split[2]; /* dword 2 */ 381 u8 rsvd1[13]; /* dword 2 */ 382 u8 valid; /* dword 2 */ 383 u8 rsshash[32]; /* dword 3 */ 384 } __packed; 385 386 struct be_eth_rx_compl { 387 u32 dw[4]; 388 }; 389 390 struct mgmt_hba_attribs { 391 u8 flashrom_version_string[32]; 392 u8 manufacturer_name[32]; 393 u32 supported_modes; 394 u32 rsvd0[3]; 395 u8 ncsi_ver_string[12]; 396 u32 default_extended_timeout; 397 u8 controller_model_number[32]; 398 u8 controller_description[64]; 399 u8 controller_serial_number[32]; 400 u8 ip_version_string[32]; 401 u8 firmware_version_string[32]; 402 u8 bios_version_string[32]; 403 u8 redboot_version_string[32]; 404 u8 driver_version_string[32]; 405 u8 fw_on_flash_version_string[32]; 406 u32 functionalities_supported; 407 u16 max_cdblength; 408 u8 asic_revision; 409 u8 generational_guid[16]; 410 u8 hba_port_count; 411 u16 default_link_down_timeout; 412 u8 iscsi_ver_min_max; 413 u8 multifunction_device; 414 u8 cache_valid; 415 u8 hba_status; 416 u8 max_domains_supported; 417 u8 phy_port; 418 u32 firmware_post_status; 419 u32 hba_mtu[8]; 420 u32 rsvd1[4]; 421 }; 422 423 struct mgmt_controller_attrib { 424 struct mgmt_hba_attribs hba_attribs; 425 u16 pci_vendor_id; 426 u16 pci_device_id; 427 u16 pci_sub_vendor_id; 428 u16 pci_sub_system_id; 429 u8 pci_bus_number; 430 u8 pci_device_number; 431 u8 pci_function_number; 432 u8 interface_type; 433 u64 unique_identifier; 434 u32 rsvd0[5]; 435 }; 436 437 struct controller_id { 438 u32 vendor; 439 u32 device; 440 u32 subvendor; 441 u32 subdevice; 442 }; 443 444 struct flash_comp { 445 unsigned long offset; 446 int optype; 447 int size; 448 }; 449 450 struct image_hdr { 451 u32 imageid; 452 u32 imageoffset; 453 u32 imagelength; 454 u32 image_checksum; 455 u8 image_version[32]; 456 }; 457 struct flash_file_hdr_g2 { 458 u8 sign[32]; 459 u32 cksum; 460 u32 antidote; 461 struct controller_id cont_id; 462 u32 file_len; 463 u32 chunk_num; 464 u32 total_chunks; 465 u32 num_imgs; 466 u8 build[24]; 467 }; 468 469 struct flash_file_hdr_g3 { 470 u8 sign[52]; 471 u8 ufi_version[4]; 472 u32 file_len; 473 u32 cksum; 474 u32 antidote; 475 u32 num_imgs; 476 u8 build[24]; 477 u8 rsvd[32]; 478 }; 479 480 struct flash_section_hdr { 481 u32 format_rev; 482 u32 cksum; 483 u32 antidote; 484 u32 build_no; 485 u8 id_string[64]; 486 u32 active_entry_mask; 487 u32 valid_entry_mask; 488 u32 org_content_mask; 489 u32 rsvd0; 490 u32 rsvd1; 491 u32 rsvd2; 492 u32 rsvd3; 493 u32 rsvd4; 494 }; 495 496 struct flash_section_entry { 497 u32 type; 498 u32 offset; 499 u32 pad_size; 500 u32 image_size; 501 u32 cksum; 502 u32 entry_point; 503 u32 rsvd0; 504 u32 rsvd1; 505 u8 ver_data[32]; 506 }; 507 508 struct flash_section_info { 509 u8 cookie[32]; 510 struct flash_section_hdr fsec_hdr; 511 struct flash_section_entry fsec_entry[32]; 512 }; 513