1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * TI DaVinci Audio definitions
4  */
5 #ifndef __ASM_ARCH_DAVINCI_ASP_H
6 #define __ASM_ARCH_DAVINCI_ASP_H
7 
8 /* Bases of dm644x and dm355 register banks */
9 #define DAVINCI_ASP0_BASE	0x01E02000
10 #define DAVINCI_ASP1_BASE	0x01E04000
11 
12 /* Bases of dm365 register banks */
13 #define DAVINCI_DM365_ASP0_BASE	0x01D02000
14 
15 /* Bases of dm646x register banks */
16 #define DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
17 #define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
18 
19 /* Bases of da850/da830 McASP0  register banks */
20 #define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
21 
22 /* Bases of da830 McASP1 register banks */
23 #define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
24 
25 /* Bases of da830 McASP2 register banks */
26 #define DAVINCI_DA830_MCASP2_REG_BASE	0x01D08000
27 
28 /* EDMA channels of dm644x and dm355 */
29 #define DAVINCI_DMA_ASP0_TX	2
30 #define DAVINCI_DMA_ASP0_RX	3
31 #define DAVINCI_DMA_ASP1_TX	8
32 #define DAVINCI_DMA_ASP1_RX	9
33 
34 /* EDMA channels of dm646x */
35 #define DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
36 #define DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
37 #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
38 
39 /* EDMA channels of da850/da830 McASP0 */
40 #define DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
41 #define DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
42 
43 /* EDMA channels of da830 McASP1 */
44 #define DAVINCI_DA830_DMA_MCASP1_AREVT	2
45 #define DAVINCI_DA830_DMA_MCASP1_AXEVT	3
46 
47 /* EDMA channels of da830 McASP2 */
48 #define DAVINCI_DA830_DMA_MCASP2_AREVT	4
49 #define DAVINCI_DA830_DMA_MCASP2_AXEVT	5
50 
51 /* Interrupts */
52 #define DAVINCI_ASP0_RX_INT	DAVINCI_INTC_IRQ(IRQ_MBRINT)
53 #define DAVINCI_ASP0_TX_INT	DAVINCI_INTC_IRQ(IRQ_MBXINT)
54 #define DAVINCI_ASP1_RX_INT	DAVINCI_INTC_IRQ(IRQ_MBRINT)
55 #define DAVINCI_ASP1_TX_INT	DAVINCI_INTC_IRQ(IRQ_MBXINT)
56 
57 #endif /* __ASM_ARCH_DAVINCI_ASP_H */
58