1 /*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #ifndef __PINCTRL_SUNXI_H
14 #define __PINCTRL_SUNXI_H
15
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
18
19 #define PA_BASE 0
20 #define PB_BASE 32
21 #define PC_BASE 64
22 #define PD_BASE 96
23 #define PE_BASE 128
24 #define PF_BASE 160
25 #define PG_BASE 192
26 #define PH_BASE 224
27 #define PI_BASE 256
28 #define PL_BASE 352
29 #define PM_BASE 384
30 #define PN_BASE 416
31
32 #define SUNXI_PINCTRL_PIN(bank, pin) \
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
34
35 #define SUNXI_PIN_NAME_MAX_LEN 5
36
37 #define BANK_MEM_SIZE 0x24
38 #define MUX_REGS_OFFSET 0x0
39 #define MUX_FIELD_WIDTH 4
40 #define DATA_REGS_OFFSET 0x10
41 #define DATA_FIELD_WIDTH 1
42 #define DLEVEL_REGS_OFFSET 0x14
43 #define DLEVEL_FIELD_WIDTH 2
44 #define PULL_REGS_OFFSET 0x1c
45 #define PULL_FIELD_WIDTH 2
46
47 #define D1_BANK_MEM_SIZE 0x30
48 #define D1_DLEVEL_FIELD_WIDTH 4
49 #define D1_PULL_REGS_OFFSET 0x24
50
51 #define PINS_PER_BANK 32
52
53 #define IRQ_PER_BANK 32
54
55 #define IRQ_CFG_REG 0x200
56 #define IRQ_CFG_IRQ_PER_REG 8
57 #define IRQ_CFG_IRQ_BITS 4
58 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
59 #define IRQ_CTRL_REG 0x210
60 #define IRQ_CTRL_IRQ_PER_REG 32
61 #define IRQ_CTRL_IRQ_BITS 1
62 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
63 #define IRQ_STATUS_REG 0x214
64 #define IRQ_STATUS_IRQ_PER_REG 32
65 #define IRQ_STATUS_IRQ_BITS 1
66 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
67
68 #define IRQ_DEBOUNCE_REG 0x218
69
70 #define IRQ_MEM_SIZE 0x20
71
72 #define IRQ_EDGE_RISING 0x00
73 #define IRQ_EDGE_FALLING 0x01
74 #define IRQ_LEVEL_HIGH 0x02
75 #define IRQ_LEVEL_LOW 0x03
76 #define IRQ_EDGE_BOTH 0x04
77
78 #define GRP_CFG_REG 0x300
79
80 #define IO_BIAS_MASK GENMASK(3, 0)
81
82 #define SUN4I_FUNC_INPUT 0
83 #define SUN4I_FUNC_IRQ 6
84
85 #define PINCTRL_SUN5I_A10S BIT(1)
86 #define PINCTRL_SUN5I_A13 BIT(2)
87 #define PINCTRL_SUN5I_GR8 BIT(3)
88 #define PINCTRL_SUN6I_A31 BIT(4)
89 #define PINCTRL_SUN6I_A31S BIT(5)
90 #define PINCTRL_SUN4I_A10 BIT(6)
91 #define PINCTRL_SUN7I_A20 BIT(7)
92 #define PINCTRL_SUN8I_R40 BIT(8)
93 #define PINCTRL_SUN8I_V3 BIT(9)
94 #define PINCTRL_SUN8I_V3S BIT(10)
95 /* Variants below here have an updated register layout. */
96 #define PINCTRL_SUN20I_D1 BIT(11)
97
98 #define PIO_POW_MOD_SEL_REG 0x340
99 #define PIO_POW_MOD_CTL_REG 0x344
100
101 enum sunxi_desc_bias_voltage {
102 BIAS_VOLTAGE_NONE,
103 /*
104 * Bias voltage configuration is done through
105 * Pn_GRP_CONFIG registers, as seen on A80 SoC.
106 */
107 BIAS_VOLTAGE_GRP_CONFIG,
108 /*
109 * Bias voltage is set through PIO_POW_MOD_SEL_REG
110 * register, as seen on H6 SoC, for example.
111 */
112 BIAS_VOLTAGE_PIO_POW_MODE_SEL,
113 /*
114 * Bias voltage is set through PIO_POW_MOD_SEL_REG
115 * and PIO_POW_MOD_CTL_REG register, as seen on
116 * A100 and D1 SoC, for example.
117 */
118 BIAS_VOLTAGE_PIO_POW_MODE_CTL,
119 };
120
121 struct sunxi_desc_function {
122 unsigned long variant;
123 const char *name;
124 u8 muxval;
125 u8 irqbank;
126 u8 irqnum;
127 };
128
129 struct sunxi_desc_pin {
130 struct pinctrl_pin_desc pin;
131 unsigned long variant;
132 struct sunxi_desc_function *functions;
133 };
134
135 struct sunxi_pinctrl_desc {
136 const struct sunxi_desc_pin *pins;
137 int npins;
138 unsigned pin_base;
139 unsigned irq_banks;
140 const unsigned int *irq_bank_map;
141 bool irq_read_needs_mux;
142 bool disable_strict_mode;
143 enum sunxi_desc_bias_voltage io_bias_cfg_variant;
144 };
145
146 struct sunxi_pinctrl_function {
147 const char *name;
148 const char **groups;
149 unsigned ngroups;
150 };
151
152 struct sunxi_pinctrl_group {
153 const char *name;
154 unsigned pin;
155 };
156
157 struct sunxi_pinctrl_regulator {
158 struct regulator *regulator;
159 refcount_t refcount;
160 };
161
162 struct sunxi_pinctrl {
163 void __iomem *membase;
164 struct gpio_chip *chip;
165 const struct sunxi_pinctrl_desc *desc;
166 struct device *dev;
167 struct sunxi_pinctrl_regulator regulators[9];
168 struct irq_domain *domain;
169 struct sunxi_pinctrl_function *functions;
170 unsigned nfunctions;
171 struct sunxi_pinctrl_group *groups;
172 unsigned ngroups;
173 int *irq;
174 unsigned *irq_array;
175 raw_spinlock_t lock;
176 struct pinctrl_dev *pctl_dev;
177 unsigned long variant;
178 u32 bank_mem_size;
179 u32 pull_regs_offset;
180 u32 dlevel_field_width;
181 };
182
183 #define SUNXI_PIN(_pin, ...) \
184 { \
185 .pin = _pin, \
186 .functions = (struct sunxi_desc_function[]){ \
187 __VA_ARGS__, { } }, \
188 }
189
190 #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
191 { \
192 .pin = _pin, \
193 .variant = _variant, \
194 .functions = (struct sunxi_desc_function[]){ \
195 __VA_ARGS__, { } }, \
196 }
197
198 #define SUNXI_FUNCTION(_val, _name) \
199 { \
200 .name = _name, \
201 .muxval = _val, \
202 }
203
204 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
205 { \
206 .name = _name, \
207 .muxval = _val, \
208 .variant = _variant, \
209 }
210
211 #define SUNXI_FUNCTION_IRQ(_val, _irq) \
212 { \
213 .name = "irq", \
214 .muxval = _val, \
215 .irqnum = _irq, \
216 }
217
218 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
219 { \
220 .name = "irq", \
221 .muxval = _val, \
222 .irqbank = _bank, \
223 .irqnum = _irq, \
224 }
225
sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc * desc,u8 bank)226 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
227 {
228 if (!desc->irq_bank_map)
229 return bank;
230 else
231 return desc->irq_bank_map[bank];
232 }
233
sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)234 static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
235 u16 irq)
236 {
237 u8 bank = irq / IRQ_PER_BANK;
238 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
239
240 return IRQ_CFG_REG +
241 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
242 }
243
sunxi_irq_cfg_offset(u16 irq)244 static inline u32 sunxi_irq_cfg_offset(u16 irq)
245 {
246 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
247 return irq_num * IRQ_CFG_IRQ_BITS;
248 }
249
sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)250 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
251 {
252 return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
253 }
254
sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)255 static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
256 u16 irq)
257 {
258 u8 bank = irq / IRQ_PER_BANK;
259
260 return sunxi_irq_ctrl_reg_from_bank(desc, bank);
261 }
262
sunxi_irq_ctrl_offset(u16 irq)263 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
264 {
265 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
266 return irq_num * IRQ_CTRL_IRQ_BITS;
267 }
268
sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)269 static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
270 {
271 return IRQ_DEBOUNCE_REG +
272 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
273 }
274
sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)275 static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
276 {
277 return IRQ_STATUS_REG +
278 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
279 }
280
sunxi_irq_status_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)281 static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
282 u16 irq)
283 {
284 u8 bank = irq / IRQ_PER_BANK;
285
286 return sunxi_irq_status_reg_from_bank(desc, bank);
287 }
288
sunxi_irq_status_offset(u16 irq)289 static inline u32 sunxi_irq_status_offset(u16 irq)
290 {
291 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
292 return irq_num * IRQ_STATUS_IRQ_BITS;
293 }
294
sunxi_grp_config_reg(u16 pin)295 static inline u32 sunxi_grp_config_reg(u16 pin)
296 {
297 u8 bank = pin / PINS_PER_BANK;
298
299 return GRP_CFG_REG + bank * 0x4;
300 }
301
302 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
303 const struct sunxi_pinctrl_desc *desc,
304 unsigned long variant);
305
306 #define sunxi_pinctrl_init(_dev, _desc) \
307 sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
308
309 #endif /* __PINCTRL_SUNXI_H */
310