1 /*********************************************************************** 2 ;* File Name : TMSCSIM.H * 3 ;* TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter * 4 ;* Device Driver * 5 ;***********************************************************************/ 6 /* $Id: tmscsim.h,v 2.15.2.3 2000/11/17 20:52:27 garloff Exp $ */ 7 8 #ifndef _TMSCSIM_H 9 #define _TMSCSIM_H 10 11 #include <linux/types.h> 12 #include <linux/config.h> 13 14 #define SCSI_IRQ_NONE 255 15 16 #define MAX_ADAPTER_NUM 4 17 #define MAX_SG_LIST_BUF 16 /* Not used */ 18 #define MAX_CMD_PER_LUN 32 19 #define MAX_CMD_QUEUE MAX_CMD_PER_LUN+MAX_CMD_PER_LUN/2+1 20 #define MAX_SCSI_ID 8 21 #define MAX_SRB_CNT MAX_CMD_QUEUE+1 /* Max number of started commands */ 22 23 #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */ 24 25 #define END_SCAN 2 26 27 typedef u8 UCHAR; /* 8 bits */ 28 typedef u16 USHORT; /* 16 bits */ 29 typedef u32 UINT; /* 32 bits */ 30 typedef unsigned long ULONG; /* 32/64 bits */ 31 32 typedef UCHAR *PUCHAR; 33 typedef USHORT *PUSHORT; 34 typedef UINT *PUINT; 35 typedef ULONG *PULONG; 36 typedef Scsi_Host_Template *PSHT; 37 typedef struct Scsi_Host *PSH; 38 typedef Scsi_Device *PSCSIDEV; 39 typedef Scsi_Cmnd *PSCSICMD; 40 typedef void *PVOID; 41 typedef struct scatterlist *PSGL, SGL; 42 43 44 /*;-----------------------------------------------------------------------*/ 45 typedef struct _SyncMsg 46 { 47 UCHAR ExtendMsg; 48 UCHAR ExtMsgLen; 49 UCHAR SyncXferReq; 50 UCHAR Period; 51 UCHAR ReqOffset; 52 } SyncMsg; 53 /*;-----------------------------------------------------------------------*/ 54 typedef struct _Capacity 55 { 56 ULONG BlockCount; 57 ULONG BlockLength; 58 } Capacity; 59 /*;-----------------------------------------------------------------------*/ 60 typedef struct _SGentry 61 { 62 ULONG SGXferDataPtr; 63 ULONG SGXferDataLen; 64 } SGentry; 65 66 typedef struct _SGentry1 67 { 68 ULONG SGXLen; 69 ULONG SGXPtr; 70 } SGentry1, *PSGE; 71 72 73 /* 74 ;----------------------------------------------------------------------- 75 ; SCSI Request Block 76 ;----------------------------------------------------------------------- 77 */ 78 struct _SRB 79 { 80 //UCHAR CmdBlock[12]; 81 82 struct _SRB *pNextSRB; 83 struct _DCB *pSRBDCB; 84 PSCSICMD pcmd; 85 PSGL pSegmentList; 86 87 /* 0x10: */ 88 SGL Segmentx; /* make a one entry of S/G list table */ 89 90 /* 0x1c: */ 91 ULONG SGBusAddr; /*;a segment starting address as seen by AM53C974A*/ 92 ULONG SGToBeXferLen; /*; to be xfer length */ 93 ULONG TotalXferredLen; 94 ULONG SavedTotXLen; 95 UINT SRBState; 96 97 /* 0x30: */ 98 UCHAR SRBStatus; 99 UCHAR SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */ 100 /*; b4-settimeout,b5-Residual valid */ 101 UCHAR AdaptStatus; 102 UCHAR TargetStatus; 103 104 UCHAR ScsiPhase; 105 UCHAR TagNumber; 106 UCHAR SGIndex; 107 UCHAR SGcount; 108 109 /* 0x38: */ 110 UCHAR MsgCnt; 111 UCHAR EndMessage; 112 UCHAR RetryCnt; 113 UCHAR SavedSGCount; 114 115 ULONG Saved_Ptr; 116 117 /* 0x40: */ 118 UCHAR MsgInBuf[6]; 119 UCHAR MsgOutBuf[6]; 120 121 //UCHAR IORBFlag; /*;81h-Reset, 2-retry */ 122 /* 0x4c: */ 123 }; 124 125 126 typedef struct _SRB DC390_SRB, *PSRB; 127 128 /* 129 ;----------------------------------------------------------------------- 130 ; Device Control Block 131 ;----------------------------------------------------------------------- 132 */ 133 struct _DCB 134 { 135 struct _DCB *pNextDCB; 136 struct _ACB *pDCBACB; 137 138 /* Aborted Commands */ 139 //PSCSICMD AboIORBhead; 140 //PSCSICMD AboIORBtail; 141 //ULONG AboIORBcnt; 142 143 /* 0x08: */ 144 /* Queued SRBs */ 145 PSRB pWaitingSRB; 146 PSRB pWaitLast; 147 PSRB pGoingSRB; 148 PSRB pGoingLast; 149 PSRB pActiveSRB; 150 UCHAR WaitSRBCnt; /* Not used */ 151 UCHAR GoingSRBCnt; 152 153 UCHAR DevType; 154 UCHAR MaxCommand; 155 156 /* 0x20: */ 157 UINT TagMask; 158 159 UCHAR TargetID; /*; SCSI Target ID (SCSI Only) */ 160 UCHAR TargetLUN; /*; SCSI Log. Unit (SCSI Only) */ 161 UCHAR DevMode; 162 UCHAR DCBFlag; 163 164 UCHAR CtrlR1; 165 UCHAR CtrlR3; 166 UCHAR CtrlR4; 167 UCHAR Inquiry7; 168 169 /* 0x2c: */ 170 UCHAR SyncMode; /*; 0:async mode */ 171 UCHAR NegoPeriod; /*;for nego. */ 172 UCHAR SyncPeriod; /*;for reg. */ 173 UCHAR SyncOffset; /*;for reg. and nego.(low nibble) */ 174 175 /* 0x30:*/ 176 //UCHAR InqDataBuf[8]; 177 //UCHAR CapacityBuf[8]; 178 ///* 0x40: */ 179 }; 180 181 typedef struct _DCB DC390_DCB, *PDCB; 182 /* 183 ;----------------------------------------------------------------------- 184 ; Adapter Control Block 185 ;----------------------------------------------------------------------- 186 */ 187 struct _ACB 188 { 189 PSH pScsiHost; 190 struct _ACB *pNextACB; 191 USHORT IOPortBase; 192 UCHAR IRQLevel; 193 UCHAR status; 194 195 UCHAR SRBCount; 196 UCHAR AdapterIndex; /*; nth Adapter this driver */ 197 UCHAR DeviceCnt; 198 UCHAR DCBCnt; 199 200 /* 0x10: */ 201 UCHAR TagMaxNum; 202 UCHAR ACBFlag; 203 UCHAR Gmode2; 204 UCHAR scan_devices; 205 206 PDCB pLinkDCB; 207 PDCB pLastDCB; 208 PDCB pDCBRunRobin; 209 210 PDCB pActiveDCB; 211 PSRB pFreeSRB; 212 PSRB pTmpSRB; 213 214 /* 0x2c: */ 215 ULONG QueryCnt; 216 PSCSICMD pQueryHead; 217 PSCSICMD pQueryTail; 218 219 /* 0x38: */ 220 UCHAR msgin123[4]; 221 UCHAR DCBmap[MAX_SCSI_ID]; 222 UCHAR Connected; 223 UCHAR pad; 224 225 /* 0x3c: */ 226 #if defined(USE_SPINLOCKS) && USE_SPINLOCKS > 1 && (defined(CONFIG_SMP) || DEBUG_SPINLOCKS > 0) 227 spinlock_t lock; 228 #endif 229 UCHAR sel_timeout; 230 UCHAR glitch_cfg; 231 232 UCHAR MsgLen; 233 UCHAR Ignore_IRQ; /* Not used */ 234 235 PDEVDECL1; /* Pointer to PCI cfg. space */ 236 /* 0x4c/0x48: */ 237 ULONG Cmds; 238 UINT SelLost; 239 UINT SelConn; 240 UINT CmdInQ; 241 UINT CmdOutOfSRB; 242 243 /* 0x60/0x5c: */ 244 struct timer_list Waiting_Timer; 245 /* 0x74/0x70: */ 246 DC390_SRB TmpSRB; 247 /* 0xd8/0xd4: */ 248 DC390_SRB SRB_array[MAX_SRB_CNT]; /* 50 SRBs */ 249 /* 0xfb0/0xfac: */ 250 }; 251 252 typedef struct _ACB DC390_ACB, *PACB; 253 254 /*;-----------------------------------------------------------------------*/ 255 256 257 #define BIT31 0x80000000 258 #define BIT30 0x40000000 259 #define BIT29 0x20000000 260 #define BIT28 0x10000000 261 #define BIT27 0x08000000 262 #define BIT26 0x04000000 263 #define BIT25 0x02000000 264 #define BIT24 0x01000000 265 #define BIT23 0x00800000 266 #define BIT22 0x00400000 267 #define BIT21 0x00200000 268 #define BIT20 0x00100000 269 #define BIT19 0x00080000 270 #define BIT18 0x00040000 271 #define BIT17 0x00020000 272 #define BIT16 0x00010000 273 #define BIT15 0x00008000 274 #define BIT14 0x00004000 275 #define BIT13 0x00002000 276 #define BIT12 0x00001000 277 #define BIT11 0x00000800 278 #define BIT10 0x00000400 279 #define BIT9 0x00000200 280 #define BIT8 0x00000100 281 #define BIT7 0x00000080 282 #define BIT6 0x00000040 283 #define BIT5 0x00000020 284 #define BIT4 0x00000010 285 #define BIT3 0x00000008 286 #define BIT2 0x00000004 287 #define BIT1 0x00000002 288 #define BIT0 0x00000001 289 290 /*;---UnitCtrlFlag */ 291 #define UNIT_ALLOCATED BIT0 292 #define UNIT_INFO_CHANGED BIT1 293 #define FORMATING_MEDIA BIT2 294 #define UNIT_RETRY BIT3 295 296 /*;---UnitFlags */ 297 #define DASD_SUPPORT BIT0 298 #define SCSI_SUPPORT BIT1 299 #define ASPI_SUPPORT BIT2 300 301 /*;----SRBState machine definition */ 302 #define SRB_FREE 0 303 #define SRB_WAIT BIT0 304 #define SRB_READY BIT1 305 #define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/ 306 #define SRB_MSGIN BIT3 307 #define SRB_MSGIN_MULTI BIT4 308 #define SRB_COMMAND BIT5 309 #define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/ 310 #define SRB_DISCONNECT BIT7 311 #define SRB_DATA_XFER BIT8 312 #define SRB_XFERPAD BIT9 313 #define SRB_STATUS BIT10 314 #define SRB_COMPLETED BIT11 315 #define SRB_ABORT_SENT BIT12 316 #define DO_SYNC_NEGO BIT13 317 #define SRB_UNEXPECT_RESEL BIT14 318 319 /*;---SRBstatus */ 320 #define SRB_OK BIT0 321 #define ABORTION BIT1 322 #define OVER_RUN BIT2 323 #define UNDER_RUN BIT3 324 #define PARITY_ERROR BIT4 325 #define SRB_ERROR BIT5 326 327 /*;---ACBFlag */ 328 #define RESET_DEV BIT0 329 #define RESET_DETECT BIT1 330 #define RESET_DONE BIT2 331 332 /*;---DCBFlag */ 333 #define ABORT_DEV_ BIT0 334 335 /*;---SRBFlag */ 336 #define DATAOUT BIT7 337 #define DATAIN BIT6 338 #define RESIDUAL_VALID BIT5 339 #define ENABLE_TIMER BIT4 340 #define RESET_DEV0 BIT2 341 #define ABORT_DEV BIT1 342 #define AUTO_REQSENSE BIT0 343 344 /*;---Adapter status */ 345 #define H_STATUS_GOOD 0 346 #define H_SEL_TIMEOUT 0x11 347 #define H_OVER_UNDER_RUN 0x12 348 #define H_UNEXP_BUS_FREE 0x13 349 #define H_TARGET_PHASE_F 0x14 350 #define H_INVALID_CCB_OP 0x16 351 #define H_LINK_CCB_BAD 0x17 352 #define H_BAD_TARGET_DIR 0x18 353 #define H_DUPLICATE_CCB 0x19 354 #define H_BAD_CCB_OR_SG 0x1A 355 #define H_ABORT 0x0FF 356 357 /*; SCSI Status byte codes*/ 358 /* The values defined in include/scsi/scsi.h, to be shifted << 1 */ 359 360 #define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */ 361 #define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */ 362 #define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */ 363 364 /* cmd->result */ 365 #define RES_TARGET 0x000000FF /* Target State */ 366 #define RES_TARGET_LNX STATUS_MASK /* Only official ... */ 367 #define RES_ENDMSG 0x0000FF00 /* End Message */ 368 #define RES_DID 0x00FF0000 /* DID_ codes */ 369 #define RES_DRV 0xFF000000 /* DRIVER_ codes */ 370 371 #define MK_RES(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt)) 372 #define MK_RES_LNX(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt)<<1) 373 374 #define SET_RES_TARGET(who,tgt) { who &= ~RES_TARGET; who |= (int)(tgt); } 375 #define SET_RES_TARGET_LNX(who,tgt) { who &= ~RES_TARGET_LNX; who |= (int)(tgt) << 1; } 376 #define SET_RES_MSG(who,msg) { who &= ~RES_ENDMSG; who |= (int)(msg) << 8; } 377 #define SET_RES_DID(who,did) { who &= ~RES_DID; who |= (int)(did) << 16; } 378 #define SET_RES_DRV(who,drv) { who &= ~RES_DRV; who |= (int)(drv) << 24; } 379 380 /*;---Sync_Mode */ 381 #define SYNC_DISABLE 0 382 #define SYNC_ENABLE BIT0 383 #define SYNC_NEGO_DONE BIT1 384 #define WIDE_ENABLE BIT2 /* Not used ;-) */ 385 #define WIDE_NEGO_DONE BIT3 /* Not used ;-) */ 386 #define EN_TAG_QUEUEING BIT4 387 #define EN_ATN_STOP BIT5 388 389 #define SYNC_NEGO_OFFSET 15 390 391 /*;---SCSI bus phase*/ 392 #define SCSI_DATA_OUT 0 393 #define SCSI_DATA_IN 1 394 #define SCSI_COMMAND 2 395 #define SCSI_STATUS_ 3 396 #define SCSI_NOP0 4 397 #define SCSI_NOP1 5 398 #define SCSI_MSG_OUT 6 399 #define SCSI_MSG_IN 7 400 401 /*;----SCSI MSG BYTE*/ /* see scsi/scsi.h */ /* One is missing ! */ 402 #define ABORT_TAG 0x0d 403 404 /* 405 ** Inquiry Data format 406 */ 407 408 typedef struct _SCSIInqData { /* INQUIRY */ 409 410 UCHAR DevType; /* Periph Qualifier & Periph Dev Type*/ 411 UCHAR RMB_TypeMod; /* rem media bit & Dev Type Modifier */ 412 UCHAR Vers; /* ISO, ECMA, & ANSI versions */ 413 UCHAR RDF; /* AEN, TRMIOP, & response data format*/ 414 UCHAR AddLen; /* length of additional data */ 415 UCHAR Res1; /* reserved */ 416 UCHAR Res2; /* reserved */ 417 UCHAR Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */ 418 UCHAR VendorID[8]; /* Vendor Identification */ 419 UCHAR ProductID[16]; /* Product Identification */ 420 UCHAR ProductRev[4]; /* Product Revision */ 421 422 423 } SCSI_INQDATA, *PSCSI_INQDATA; 424 425 426 /* Inquiry byte 0 masks */ 427 428 429 #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */ 430 #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */ 431 #define TYPE_NODEV SCSI_DEVTYPE /* Unknown or no device type */ 432 433 434 /* Inquiry byte 1 mask */ 435 436 #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */ 437 438 439 /* Peripheral Device Type definitions */ 440 /* see include/scsi/scsi.h for the rest */ 441 442 #ifndef TYPE_PRINTER 443 # define TYPE_PRINTER 0x02 /* Printer device */ 444 #endif 445 #ifndef TYPE_COMM 446 # define TYPE_COMM 0x09 /* Communications device */ 447 #endif 448 449 /* 450 ** Inquiry flag definitions (Inq data byte 7) 451 */ 452 453 #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/ 454 #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */ 455 #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */ 456 #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */ 457 #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */ 458 #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */ 459 #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */ 460 461 462 /* 463 ;========================================================== 464 ; EEPROM byte offset 465 ;========================================================== 466 */ 467 typedef struct _EEprom 468 { 469 UCHAR EE_MODE1; 470 UCHAR EE_SPEED; 471 UCHAR xx1; 472 UCHAR xx2; 473 } EEprom, *PEEprom; 474 475 #define REAL_EE_ADAPT_SCSI_ID 64 476 #define REAL_EE_MODE2 65 477 #define REAL_EE_DELAY 66 478 #define REAL_EE_TAG_CMD_NUM 67 479 480 #define EE_ADAPT_SCSI_ID 32 481 #define EE_MODE2 33 482 #define EE_DELAY 34 483 #define EE_TAG_CMD_NUM 35 484 485 #define EE_LEN 40 486 487 /*; EE_MODE1 bits definition*/ 488 #define PARITY_CHK_ BIT0 489 #define SYNC_NEGO_ BIT1 490 #define EN_DISCONNECT_ BIT2 491 #define SEND_START_ BIT3 492 #define TAG_QUEUEING_ BIT4 493 494 /*; EE_MODE2 bits definition*/ 495 #define MORE2_DRV BIT0 496 #define GREATER_1G BIT1 497 #define RST_SCSI_BUS BIT2 498 #define ACTIVE_NEGATION BIT3 499 #define NO_SEEK BIT4 500 #define LUN_CHECK BIT5 501 502 #define ENABLE_CE 1 503 #define DISABLE_CE 0 504 #define EEPROM_READ 0x80 505 506 /* 507 ;========================================================== 508 ; AMD 53C974 Registers bit Definition 509 ;========================================================== 510 */ 511 /* 512 ;==================== 513 ; SCSI Register 514 ;==================== 515 */ 516 517 /*; Command Reg.(+0CH) (rw) */ 518 #define DMA_COMMAND BIT7 519 #define NOP_CMD 0 520 #define CLEAR_FIFO_CMD 1 521 #define RST_DEVICE_CMD 2 522 #define RST_SCSI_BUS_CMD 3 523 524 #define INFO_XFER_CMD 0x10 525 #define INITIATOR_CMD_CMPLTE 0x11 526 #define MSG_ACCEPTED_CMD 0x12 527 #define XFER_PAD_BYTE 0x18 528 #define SET_ATN_CMD 0x1A 529 #define RESET_ATN_CMD 0x1B 530 531 #define SEL_WO_ATN 0x41 /* currently not used */ 532 #define SEL_W_ATN 0x42 533 #define SEL_W_ATN_STOP 0x43 534 #define SEL_W_ATN3 0x46 535 #define EN_SEL_RESEL 0x44 536 #define DIS_SEL_RESEL 0x45 /* currently not used */ 537 #define RESEL 0x40 /* " */ 538 #define RESEL_ATN3 0x47 /* " */ 539 540 #define DATA_XFER_CMD INFO_XFER_CMD 541 542 543 /*; SCSI Status Reg.(+10H) (r) */ 544 #define INTERRUPT BIT7 545 #define ILLEGAL_OP_ERR BIT6 546 #define PARITY_ERR BIT5 547 #define COUNT_2_ZERO BIT4 548 #define GROUP_CODE_VALID BIT3 549 #define SCSI_PHASE_MASK (BIT2+BIT1+BIT0) 550 /* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */ 551 552 /*; Interrupt Status Reg.(+14H) (r) */ 553 #define SCSI_RESET BIT7 554 #define INVALID_CMD BIT6 555 #define DISCONNECTED BIT5 556 #define SERVICE_REQUEST BIT4 557 #define SUCCESSFUL_OP BIT3 558 #define RESELECTED BIT2 559 #define SEL_ATTENTION BIT1 560 #define SELECTED BIT0 561 562 /*; Internal State Reg.(+18H) (r) */ 563 #define SYNC_OFFSET_FLAG BIT3 564 #define INTRN_STATE_MASK (BIT2+BIT1+BIT0) 565 /* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */ 566 567 /*; Clock Factor Reg.(+24H) (w) */ 568 #define CLK_FREQ_40MHZ 0 569 #define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0) 570 #define CLK_FREQ_30MHZ (BIT2+BIT1) 571 #define CLK_FREQ_25MHZ (BIT2+BIT0) 572 #define CLK_FREQ_20MHZ BIT2 573 #define CLK_FREQ_15MHZ (BIT1+BIT0) 574 #define CLK_FREQ_10MHZ BIT1 575 576 /*; Control Reg. 1(+20H) (rw) */ 577 #define EXTENDED_TIMING BIT7 578 #define DIS_INT_ON_SCSI_RST BIT6 579 #define PARITY_ERR_REPO BIT4 580 #define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0) /* host adapter ID */ 581 582 /*; Control Reg. 2(+2CH) (rw) */ 583 #define EN_FEATURE BIT6 584 #define EN_SCSI2_CMD BIT3 585 586 /*; Control Reg. 3(+30H) (rw) */ 587 #define ID_MSG_CHECK BIT7 588 #define EN_QTAG_MSG BIT6 589 #define EN_GRP2_CMD BIT5 590 #define FAST_SCSI BIT4 /* ;10MB/SEC */ 591 #define FAST_CLK BIT3 /* ;25 - 40 MHZ */ 592 593 /*; Control Reg. 4(+34H) (rw) */ 594 #define EATER_12NS 0 595 #define EATER_25NS BIT7 596 #define EATER_35NS BIT6 597 #define EATER_0NS (BIT7+BIT6) 598 #define REDUCED_POWER BIT5 599 #define CTRL4_RESERVED BIT4 /* must be 1 acc. to AM53C974.c */ 600 #define NEGATE_REQACKDATA BIT2 601 #define NEGATE_REQACK BIT3 602 603 #define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2))) 604 #define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0) 605 606 /* 607 ;==================== 608 ; DMA Register 609 ;==================== 610 */ 611 /*; DMA Command Reg.(+40H) (rw) */ 612 #define READ_DIRECTION BIT7 613 #define WRITE_DIRECTION 0 614 #define EN_DMA_INT BIT6 615 #define EN_PAGE_INT BIT5 /* page transfer interrupt enable */ 616 #define MAP_TO_MDL BIT4 617 #define DIAGNOSTIC BIT2 618 #define DMA_IDLE_CMD 0 619 #define DMA_BLAST_CMD BIT0 620 #define DMA_ABORT_CMD BIT1 621 #define DMA_START_CMD (BIT1+BIT0) 622 623 /*; DMA Status Reg.(+54H) (r) */ 624 #define PCI_MS_ABORT BIT6 625 #define BLAST_COMPLETE BIT5 626 #define SCSI_INTERRUPT BIT4 627 #define DMA_XFER_DONE BIT3 628 #define DMA_XFER_ABORT BIT2 629 #define DMA_XFER_ERROR BIT1 630 #define POWER_DOWN BIT0 631 632 /*; DMA SCSI Bus and Ctrl.(+70H) */ 633 #define EN_INT_ON_PCI_ABORT BIT25 634 #define WRT_ERASE_DMA_STAT BIT24 635 #define PW_DOWN_CTRL BIT21 636 #define SCSI_BUSY BIT20 637 #define SCLK BIT19 638 #define SCAM BIT18 639 #define SCSI_LINES 0x0003ffff 640 641 /* 642 ;========================================================== 643 ; SCSI Chip register address offset 644 ;========================================================== 645 ;Registers are rw unless declared otherwise 646 */ 647 #define CtcReg_Low 0x00 /* r curr. transfer count */ 648 #define CtcReg_Mid 0x04 /* r */ 649 #define CtcReg_High 0x38 /* r */ 650 #define ScsiFifo 0x08 651 #define ScsiCmd 0x0C 652 #define Scsi_Status 0x10 /* r */ 653 #define INT_Status 0x14 /* r */ 654 #define Sync_Period 0x18 /* w */ 655 #define Sync_Offset 0x1C /* w */ 656 #define Clk_Factor 0x24 /* w */ 657 #define CtrlReg1 0x20 658 #define CtrlReg2 0x2C 659 #define CtrlReg3 0x30 660 #define CtrlReg4 0x34 661 #define DMA_Cmd 0x40 662 #define DMA_XferCnt 0x44 /* rw starting transfer count (32 bit) */ 663 #define DMA_XferAddr 0x48 /* rw starting physical address (32 bit) */ 664 #define DMA_Wk_ByteCntr 0x4C /* r working byte counter */ 665 #define DMA_Wk_AddrCntr 0x50 /* r working address counter */ 666 #define DMA_Status 0x54 /* r */ 667 #define DMA_MDL_Addr 0x58 /* rw starting MDL address */ 668 #define DMA_Wk_MDL_Cntr 0x5C /* r working MDL counter */ 669 #define DMA_ScsiBusCtrl 0x70 /* rw SCSI Bus, PCI/DMA Ctrl */ 670 671 #define StcReg_Low CtcReg_Low /* w start transfer count */ 672 #define StcReg_Mid CtcReg_Mid /* w */ 673 #define StcReg_High CtcReg_High /* w */ 674 #define Scsi_Dest_ID Scsi_Status /* w */ 675 #define Scsi_TimeOut INT_Status /* w */ 676 #define Intern_State Sync_Period /* r */ 677 #define Current_Fifo Sync_Offset /* r Curr. FIFO / int. state */ 678 679 680 #define DC390_read8(address) \ 681 (inb (pACB->IOPortBase + (address))) 682 683 #define DC390_read8_(address, base) \ 684 (inb ((USHORT)(base) + (address))) 685 686 #define DC390_read16(address) \ 687 (inw (pACB->IOPortBase + (address))) 688 689 #define DC390_read32(address) \ 690 (inl (pACB->IOPortBase + (address))) 691 692 #define DC390_write8(address,value) \ 693 outb ((value), pACB->IOPortBase + (address)) 694 695 #define DC390_write8_(address,value,base) \ 696 outb ((value), (USHORT)(base) + (address)) 697 698 #define DC390_write16(address,value) \ 699 outw ((value), pACB->IOPortBase + (address)) 700 701 #define DC390_write32(address,value) \ 702 outl ((value), pACB->IOPortBase + (address)) 703 704 705 #endif /* _TMSCSIM_H */ 706