1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020-2021 Intel Corporation. */
3 #ifndef __CXL_MEM_H__
4 #define __CXL_MEM_H__
5 #include <uapi/linux/cxl_mem.h>
6 #include <linux/cdev.h>
7 #include "cxl.h"
8 
9 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
10 #define CXLMDEV_STATUS_OFFSET 0x0
11 #define   CXLMDEV_DEV_FATAL BIT(0)
12 #define   CXLMDEV_FW_HALT BIT(1)
13 #define   CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
14 #define     CXLMDEV_MS_NOT_READY 0
15 #define     CXLMDEV_MS_READY 1
16 #define     CXLMDEV_MS_ERROR 2
17 #define     CXLMDEV_MS_DISABLED 3
18 #define CXLMDEV_READY(status)                                                  \
19 	(FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) ==                \
20 	 CXLMDEV_MS_READY)
21 #define   CXLMDEV_MBOX_IF_READY BIT(4)
22 #define   CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
23 #define     CXLMDEV_RESET_NEEDED_NOT 0
24 #define     CXLMDEV_RESET_NEEDED_COLD 1
25 #define     CXLMDEV_RESET_NEEDED_WARM 2
26 #define     CXLMDEV_RESET_NEEDED_HOT 3
27 #define     CXLMDEV_RESET_NEEDED_CXL 4
28 #define CXLMDEV_RESET_NEEDED(status)                                           \
29 	(FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) !=                       \
30 	 CXLMDEV_RESET_NEEDED_NOT)
31 
32 /**
33  * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
34  * @dev: driver core device object
35  * @cdev: char dev core object for ioctl operations
36  * @cxlds: The device state backing this device
37  * @detach_work: active memdev lost a port in its ancestry
38  * @id: id number of this memdev instance.
39  */
40 struct cxl_memdev {
41 	struct device dev;
42 	struct cdev cdev;
43 	struct cxl_dev_state *cxlds;
44 	struct work_struct detach_work;
45 	int id;
46 };
47 
to_cxl_memdev(struct device * dev)48 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
49 {
50 	return container_of(dev, struct cxl_memdev, dev);
51 }
52 
cxled_to_port(struct cxl_endpoint_decoder * cxled)53 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
54 {
55 	return to_cxl_port(cxled->cxld.dev.parent);
56 }
57 
cxlrd_to_port(struct cxl_root_decoder * cxlrd)58 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)
59 {
60 	return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
61 }
62 
63 static inline struct cxl_memdev *
cxled_to_memdev(struct cxl_endpoint_decoder * cxled)64 cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
65 {
66 	struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
67 
68 	return to_cxl_memdev(port->uport);
69 }
70 
71 bool is_cxl_memdev(struct device *dev);
is_cxl_endpoint(struct cxl_port * port)72 static inline bool is_cxl_endpoint(struct cxl_port *port)
73 {
74 	return is_cxl_memdev(port->uport);
75 }
76 
77 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);
78 
79 /**
80  * struct cxl_mbox_cmd - A command to be submitted to hardware.
81  * @opcode: (input) The command set and command submitted to hardware.
82  * @payload_in: (input) Pointer to the input payload.
83  * @payload_out: (output) Pointer to the output payload. Must be allocated by
84  *		 the caller.
85  * @size_in: (input) Number of bytes to load from @payload_in.
86  * @size_out: (input) Max number of bytes loaded into @payload_out.
87  *            (output) Number of bytes generated by the device. For fixed size
88  *            outputs commands this is always expected to be deterministic. For
89  *            variable sized output commands, it tells the exact number of bytes
90  *            written.
91  * @return_code: (output) Error code returned from hardware.
92  *
93  * This is the primary mechanism used to send commands to the hardware.
94  * All the fields except @payload_* correspond exactly to the fields described in
95  * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
96  * @payload_out are written to, and read from the Command Payload Registers
97  * defined in CXL 2.0 8.2.8.4.8.
98  */
99 struct cxl_mbox_cmd {
100 	u16 opcode;
101 	void *payload_in;
102 	void *payload_out;
103 	size_t size_in;
104 	size_t size_out;
105 	u16 return_code;
106 };
107 
108 /*
109  * Per CXL 2.0 Section 8.2.8.4.5.1
110  */
111 #define CMD_CMD_RC_TABLE							\
112 	C(SUCCESS, 0, NULL),							\
113 	C(BACKGROUND, -ENXIO, "background cmd started successfully"),           \
114 	C(INPUT, -ENXIO, "cmd input was invalid"),				\
115 	C(UNSUPPORTED, -ENXIO, "cmd is not supported"),				\
116 	C(INTERNAL, -ENXIO, "internal device error"),				\
117 	C(RETRY, -ENXIO, "temporary error, retry once"),			\
118 	C(BUSY, -ENXIO, "ongoing background operation"),			\
119 	C(MEDIADISABLED, -ENXIO, "media access is disabled"),			\
120 	C(FWINPROGRESS, -ENXIO,	"one FW package can be transferred at a time"), \
121 	C(FWOOO, -ENXIO, "FW package content was transferred out of order"),    \
122 	C(FWAUTH, -ENXIO, "FW package authentication failed"),			\
123 	C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"),  \
124 	C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"),         \
125 	C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"),		\
126 	C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"),     \
127 	C(PADDR, -ENXIO, "physical address specified is invalid"),		\
128 	C(POISONLMT, -ENXIO, "poison injection limit has been reached"),        \
129 	C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"),		\
130 	C(ABORT, -ENXIO, "background cmd was aborted by device"),               \
131 	C(SECURITY, -ENXIO, "not valid in the current security state"),         \
132 	C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"),   \
133 	C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
134 	C(PAYLOADLEN, -ENXIO, "invalid payload length")
135 
136 #undef C
137 #define C(a, b, c) CXL_MBOX_CMD_RC_##a
138 enum  { CMD_CMD_RC_TABLE };
139 #undef C
140 #define C(a, b, c) { b, c }
141 struct cxl_mbox_cmd_rc {
142 	int err;
143 	const char *desc;
144 };
145 
146 static const
147 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
148 #undef C
149 
cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd * mbox_cmd)150 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
151 {
152 	return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
153 }
154 
cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd * mbox_cmd)155 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
156 {
157 	return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
158 }
159 
160 /*
161  * CXL 2.0 - Memory capacity multiplier
162  * See Section 8.2.9.5
163  *
164  * Volatile, Persistent, and Partition capacities are specified to be in
165  * multiples of 256MB - define a multiplier to convert to/from bytes.
166  */
167 #define CXL_CAPACITY_MULTIPLIER SZ_256M
168 
169 /**
170  * struct cxl_endpoint_dvsec_info - Cached DVSEC info
171  * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
172  * @ranges: Number of active HDM ranges this device uses.
173  * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
174  */
175 struct cxl_endpoint_dvsec_info {
176 	bool mem_enabled;
177 	int ranges;
178 	struct range dvsec_range[2];
179 };
180 
181 /**
182  * struct cxl_dev_state - The driver device state
183  *
184  * cxl_dev_state represents the CXL driver/device state.  It provides an
185  * interface to mailbox commands as well as some cached data about the device.
186  * Currently only memory devices are represented.
187  *
188  * @dev: The device associated with this CXL state
189  * @regs: Parsed register blocks
190  * @cxl_dvsec: Offset to the PCIe device DVSEC
191  * @payload_size: Size of space for payload
192  *                (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
193  * @lsa_size: Size of Label Storage Area
194  *                (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
195  * @mbox_mutex: Mutex to synchronize mailbox access.
196  * @firmware_version: Firmware version for the memory device.
197  * @enabled_cmds: Hardware commands found enabled in CEL.
198  * @exclusive_cmds: Commands that are kernel-internal only
199  * @dpa_res: Overall DPA resource tree for the device
200  * @pmem_res: Active Persistent memory capacity configuration
201  * @ram_res: Active Volatile memory capacity configuration
202  * @total_bytes: sum of all possible capacities
203  * @volatile_only_bytes: hard volatile capacity
204  * @persistent_only_bytes: hard persistent capacity
205  * @partition_align_bytes: alignment size for partition-able capacity
206  * @active_volatile_bytes: sum of hard + soft volatile
207  * @active_persistent_bytes: sum of hard + soft persistent
208  * @next_volatile_bytes: volatile capacity change pending device reset
209  * @next_persistent_bytes: persistent capacity change pending device reset
210  * @component_reg_phys: register base of component registers
211  * @info: Cached DVSEC information about the device.
212  * @serial: PCIe Device Serial Number
213  * @doe_mbs: PCI DOE mailbox array
214  * @mbox_send: @dev specific transport for transmitting mailbox commands
215  *
216  * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
217  * details on capacity parameters.
218  */
219 struct cxl_dev_state {
220 	struct device *dev;
221 
222 	struct cxl_regs regs;
223 	int cxl_dvsec;
224 
225 	size_t payload_size;
226 	size_t lsa_size;
227 	struct mutex mbox_mutex; /* Protects device mailbox and firmware */
228 	char firmware_version[0x10];
229 	DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
230 	DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
231 
232 	struct resource dpa_res;
233 	struct resource pmem_res;
234 	struct resource ram_res;
235 	u64 total_bytes;
236 	u64 volatile_only_bytes;
237 	u64 persistent_only_bytes;
238 	u64 partition_align_bytes;
239 
240 	u64 active_volatile_bytes;
241 	u64 active_persistent_bytes;
242 	u64 next_volatile_bytes;
243 	u64 next_persistent_bytes;
244 
245 	resource_size_t component_reg_phys;
246 	u64 serial;
247 
248 	struct xarray doe_mbs;
249 
250 	int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
251 };
252 
253 enum cxl_opcode {
254 	CXL_MBOX_OP_INVALID		= 0x0000,
255 	CXL_MBOX_OP_RAW			= CXL_MBOX_OP_INVALID,
256 	CXL_MBOX_OP_GET_FW_INFO		= 0x0200,
257 	CXL_MBOX_OP_ACTIVATE_FW		= 0x0202,
258 	CXL_MBOX_OP_GET_SUPPORTED_LOGS	= 0x0400,
259 	CXL_MBOX_OP_GET_LOG		= 0x0401,
260 	CXL_MBOX_OP_IDENTIFY		= 0x4000,
261 	CXL_MBOX_OP_GET_PARTITION_INFO	= 0x4100,
262 	CXL_MBOX_OP_SET_PARTITION_INFO	= 0x4101,
263 	CXL_MBOX_OP_GET_LSA		= 0x4102,
264 	CXL_MBOX_OP_SET_LSA		= 0x4103,
265 	CXL_MBOX_OP_GET_HEALTH_INFO	= 0x4200,
266 	CXL_MBOX_OP_GET_ALERT_CONFIG	= 0x4201,
267 	CXL_MBOX_OP_SET_ALERT_CONFIG	= 0x4202,
268 	CXL_MBOX_OP_GET_SHUTDOWN_STATE	= 0x4203,
269 	CXL_MBOX_OP_SET_SHUTDOWN_STATE	= 0x4204,
270 	CXL_MBOX_OP_GET_POISON		= 0x4300,
271 	CXL_MBOX_OP_INJECT_POISON	= 0x4301,
272 	CXL_MBOX_OP_CLEAR_POISON	= 0x4302,
273 	CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS	= 0x4303,
274 	CXL_MBOX_OP_SCAN_MEDIA		= 0x4304,
275 	CXL_MBOX_OP_GET_SCAN_MEDIA	= 0x4305,
276 	CXL_MBOX_OP_MAX			= 0x10000
277 };
278 
279 #define DEFINE_CXL_CEL_UUID                                                    \
280 	UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62,     \
281 		  0x3b, 0x3f, 0x17)
282 
283 #define DEFINE_CXL_VENDOR_DEBUG_UUID                                           \
284 	UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19,     \
285 		  0x40, 0x3d, 0x86)
286 
287 struct cxl_mbox_get_supported_logs {
288 	__le16 entries;
289 	u8 rsvd[6];
290 	struct cxl_gsl_entry {
291 		uuid_t uuid;
292 		__le32 size;
293 	} __packed entry[];
294 }  __packed;
295 
296 struct cxl_cel_entry {
297 	__le16 opcode;
298 	__le16 effect;
299 } __packed;
300 
301 struct cxl_mbox_get_log {
302 	uuid_t uuid;
303 	__le32 offset;
304 	__le32 length;
305 } __packed;
306 
307 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
308 struct cxl_mbox_identify {
309 	char fw_revision[0x10];
310 	__le64 total_capacity;
311 	__le64 volatile_capacity;
312 	__le64 persistent_capacity;
313 	__le64 partition_align;
314 	__le16 info_event_log_size;
315 	__le16 warning_event_log_size;
316 	__le16 failure_event_log_size;
317 	__le16 fatal_event_log_size;
318 	__le32 lsa_size;
319 	u8 poison_list_max_mer[3];
320 	__le16 inject_poison_limit;
321 	u8 poison_caps;
322 	u8 qos_telemetry_caps;
323 } __packed;
324 
325 struct cxl_mbox_get_partition_info {
326 	__le64 active_volatile_cap;
327 	__le64 active_persistent_cap;
328 	__le64 next_volatile_cap;
329 	__le64 next_persistent_cap;
330 } __packed;
331 
332 struct cxl_mbox_get_lsa {
333 	__le32 offset;
334 	__le32 length;
335 } __packed;
336 
337 struct cxl_mbox_set_lsa {
338 	__le32 offset;
339 	__le32 reserved;
340 	u8 data[];
341 } __packed;
342 
343 struct cxl_mbox_set_partition_info {
344 	__le64 volatile_capacity;
345 	u8 flags;
346 } __packed;
347 
348 #define  CXL_SET_PARTITION_IMMEDIATE_FLAG	BIT(0)
349 
350 /**
351  * struct cxl_mem_command - Driver representation of a memory device command
352  * @info: Command information as it exists for the UAPI
353  * @opcode: The actual bits used for the mailbox protocol
354  * @flags: Set of flags effecting driver behavior.
355  *
356  *  * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
357  *    will be enabled by the driver regardless of what hardware may have
358  *    advertised.
359  *
360  * The cxl_mem_command is the driver's internal representation of commands that
361  * are supported by the driver. Some of these commands may not be supported by
362  * the hardware. The driver will use @info to validate the fields passed in by
363  * the user then submit the @opcode to the hardware.
364  *
365  * See struct cxl_command_info.
366  */
367 struct cxl_mem_command {
368 	struct cxl_command_info info;
369 	enum cxl_opcode opcode;
370 	u32 flags;
371 #define CXL_CMD_FLAG_NONE 0
372 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
373 };
374 
375 int cxl_mbox_send_cmd(struct cxl_dev_state *cxlds, u16 opcode, void *in,
376 		      size_t in_size, void *out, size_t out_size);
377 int cxl_dev_state_identify(struct cxl_dev_state *cxlds);
378 int cxl_await_media_ready(struct cxl_dev_state *cxlds);
379 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds);
380 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds);
381 struct cxl_dev_state *cxl_dev_state_create(struct device *dev);
382 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
383 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
384 #ifdef CONFIG_CXL_SUSPEND
385 void cxl_mem_active_inc(void);
386 void cxl_mem_active_dec(void);
387 #else
cxl_mem_active_inc(void)388 static inline void cxl_mem_active_inc(void)
389 {
390 }
cxl_mem_active_dec(void)391 static inline void cxl_mem_active_dec(void)
392 {
393 }
394 #endif
395 
396 struct cxl_hdm {
397 	struct cxl_component_regs regs;
398 	unsigned int decoder_count;
399 	unsigned int target_count;
400 	unsigned int interleave_mask;
401 	struct cxl_port *port;
402 };
403 
404 struct seq_file;
405 struct dentry *cxl_debugfs_create_dir(const char *dir);
406 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
407 #endif /* __CXL_MEM_H__ */
408