1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_MDSS_H 6 #define _DPU_HW_MDSS_H 7 8 #include <linux/kernel.h> 9 #include <linux/err.h> 10 11 #include "msm_drv.h" 12 13 #define DPU_DBG_NAME "dpu" 14 15 #define DPU_NONE 0 16 17 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 18 #define DPU_CSC_MATRIX_COEFF_SIZE 9 19 #endif 20 21 #ifndef DPU_CSC_CLAMP_SIZE 22 #define DPU_CSC_CLAMP_SIZE 6 23 #endif 24 25 #ifndef DPU_CSC_BIAS_SIZE 26 #define DPU_CSC_BIAS_SIZE 3 27 #endif 28 29 #ifndef DPU_MAX_PLANES 30 #define DPU_MAX_PLANES 4 31 #endif 32 33 #define PIPES_PER_STAGE 2 34 #ifndef DPU_MAX_DE_CURVES 35 #define DPU_MAX_DE_CURVES 3 36 #endif 37 38 enum dpu_format_flags { 39 DPU_FORMAT_FLAG_YUV_BIT, 40 DPU_FORMAT_FLAG_DX_BIT, 41 DPU_FORMAT_FLAG_COMPRESSED_BIT, 42 DPU_FORMAT_FLAG_BIT_MAX, 43 }; 44 45 #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) 46 #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) 47 #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) 48 #define DPU_FORMAT_IS_YUV(X) \ 49 (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag)) 50 #define DPU_FORMAT_IS_DX(X) \ 51 (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag)) 52 #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR) 53 #define DPU_FORMAT_IS_TILE(X) \ 54 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 55 !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 56 #define DPU_FORMAT_IS_UBWC(X) \ 57 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 58 test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 59 60 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 61 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 62 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 63 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 64 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 65 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 66 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 67 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 68 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 69 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 70 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 71 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 72 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 73 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 74 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 75 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 76 77 #define DPU_VSYNC0_SOURCE_GPIO 0 78 #define DPU_VSYNC1_SOURCE_GPIO 1 79 #define DPU_VSYNC2_SOURCE_GPIO 2 80 #define DPU_VSYNC_SOURCE_INTF_0 3 81 #define DPU_VSYNC_SOURCE_INTF_1 4 82 #define DPU_VSYNC_SOURCE_INTF_2 5 83 #define DPU_VSYNC_SOURCE_INTF_3 6 84 #define DPU_VSYNC_SOURCE_WD_TIMER_4 11 85 #define DPU_VSYNC_SOURCE_WD_TIMER_3 12 86 #define DPU_VSYNC_SOURCE_WD_TIMER_2 13 87 #define DPU_VSYNC_SOURCE_WD_TIMER_1 14 88 #define DPU_VSYNC_SOURCE_WD_TIMER_0 15 89 90 enum dpu_hw_blk_type { 91 DPU_HW_BLK_TOP = 0, 92 DPU_HW_BLK_SSPP, 93 DPU_HW_BLK_LM, 94 DPU_HW_BLK_CTL, 95 DPU_HW_BLK_PINGPONG, 96 DPU_HW_BLK_INTF, 97 DPU_HW_BLK_WB, 98 DPU_HW_BLK_DSPP, 99 DPU_HW_BLK_MERGE_3D, 100 DPU_HW_BLK_DSC, 101 DPU_HW_BLK_MAX, 102 }; 103 104 enum dpu_sspp { 105 SSPP_NONE, 106 SSPP_VIG0, 107 SSPP_VIG1, 108 SSPP_VIG2, 109 SSPP_VIG3, 110 SSPP_RGB0, 111 SSPP_RGB1, 112 SSPP_RGB2, 113 SSPP_RGB3, 114 SSPP_DMA0, 115 SSPP_DMA1, 116 SSPP_DMA2, 117 SSPP_DMA3, 118 SSPP_DMA4, 119 SSPP_DMA5, 120 SSPP_CURSOR0, 121 SSPP_CURSOR1, 122 SSPP_MAX 123 }; 124 125 enum dpu_sspp_type { 126 SSPP_TYPE_VIG, 127 SSPP_TYPE_RGB, 128 SSPP_TYPE_DMA, 129 SSPP_TYPE_CURSOR, 130 SSPP_TYPE_MAX 131 }; 132 133 enum dpu_lm { 134 LM_0 = 1, 135 LM_1, 136 LM_2, 137 LM_3, 138 LM_4, 139 LM_5, 140 LM_6, 141 LM_MAX 142 }; 143 144 enum dpu_stage { 145 DPU_STAGE_BASE = 0, 146 DPU_STAGE_0, 147 DPU_STAGE_1, 148 DPU_STAGE_2, 149 DPU_STAGE_3, 150 DPU_STAGE_4, 151 DPU_STAGE_5, 152 DPU_STAGE_6, 153 DPU_STAGE_7, 154 DPU_STAGE_8, 155 DPU_STAGE_9, 156 DPU_STAGE_10, 157 DPU_STAGE_MAX 158 }; 159 enum dpu_dspp { 160 DSPP_0 = 1, 161 DSPP_1, 162 DSPP_2, 163 DSPP_3, 164 DSPP_MAX 165 }; 166 167 enum dpu_ctl { 168 CTL_0 = 1, 169 CTL_1, 170 CTL_2, 171 CTL_3, 172 CTL_4, 173 CTL_5, 174 CTL_MAX 175 }; 176 177 enum dpu_dsc { 178 DSC_NONE = 0, 179 DSC_0, 180 DSC_1, 181 DSC_2, 182 DSC_3, 183 DSC_4, 184 DSC_5, 185 DSC_MAX 186 }; 187 188 enum dpu_pingpong { 189 PINGPONG_NONE, 190 PINGPONG_0, 191 PINGPONG_1, 192 PINGPONG_2, 193 PINGPONG_3, 194 PINGPONG_4, 195 PINGPONG_5, 196 PINGPONG_6, 197 PINGPONG_7, 198 PINGPONG_S0, 199 PINGPONG_MAX 200 }; 201 202 enum dpu_merge_3d { 203 MERGE_3D_0 = 1, 204 MERGE_3D_1, 205 MERGE_3D_2, 206 MERGE_3D_3, 207 MERGE_3D_MAX 208 }; 209 210 enum dpu_intf { 211 INTF_0 = 1, 212 INTF_1, 213 INTF_2, 214 INTF_3, 215 INTF_4, 216 INTF_5, 217 INTF_6, 218 INTF_7, 219 INTF_8, 220 INTF_MAX 221 }; 222 223 /* 224 * Historically these values correspond to the values written to the 225 * DISP_INTF_SEL register, which had to programmed manually. On newer MDP 226 * generations this register is NOP, but we keep the values for historical 227 * reasons. 228 */ 229 enum dpu_intf_type { 230 INTF_NONE = 0x0, 231 INTF_DSI = 0x1, 232 INTF_HDMI = 0x3, 233 INTF_LCDC = 0x5, 234 /* old eDP found on 8x74 and 8x84 */ 235 INTF_EDP = 0x9, 236 /* both DP and eDP, handled by the new DP driver */ 237 INTF_DP = 0xa, 238 239 /* virtual interfaces */ 240 INTF_WB = 0x100, 241 }; 242 243 enum dpu_intf_mode { 244 INTF_MODE_NONE = 0, 245 INTF_MODE_CMD, 246 INTF_MODE_VIDEO, 247 INTF_MODE_WB_BLOCK, 248 INTF_MODE_WB_LINE, 249 INTF_MODE_MAX 250 }; 251 252 enum dpu_wb { 253 WB_0 = 1, 254 WB_1, 255 WB_2, 256 WB_3, 257 WB_MAX 258 }; 259 260 enum dpu_cwb { 261 CWB_0 = 0x1, 262 CWB_1, 263 CWB_2, 264 CWB_3, 265 CWB_MAX 266 }; 267 268 enum dpu_wd_timer { 269 WD_TIMER_0 = 0x1, 270 WD_TIMER_1, 271 WD_TIMER_2, 272 WD_TIMER_3, 273 WD_TIMER_4, 274 WD_TIMER_5, 275 WD_TIMER_MAX 276 }; 277 278 enum dpu_vbif { 279 VBIF_RT, 280 VBIF_NRT, 281 VBIF_MAX, 282 }; 283 284 /** 285 * DPU HW,Component order color map 286 */ 287 enum { 288 C0_G_Y = 0, 289 C1_B_Cb = 1, 290 C2_R_Cr = 2, 291 C3_ALPHA = 3 292 }; 293 294 /** 295 * enum dpu_plane_type - defines how the color component pixel packing 296 * @DPU_PLANE_INTERLEAVED : Color components in single plane 297 * @DPU_PLANE_PLANAR : Color component in separate planes 298 * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane 299 */ 300 enum dpu_plane_type { 301 DPU_PLANE_INTERLEAVED, 302 DPU_PLANE_PLANAR, 303 DPU_PLANE_PSEUDO_PLANAR, 304 }; 305 306 /** 307 * enum dpu_chroma_samp_type - chroma sub-samplng type 308 * @DPU_CHROMA_RGB : No chroma subsampling 309 * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled 310 * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled 311 * @DPU_CHROMA_420 : 420 subsampling 312 */ 313 enum dpu_chroma_samp_type { 314 DPU_CHROMA_RGB, 315 DPU_CHROMA_H2V1, 316 DPU_CHROMA_H1V2, 317 DPU_CHROMA_420 318 }; 319 320 /** 321 * dpu_fetch_type - Defines How DPU HW fetches data 322 * @DPU_FETCH_LINEAR : fetch is line by line 323 * @DPU_FETCH_TILE : fetches data in Z order from a tile 324 * @DPU_FETCH_UBWC : fetch and decompress data 325 */ 326 enum dpu_fetch_type { 327 DPU_FETCH_LINEAR, 328 DPU_FETCH_TILE, 329 DPU_FETCH_UBWC 330 }; 331 332 /** 333 * Value of enum chosen to fit the number of bits 334 * expected by the HW programming. 335 */ 336 enum { 337 COLOR_ALPHA_1BIT = 0, 338 COLOR_ALPHA_4BIT = 1, 339 COLOR_4BIT = 0, 340 COLOR_5BIT = 1, /* No 5-bit Alpha */ 341 COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */ 342 COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */ 343 }; 344 345 /** 346 * enum dpu_3d_blend_mode 347 * Desribes how the 3d data is blended 348 * @BLEND_3D_NONE : 3d blending not enabled 349 * @BLEND_3D_FRAME_INT : Frame interleaving 350 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 351 * @BLEND_3D_V_ROW_INT : vertical row interleaving 352 * @BLEND_3D_COL_INT : column interleaving 353 * @BLEND_3D_MAX : 354 */ 355 enum dpu_3d_blend_mode { 356 BLEND_3D_NONE = 0, 357 BLEND_3D_FRAME_INT, 358 BLEND_3D_H_ROW_INT, 359 BLEND_3D_V_ROW_INT, 360 BLEND_3D_COL_INT, 361 BLEND_3D_MAX 362 }; 363 364 /** struct dpu_format - defines the format configuration which 365 * allows DPU HW to correctly fetch and decode the format 366 * @base: base msm_format structure containing fourcc code 367 * @fetch_planes: how the color components are packed in pixel format 368 * @element: element color ordering 369 * @bits: element bit widths 370 * @chroma_sample: chroma sub-samplng type 371 * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB 372 * @unpack_tight: 0 for loose, 1 for tight 373 * @unpack_count: 0 = 1 component, 1 = 2 component 374 * @bpp: bytes per pixel 375 * @alpha_enable: whether the format has an alpha channel 376 * @num_planes: number of planes (including meta data planes) 377 * @fetch_mode: linear, tiled, or ubwc hw fetch behavior 378 * @flag: usage bit flags 379 * @tile_width: format tile width 380 * @tile_height: format tile height 381 */ 382 struct dpu_format { 383 struct msm_format base; 384 enum dpu_plane_type fetch_planes; 385 u8 element[DPU_MAX_PLANES]; 386 u8 bits[DPU_MAX_PLANES]; 387 enum dpu_chroma_samp_type chroma_sample; 388 u8 unpack_align_msb; 389 u8 unpack_tight; 390 u8 unpack_count; 391 u8 bpp; 392 u8 alpha_enable; 393 u8 num_planes; 394 enum dpu_fetch_type fetch_mode; 395 DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX); 396 u16 tile_width; 397 u16 tile_height; 398 }; 399 #define to_dpu_format(x) container_of(x, struct dpu_format, base) 400 401 /** 402 * struct dpu_hw_fmt_layout - format information of the source pixel data 403 * @format: pixel format parameters 404 * @num_planes: number of planes (including meta data planes) 405 * @width: image width 406 * @height: image height 407 * @total_size: total size in bytes 408 * @plane_addr: address of each plane 409 * @plane_size: length of each plane 410 * @plane_pitch: pitch of each plane 411 */ 412 struct dpu_hw_fmt_layout { 413 const struct dpu_format *format; 414 uint32_t num_planes; 415 uint32_t width; 416 uint32_t height; 417 uint32_t total_size; 418 uint32_t plane_addr[DPU_MAX_PLANES]; 419 uint32_t plane_size[DPU_MAX_PLANES]; 420 uint32_t plane_pitch[DPU_MAX_PLANES]; 421 }; 422 423 struct dpu_csc_cfg { 424 /* matrix coefficients in S15.16 format */ 425 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 426 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 427 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 428 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 429 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 430 }; 431 432 /** 433 * struct dpu_mdss_color - mdss color description 434 * color 0 : green 435 * color 1 : blue 436 * color 2 : red 437 * color 3 : alpha 438 */ 439 struct dpu_mdss_color { 440 u32 color_0; 441 u32 color_1; 442 u32 color_2; 443 u32 color_3; 444 }; 445 446 /* 447 * Define bit masks for h/w logging. 448 */ 449 #define DPU_DBG_MASK_NONE (1 << 0) 450 #define DPU_DBG_MASK_INTF (1 << 1) 451 #define DPU_DBG_MASK_LM (1 << 2) 452 #define DPU_DBG_MASK_CTL (1 << 3) 453 #define DPU_DBG_MASK_PINGPONG (1 << 4) 454 #define DPU_DBG_MASK_SSPP (1 << 5) 455 #define DPU_DBG_MASK_WB (1 << 6) 456 #define DPU_DBG_MASK_TOP (1 << 7) 457 #define DPU_DBG_MASK_VBIF (1 << 8) 458 #define DPU_DBG_MASK_ROT (1 << 9) 459 #define DPU_DBG_MASK_DSPP (1 << 10) 460 #define DPU_DBG_MASK_DSC (1 << 11) 461 462 /** 463 * struct dpu_hw_tear_check - Struct contains parameters to configure 464 * tear-effect module. This structure is used to configure tear-check 465 * logic present either in ping-pong or in interface module. 466 * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided 467 * by no of lines 468 * @sync_cfg_height: Total vertical lines (display height - 1) 469 * @vsync_init_val: Init value to which the read pointer gets loaded at 470 * vsync edge 471 * @sync_threshold_start: Read pointer threshold start ROI for write operation 472 * @sync_threshold_continue: The minimum number of lines the write pointer 473 * needs to be above the read pointer 474 * @start_pos: The position from which the start_threshold value is added 475 * @rd_ptr_irq: The read pointer line at which interrupt has to be generated 476 * @hw_vsync_mode: Sync with external frame sync input 477 */ 478 struct dpu_hw_tear_check { 479 /* 480 * This is ratio of MDP VSYNC clk freq(Hz) to 481 * refresh rate divided by no of lines 482 */ 483 u32 vsync_count; 484 u32 sync_cfg_height; 485 u32 vsync_init_val; 486 u32 sync_threshold_start; 487 u32 sync_threshold_continue; 488 u32 start_pos; 489 u32 rd_ptr_irq; 490 u8 hw_vsync_mode; 491 }; 492 493 /** 494 * struct dpu_hw_pp_vsync_info - Struct contains parameters to configure 495 * read and write pointers for command mode panels 496 * @rd_ptr_init_val: Value of rd pointer at vsync edge 497 * @rd_ptr_frame_count: Num frames sent since enabling interface 498 * @rd_ptr_line_count: Current line on panel (rd ptr) 499 * @wr_ptr_line_count: Current line within pp fifo (wr ptr) 500 * @intf_frame_count: Frames read from intf 501 */ 502 struct dpu_hw_pp_vsync_info { 503 u32 rd_ptr_init_val; 504 u32 rd_ptr_frame_count; 505 u32 rd_ptr_line_count; 506 u32 wr_ptr_line_count; 507 u32 intf_frame_count; 508 }; 509 510 #endif /* _DPU_HW_MDSS_H */ 511