1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * linux/sound/cs42l42.h -- Platform data for CS42L42 ALSA SoC audio driver header
4  *
5  * Copyright 2016-2022 Cirrus Logic, Inc.
6  *
7  * Author: James Schulman <james.schulman@cirrus.com>
8  * Author: Brian Austin <brian.austin@cirrus.com>
9  * Author: Michael White <michael.white@cirrus.com>
10  */
11 
12 #ifndef __CS42L42_H
13 #define __CS42L42_H
14 
15 #define CS42L42_PAGE_REGISTER	0x00	/* Page Select Register */
16 #define CS42L42_WIN_START	0x00
17 #define CS42L42_WIN_LEN		0x100
18 #define CS42L42_RANGE_MIN	0x00
19 #define CS42L42_RANGE_MAX	0x7F
20 
21 #define CS42L42_PAGE_10		0x1000
22 #define CS42L42_PAGE_11		0x1100
23 #define CS42L42_PAGE_12		0x1200
24 #define CS42L42_PAGE_13		0x1300
25 #define CS42L42_PAGE_15		0x1500
26 #define CS42L42_PAGE_19		0x1900
27 #define CS42L42_PAGE_1B		0x1B00
28 #define CS42L42_PAGE_1C		0x1C00
29 #define CS42L42_PAGE_1D		0x1D00
30 #define CS42L42_PAGE_1F		0x1F00
31 #define CS42L42_PAGE_20		0x2000
32 #define CS42L42_PAGE_21		0x2100
33 #define CS42L42_PAGE_23		0x2300
34 #define CS42L42_PAGE_24		0x2400
35 #define CS42L42_PAGE_25		0x2500
36 #define CS42L42_PAGE_26		0x2600
37 #define CS42L42_PAGE_28		0x2800
38 #define CS42L42_PAGE_29		0x2900
39 #define CS42L42_PAGE_2A		0x2A00
40 #define CS42L42_PAGE_30		0x3000
41 
42 #define CS42L42_CHIP_ID		0x42A42
43 
44 /* Page 0x10 Global Registers */
45 #define CS42L42_DEVID_AB		(CS42L42_PAGE_10 + 0x01)
46 #define CS42L42_DEVID_CD		(CS42L42_PAGE_10 + 0x02)
47 #define CS42L42_DEVID_E			(CS42L42_PAGE_10 + 0x03)
48 #define CS42L42_FABID			(CS42L42_PAGE_10 + 0x04)
49 #define CS42L42_REVID			(CS42L42_PAGE_10 + 0x05)
50 #define CS42L42_FRZ_CTL			(CS42L42_PAGE_10 + 0x06)
51 
52 #define CS42L42_SRC_CTL			(CS42L42_PAGE_10 + 0x07)
53 #define CS42L42_SRC_BYPASS_DAC_SHIFT	1
54 #define CS42L42_SRC_BYPASS_DAC_MASK	(1 << CS42L42_SRC_BYPASS_DAC_SHIFT)
55 
56 #define CS42L42_MCLK_STATUS		(CS42L42_PAGE_10 + 0x08)
57 
58 #define CS42L42_MCLK_CTL		(CS42L42_PAGE_10 + 0x09)
59 #define CS42L42_INTERNAL_FS_SHIFT	1
60 #define CS42L42_INTERNAL_FS_MASK	(1 << CS42L42_INTERNAL_FS_SHIFT)
61 
62 #define CS42L42_SFTRAMP_RATE		(CS42L42_PAGE_10 + 0x0A)
63 #define CS42L42_SLOW_START_ENABLE	(CS42L42_PAGE_10 + 0x0B)
64 #define CS42L42_SLOW_START_EN_MASK	GENMASK(6, 4)
65 #define CS42L42_SLOW_START_EN_SHIFT	4
66 #define CS42L42_I2C_DEBOUNCE		(CS42L42_PAGE_10 + 0x0E)
67 #define CS42L42_I2C_STRETCH		(CS42L42_PAGE_10 + 0x0F)
68 #define CS42L42_I2C_TIMEOUT		(CS42L42_PAGE_10 + 0x10)
69 
70 /* Page 0x11 Power and Headset Detect Registers */
71 #define CS42L42_PWR_CTL1		(CS42L42_PAGE_11 + 0x01)
72 #define CS42L42_ASP_DAO_PDN_SHIFT	7
73 #define CS42L42_ASP_DAO_PDN_MASK	(1 << CS42L42_ASP_DAO_PDN_SHIFT)
74 #define CS42L42_ASP_DAI_PDN_SHIFT	6
75 #define CS42L42_ASP_DAI_PDN_MASK	(1 << CS42L42_ASP_DAI_PDN_SHIFT)
76 #define CS42L42_MIXER_PDN_SHIFT		5
77 #define CS42L42_MIXER_PDN_MASK		(1 << CS42L42_MIXER_PDN_SHIFT)
78 #define CS42L42_EQ_PDN_SHIFT		4
79 #define CS42L42_EQ_PDN_MASK		(1 << CS42L42_EQ_PDN_SHIFT)
80 #define CS42L42_HP_PDN_SHIFT		3
81 #define CS42L42_HP_PDN_MASK		(1 << CS42L42_HP_PDN_SHIFT)
82 #define CS42L42_ADC_PDN_SHIFT		2
83 #define CS42L42_ADC_PDN_MASK		(1 << CS42L42_ADC_PDN_SHIFT)
84 #define CS42L42_PDN_ALL_SHIFT		0
85 #define CS42L42_PDN_ALL_MASK		(1 << CS42L42_PDN_ALL_SHIFT)
86 
87 #define CS42L42_PWR_CTL2		(CS42L42_PAGE_11 + 0x02)
88 #define CS42L42_ADC_SRC_PDNB_SHIFT	0
89 #define CS42L42_ADC_SRC_PDNB_MASK	(1 << CS42L42_ADC_SRC_PDNB_SHIFT)
90 #define CS42L42_DAC_SRC_PDNB_SHIFT	1
91 #define CS42L42_DAC_SRC_PDNB_MASK	(1 << CS42L42_DAC_SRC_PDNB_SHIFT)
92 #define CS42L42_ASP_DAI1_PDN_SHIFT	2
93 #define CS42L42_ASP_DAI1_PDN_MASK	(1 << CS42L42_ASP_DAI1_PDN_SHIFT)
94 #define CS42L42_SRC_PDN_OVERRIDE_SHIFT	3
95 #define CS42L42_SRC_PDN_OVERRIDE_MASK	(1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT)
96 #define CS42L42_DISCHARGE_FILT_SHIFT	4
97 #define CS42L42_DISCHARGE_FILT_MASK	(1 << CS42L42_DISCHARGE_FILT_SHIFT)
98 
99 #define CS42L42_PWR_CTL3			(CS42L42_PAGE_11 + 0x03)
100 #define CS42L42_RING_SENSE_PDNB_SHIFT		1
101 #define CS42L42_RING_SENSE_PDNB_MASK		(1 << CS42L42_RING_SENSE_PDNB_SHIFT)
102 #define CS42L42_VPMON_PDNB_SHIFT		2
103 #define CS42L42_VPMON_PDNB_MASK			(1 << CS42L42_VPMON_PDNB_SHIFT)
104 #define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT	5
105 #define CS42L42_SW_CLK_STP_STAT_SEL_MASK	(3 << CS42L42_SW_CLK_STP_STAT_SEL_SHIFT)
106 
107 #define CS42L42_RSENSE_CTL1			(CS42L42_PAGE_11 + 0x04)
108 #define CS42L42_RS_TRIM_R_SHIFT			0
109 #define CS42L42_RS_TRIM_R_MASK			(1 << CS42L42_RS_TRIM_R_SHIFT)
110 #define CS42L42_RS_TRIM_T_SHIFT			1
111 #define CS42L42_RS_TRIM_T_MASK			(1 << CS42L42_RS_TRIM_T_SHIFT)
112 #define CS42L42_HPREF_RS_SHIFT			2
113 #define CS42L42_HPREF_RS_MASK			(1 << CS42L42_HPREF_RS_SHIFT)
114 #define CS42L42_HSBIAS_FILT_REF_RS_SHIFT	3
115 #define CS42L42_HSBIAS_FILT_REF_RS_MASK		(1 << CS42L42_HSBIAS_FILT_REF_RS_SHIFT)
116 #define CS42L42_RING_SENSE_PU_HIZ_SHIFT		6
117 #define CS42L42_RING_SENSE_PU_HIZ_MASK		(1 << CS42L42_RING_SENSE_PU_HIZ_SHIFT)
118 
119 #define CS42L42_RSENSE_CTL2		(CS42L42_PAGE_11 + 0x05)
120 #define CS42L42_TS_RS_GATE_SHIFT	7
121 #define CS42L42_TS_RS_GATE_MAS		(1 << CS42L42_TS_RS_GATE_SHIFT)
122 
123 #define CS42L42_OSC_SWITCH		(CS42L42_PAGE_11 + 0x07)
124 #define CS42L42_SCLK_PRESENT_SHIFT	0
125 #define CS42L42_SCLK_PRESENT_MASK	(1 << CS42L42_SCLK_PRESENT_SHIFT)
126 
127 #define CS42L42_OSC_SWITCH_STATUS	(CS42L42_PAGE_11 + 0x09)
128 #define CS42L42_OSC_SW_SEL_STAT_SHIFT	0
129 #define CS42L42_OSC_SW_SEL_STAT_MASK	(3 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
130 #define CS42L42_OSC_PDNB_STAT_SHIFT	2
131 #define CS42L42_OSC_PDNB_STAT_MASK	(1 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
132 
133 #define CS42L42_RSENSE_CTL3			(CS42L42_PAGE_11 + 0x12)
134 #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT	0
135 #define CS42L42_RS_RISE_DBNCE_TIME_MASK		(7 << CS42L42_RS_RISE_DBNCE_TIME_SHIFT)
136 #define CS42L42_RS_FALL_DBNCE_TIME_SHIFT	3
137 #define CS42L42_RS_FALL_DBNCE_TIME_MASK		(7 << CS42L42_RS_FALL_DBNCE_TIME_SHIFT)
138 #define CS42L42_RS_PU_EN_SHIFT			6
139 #define CS42L42_RS_PU_EN_MASK			(1 << CS42L42_RS_PU_EN_SHIFT)
140 #define CS42L42_RS_INV_SHIFT			7
141 #define CS42L42_RS_INV_MASK			(1 << CS42L42_RS_INV_SHIFT)
142 
143 #define CS42L42_TSENSE_CTL			(CS42L42_PAGE_11 + 0x13)
144 #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT	0
145 #define CS42L42_TS_RISE_DBNCE_TIME_MASK		(7 << CS42L42_TS_RISE_DBNCE_TIME_SHIFT)
146 #define CS42L42_TS_FALL_DBNCE_TIME_SHIFT	3
147 #define CS42L42_TS_FALL_DBNCE_TIME_MASK		(7 << CS42L42_TS_FALL_DBNCE_TIME_SHIFT)
148 #define CS42L42_TS_INV_SHIFT			7
149 #define CS42L42_TS_INV_MASK			(1 << CS42L42_TS_INV_SHIFT)
150 
151 #define CS42L42_TSRS_INT_DISABLE	(CS42L42_PAGE_11 + 0x14)
152 #define CS42L42_D_RS_PLUG_DBNC_SHIFT	0
153 #define CS42L42_D_RS_PLUG_DBNC_MASK	(1 << CS42L42_D_RS_PLUG_DBNC_SHIFT)
154 #define CS42L42_D_RS_UNPLUG_DBNC_SHIFT	1
155 #define CS42L42_D_RS_UNPLUG_DBNC_MASK	(1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT)
156 #define CS42L42_D_TS_PLUG_DBNC_SHIFT	2
157 #define CS42L42_D_TS_PLUG_DBNC_MASK	(1 << CS42L42_D_TS_PLUG_DBNC_SHIFT)
158 #define CS42L42_D_TS_UNPLUG_DBNC_SHIFT	3
159 #define CS42L42_D_TS_UNPLUG_DBNC_MASK	(1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT)
160 
161 #define CS42L42_TRSENSE_STATUS		(CS42L42_PAGE_11 + 0x15)
162 #define CS42L42_RS_PLUG_DBNC_SHIFT	0
163 #define CS42L42_RS_PLUG_DBNC_MASK	(1 << CS42L42_RS_PLUG_DBNC_SHIFT)
164 #define CS42L42_RS_UNPLUG_DBNC_SHIFT	1
165 #define CS42L42_RS_UNPLUG_DBNC_MASK	(1 << CS42L42_RS_UNPLUG_DBNC_SHIFT)
166 #define CS42L42_TS_PLUG_DBNC_SHIFT	2
167 #define CS42L42_TS_PLUG_DBNC_MASK	(1 << CS42L42_TS_PLUG_DBNC_SHIFT)
168 #define CS42L42_TS_UNPLUG_DBNC_SHIFT	3
169 #define CS42L42_TS_UNPLUG_DBNC_MASK	(1 << CS42L42_TS_UNPLUG_DBNC_SHIFT)
170 
171 #define CS42L42_HSDET_CTL1		(CS42L42_PAGE_11 + 0x1F)
172 #define CS42L42_HSDET_COMP1_LVL_SHIFT	0
173 #define CS42L42_HSDET_COMP1_LVL_MASK	(15 << CS42L42_HSDET_COMP1_LVL_SHIFT)
174 #define CS42L42_HSDET_COMP2_LVL_SHIFT	4
175 #define CS42L42_HSDET_COMP2_LVL_MASK	(15 << CS42L42_HSDET_COMP2_LVL_SHIFT)
176 
177 #define CS42L42_HSDET_COMP1_LVL_VAL	12 /* 1.25V Comparator */
178 #define CS42L42_HSDET_COMP2_LVL_VAL	2  /* 1.75V Comparator */
179 #define CS42L42_HSDET_COMP1_LVL_DEFAULT	7  /* 1V Comparator */
180 #define CS42L42_HSDET_COMP2_LVL_DEFAULT	7  /* 2V Comparator */
181 
182 #define CS42L42_HSDET_CTL2		(CS42L42_PAGE_11 + 0x20)
183 #define CS42L42_HSDET_AUTO_TIME_SHIFT	0
184 #define CS42L42_HSDET_AUTO_TIME_MASK	(3 << CS42L42_HSDET_AUTO_TIME_SHIFT)
185 #define CS42L42_HSBIAS_REF_SHIFT	3
186 #define CS42L42_HSBIAS_REF_MASK		(1 << CS42L42_HSBIAS_REF_SHIFT)
187 #define CS42L42_HSDET_SET_SHIFT		4
188 #define CS42L42_HSDET_SET_MASK		(3 << CS42L42_HSDET_SET_SHIFT)
189 #define CS42L42_HSDET_CTRL_SHIFT	6
190 #define CS42L42_HSDET_CTRL_MASK		(3 << CS42L42_HSDET_CTRL_SHIFT)
191 
192 #define CS42L42_HS_SWITCH_CTL		(CS42L42_PAGE_11 + 0x21)
193 #define CS42L42_SW_GNDHS_HS4_SHIFT	0
194 #define CS42L42_SW_GNDHS_HS4_MASK	(1 << CS42L42_SW_GNDHS_HS4_SHIFT)
195 #define CS42L42_SW_GNDHS_HS3_SHIFT	1
196 #define CS42L42_SW_GNDHS_HS3_MASK	(1 << CS42L42_SW_GNDHS_HS3_SHIFT)
197 #define CS42L42_SW_HSB_HS4_SHIFT	2
198 #define CS42L42_SW_HSB_HS4_MASK		(1 << CS42L42_SW_HSB_HS4_SHIFT)
199 #define CS42L42_SW_HSB_HS3_SHIFT	3
200 #define CS42L42_SW_HSB_HS3_MASK		(1 << CS42L42_SW_HSB_HS3_SHIFT)
201 #define CS42L42_SW_HSB_FILT_HS4_SHIFT	4
202 #define CS42L42_SW_HSB_FILT_HS4_MASK	(1 << CS42L42_SW_HSB_FILT_HS4_SHIFT)
203 #define CS42L42_SW_HSB_FILT_HS3_SHIFT	5
204 #define CS42L42_SW_HSB_FILT_HS3_MASK	(1 << CS42L42_SW_HSB_FILT_HS3_SHIFT)
205 #define CS42L42_SW_REF_HS4_SHIFT	6
206 #define CS42L42_SW_REF_HS4_MASK		(1 << CS42L42_SW_REF_HS4_SHIFT)
207 #define CS42L42_SW_REF_HS3_SHIFT	7
208 #define CS42L42_SW_REF_HS3_MASK		(1 << CS42L42_SW_REF_HS3_SHIFT)
209 
210 #define CS42L42_HS_DET_STATUS		(CS42L42_PAGE_11 + 0x24)
211 #define CS42L42_HSDET_TYPE_SHIFT	0
212 #define CS42L42_HSDET_TYPE_MASK		(3 << CS42L42_HSDET_TYPE_SHIFT)
213 #define CS42L42_HSDET_COMP1_OUT_SHIFT	6
214 #define CS42L42_HSDET_COMP1_OUT_MASK	(1 << CS42L42_HSDET_COMP1_OUT_SHIFT)
215 #define CS42L42_HSDET_COMP2_OUT_SHIFT	7
216 #define CS42L42_HSDET_COMP2_OUT_MASK	(1 << CS42L42_HSDET_COMP2_OUT_SHIFT)
217 #define CS42L42_PLUG_CTIA		0
218 #define CS42L42_PLUG_OMTP		1
219 #define CS42L42_PLUG_HEADPHONE		2
220 #define CS42L42_PLUG_INVALID		3
221 
222 #define CS42L42_HSDET_SW_COMP1		((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
223 					 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
224 					 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \
225 					 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
226 					 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
227 					 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
228 					 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
229 					 (1 << CS42L42_SW_REF_HS3_SHIFT))
230 #define CS42L42_HSDET_SW_COMP2		((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
231 					 (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
232 					 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
233 					 (1 << CS42L42_SW_HSB_HS3_SHIFT) | \
234 					 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
235 					 (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
236 					 (1 << CS42L42_SW_REF_HS4_SHIFT) | \
237 					 (0 << CS42L42_SW_REF_HS3_SHIFT))
238 #define CS42L42_HSDET_SW_TYPE1		((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
239 					 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
240 					 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \
241 					 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
242 					 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
243 					 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
244 					 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
245 					 (1 << CS42L42_SW_REF_HS3_SHIFT))
246 #define CS42L42_HSDET_SW_TYPE2		((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
247 					 (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
248 					 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
249 					 (1 << CS42L42_SW_HSB_HS3_SHIFT) | \
250 					 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
251 					 (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
252 					 (1 << CS42L42_SW_REF_HS4_SHIFT) | \
253 					 (0 << CS42L42_SW_REF_HS3_SHIFT))
254 #define CS42L42_HSDET_SW_TYPE3		((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
255 					 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
256 					 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
257 					 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
258 					 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
259 					 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
260 					 (1 << CS42L42_SW_REF_HS4_SHIFT) | \
261 					 (1 << CS42L42_SW_REF_HS3_SHIFT))
262 #define CS42L42_HSDET_SW_TYPE4		((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
263 					 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
264 					 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \
265 					 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
266 					 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
267 					 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
268 					 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
269 					 (1 << CS42L42_SW_REF_HS3_SHIFT))
270 
271 #define CS42L42_HSDET_COMP_TYPE1	1
272 #define CS42L42_HSDET_COMP_TYPE2	2
273 #define CS42L42_HSDET_COMP_TYPE3	0
274 #define CS42L42_HSDET_COMP_TYPE4	3
275 
276 #define CS42L42_HS_CLAMP_DISABLE	(CS42L42_PAGE_11 + 0x29)
277 #define CS42L42_HS_CLAMP_DISABLE_SHIFT	0
278 #define CS42L42_HS_CLAMP_DISABLE_MASK	(1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)
279 
280 /* Page 0x12 Clocking Registers */
281 #define CS42L42_MCLK_SRC_SEL		(CS42L42_PAGE_12 + 0x01)
282 #define CS42L42_MCLKDIV_SHIFT		1
283 #define CS42L42_MCLKDIV_MASK		(1 << CS42L42_MCLKDIV_SHIFT)
284 #define CS42L42_MCLK_SRC_SEL_SHIFT	0
285 #define CS42L42_MCLK_SRC_SEL_MASK	(1 << CS42L42_MCLK_SRC_SEL_SHIFT)
286 
287 #define CS42L42_SPDIF_CLK_CFG		(CS42L42_PAGE_12 + 0x02)
288 #define CS42L42_FSYNC_PW_LOWER		(CS42L42_PAGE_12 + 0x03)
289 
290 #define CS42L42_FSYNC_PW_UPPER			(CS42L42_PAGE_12 + 0x04)
291 #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT		0
292 #define CS42L42_FSYNC_PULSE_WIDTH_MASK		(0xff << \
293 					CS42L42_FSYNC_PULSE_WIDTH_SHIFT)
294 
295 #define CS42L42_FSYNC_P_LOWER		(CS42L42_PAGE_12 + 0x05)
296 
297 #define CS42L42_FSYNC_P_UPPER		(CS42L42_PAGE_12 + 0x06)
298 #define CS42L42_FSYNC_PERIOD_SHIFT	0
299 #define CS42L42_FSYNC_PERIOD_MASK	(0xff << CS42L42_FSYNC_PERIOD_SHIFT)
300 
301 #define CS42L42_ASP_CLK_CFG		(CS42L42_PAGE_12 + 0x07)
302 #define CS42L42_ASP_SCLK_EN_SHIFT	5
303 #define CS42L42_ASP_SCLK_EN_MASK	(1 << CS42L42_ASP_SCLK_EN_SHIFT)
304 #define CS42L42_ASP_MASTER_MODE		0x01
305 #define CS42L42_ASP_SLAVE_MODE		0x00
306 #define CS42L42_ASP_MODE_SHIFT		4
307 #define CS42L42_ASP_MODE_MASK		(1 << CS42L42_ASP_MODE_SHIFT)
308 #define CS42L42_ASP_SCPOL_SHIFT		2
309 #define CS42L42_ASP_SCPOL_MASK		(3 << CS42L42_ASP_SCPOL_SHIFT)
310 #define CS42L42_ASP_SCPOL_NOR		3
311 #define CS42L42_ASP_LCPOL_SHIFT		0
312 #define CS42L42_ASP_LCPOL_MASK		(3 << CS42L42_ASP_LCPOL_SHIFT)
313 #define CS42L42_ASP_LCPOL_INV		3
314 
315 #define CS42L42_ASP_FRM_CFG		(CS42L42_PAGE_12 + 0x08)
316 #define CS42L42_ASP_STP_SHIFT		4
317 #define CS42L42_ASP_STP_MASK		(1 << CS42L42_ASP_STP_SHIFT)
318 #define CS42L42_ASP_5050_SHIFT		3
319 #define CS42L42_ASP_5050_MASK		(1 << CS42L42_ASP_5050_SHIFT)
320 #define CS42L42_ASP_FSD_SHIFT		0
321 #define CS42L42_ASP_FSD_MASK		(7 << CS42L42_ASP_FSD_SHIFT)
322 #define CS42L42_ASP_FSD_0_5		1
323 #define CS42L42_ASP_FSD_1_0		2
324 #define CS42L42_ASP_FSD_1_5		3
325 #define CS42L42_ASP_FSD_2_0		4
326 
327 #define CS42L42_FS_RATE_EN		(CS42L42_PAGE_12 + 0x09)
328 #define CS42L42_FS_EN_SHIFT		0
329 #define CS42L42_FS_EN_MASK		(0xf << CS42L42_FS_EN_SHIFT)
330 #define CS42L42_FS_EN_IASRC_96K		0x1
331 #define CS42L42_FS_EN_OASRC_96K		0x2
332 
333 #define CS42L42_IN_ASRC_CLK		(CS42L42_PAGE_12 + 0x0A)
334 #define CS42L42_CLK_IASRC_SEL_SHIFT	0
335 #define CS42L42_CLK_IASRC_SEL_MASK	(1 << CS42L42_CLK_IASRC_SEL_SHIFT)
336 #define CS42L42_CLK_IASRC_SEL_6		0
337 #define CS42L42_CLK_IASRC_SEL_12	1
338 
339 #define CS42L42_OUT_ASRC_CLK		(CS42L42_PAGE_12 + 0x0B)
340 #define CS42L42_CLK_OASRC_SEL_SHIFT	0
341 #define CS42L42_CLK_OASRC_SEL_MASK	(1 << CS42L42_CLK_OASRC_SEL_SHIFT)
342 #define CS42L42_CLK_OASRC_SEL_12	1
343 
344 #define CS42L42_PLL_DIV_CFG1		(CS42L42_PAGE_12 + 0x0C)
345 #define CS42L42_SCLK_PREDIV_SHIFT	0
346 #define CS42L42_SCLK_PREDIV_MASK	(3 << CS42L42_SCLK_PREDIV_SHIFT)
347 
348 /* Page 0x13 Interrupt Registers */
349 /* Interrupts */
350 #define CS42L42_ADC_OVFL_STATUS		(CS42L42_PAGE_13 + 0x01)
351 #define CS42L42_MIXER_STATUS		(CS42L42_PAGE_13 + 0x02)
352 #define CS42L42_SRC_STATUS		(CS42L42_PAGE_13 + 0x03)
353 #define CS42L42_ASP_RX_STATUS		(CS42L42_PAGE_13 + 0x04)
354 #define CS42L42_ASP_TX_STATUS		(CS42L42_PAGE_13 + 0x05)
355 #define CS42L42_CODEC_STATUS		(CS42L42_PAGE_13 + 0x08)
356 #define CS42L42_DET_INT_STATUS1		(CS42L42_PAGE_13 + 0x09)
357 #define CS42L42_DET_INT_STATUS2		(CS42L42_PAGE_13 + 0x0A)
358 #define CS42L42_SRCPL_INT_STATUS	(CS42L42_PAGE_13 + 0x0B)
359 #define CS42L42_VPMON_STATUS		(CS42L42_PAGE_13 + 0x0D)
360 #define CS42L42_PLL_LOCK_STATUS		(CS42L42_PAGE_13 + 0x0E)
361 #define CS42L42_TSRS_PLUG_STATUS	(CS42L42_PAGE_13 + 0x0F)
362 /* Masks */
363 #define CS42L42_ADC_OVFL_INT_MASK	(CS42L42_PAGE_13 + 0x16)
364 #define CS42L42_ADC_OVFL_SHIFT		0
365 #define CS42L42_ADC_OVFL_MASK		(1 << CS42L42_ADC_OVFL_SHIFT)
366 #define CS42L42_ADC_OVFL_VAL_MASK	CS42L42_ADC_OVFL_MASK
367 
368 #define CS42L42_MIXER_INT_MASK		(CS42L42_PAGE_13 + 0x17)
369 #define CS42L42_MIX_CHB_OVFL_SHIFT	0
370 #define CS42L42_MIX_CHB_OVFL_MASK	(1 << CS42L42_MIX_CHB_OVFL_SHIFT)
371 #define CS42L42_MIX_CHA_OVFL_SHIFT	1
372 #define CS42L42_MIX_CHA_OVFL_MASK	(1 << CS42L42_MIX_CHA_OVFL_SHIFT)
373 #define CS42L42_EQ_OVFL_SHIFT		2
374 #define CS42L42_EQ_OVFL_MASK		(1 << CS42L42_EQ_OVFL_SHIFT)
375 #define CS42L42_EQ_BIQUAD_OVFL_SHIFT	3
376 #define CS42L42_EQ_BIQUAD_OVFL_MASK	(1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)
377 #define CS42L42_MIXER_VAL_MASK		(CS42L42_MIX_CHB_OVFL_MASK | \
378 					CS42L42_MIX_CHA_OVFL_MASK | \
379 					CS42L42_EQ_OVFL_MASK | \
380 					CS42L42_EQ_BIQUAD_OVFL_MASK)
381 
382 #define CS42L42_SRC_INT_MASK		(CS42L42_PAGE_13 + 0x18)
383 #define CS42L42_SRC_ILK_SHIFT		0
384 #define CS42L42_SRC_ILK_MASK		(1 << CS42L42_SRC_ILK_SHIFT)
385 #define CS42L42_SRC_OLK_SHIFT		1
386 #define CS42L42_SRC_OLK_MASK		(1 << CS42L42_SRC_OLK_SHIFT)
387 #define CS42L42_SRC_IUNLK_SHIFT		2
388 #define CS42L42_SRC_IUNLK_MASK		(1 << CS42L42_SRC_IUNLK_SHIFT)
389 #define CS42L42_SRC_OUNLK_SHIFT		3
390 #define CS42L42_SRC_OUNLK_MASK		(1 << CS42L42_SRC_OUNLK_SHIFT)
391 #define CS42L42_SRC_VAL_MASK		(CS42L42_SRC_ILK_MASK | \
392 					CS42L42_SRC_OLK_MASK | \
393 					CS42L42_SRC_IUNLK_MASK | \
394 					CS42L42_SRC_OUNLK_MASK)
395 
396 #define CS42L42_ASP_RX_INT_MASK		(CS42L42_PAGE_13 + 0x19)
397 #define CS42L42_ASPRX_NOLRCK_SHIFT	0
398 #define CS42L42_ASPRX_NOLRCK_MASK	(1 << CS42L42_ASPRX_NOLRCK_SHIFT)
399 #define CS42L42_ASPRX_EARLY_SHIFT	1
400 #define CS42L42_ASPRX_EARLY_MASK	(1 << CS42L42_ASPRX_EARLY_SHIFT)
401 #define CS42L42_ASPRX_LATE_SHIFT	2
402 #define CS42L42_ASPRX_LATE_MASK		(1 << CS42L42_ASPRX_LATE_SHIFT)
403 #define CS42L42_ASPRX_ERROR_SHIFT	3
404 #define CS42L42_ASPRX_ERROR_MASK	(1 << CS42L42_ASPRX_ERROR_SHIFT)
405 #define CS42L42_ASPRX_OVLD_SHIFT	4
406 #define CS42L42_ASPRX_OVLD_MASK		(1 << CS42L42_ASPRX_OVLD_SHIFT)
407 #define CS42L42_ASP_RX_VAL_MASK		(CS42L42_ASPRX_NOLRCK_MASK | \
408 					CS42L42_ASPRX_EARLY_MASK | \
409 					CS42L42_ASPRX_LATE_MASK | \
410 					CS42L42_ASPRX_ERROR_MASK | \
411 					CS42L42_ASPRX_OVLD_MASK)
412 
413 #define CS42L42_ASP_TX_INT_MASK		(CS42L42_PAGE_13 + 0x1A)
414 #define CS42L42_ASPTX_NOLRCK_SHIFT	0
415 #define CS42L42_ASPTX_NOLRCK_MASK	(1 << CS42L42_ASPTX_NOLRCK_SHIFT)
416 #define CS42L42_ASPTX_EARLY_SHIFT	1
417 #define CS42L42_ASPTX_EARLY_MASK	(1 << CS42L42_ASPTX_EARLY_SHIFT)
418 #define CS42L42_ASPTX_LATE_SHIFT	2
419 #define CS42L42_ASPTX_LATE_MASK		(1 << CS42L42_ASPTX_LATE_SHIFT)
420 #define CS42L42_ASPTX_SMERROR_SHIFT	3
421 #define CS42L42_ASPTX_SMERROR_MASK	(1 << CS42L42_ASPTX_SMERROR_SHIFT)
422 #define CS42L42_ASP_TX_VAL_MASK		(CS42L42_ASPTX_NOLRCK_MASK | \
423 					CS42L42_ASPTX_EARLY_MASK | \
424 					CS42L42_ASPTX_LATE_MASK | \
425 					CS42L42_ASPTX_SMERROR_MASK)
426 
427 #define CS42L42_CODEC_INT_MASK		(CS42L42_PAGE_13 + 0x1B)
428 #define CS42L42_PDN_DONE_SHIFT		0
429 #define CS42L42_PDN_DONE_MASK		(1 << CS42L42_PDN_DONE_SHIFT)
430 #define CS42L42_HSDET_AUTO_DONE_SHIFT	1
431 #define CS42L42_HSDET_AUTO_DONE_MASK	(1 << CS42L42_HSDET_AUTO_DONE_SHIFT)
432 #define CS42L42_CODEC_VAL_MASK		(CS42L42_PDN_DONE_MASK | \
433 					CS42L42_HSDET_AUTO_DONE_MASK)
434 
435 #define CS42L42_SRCPL_INT_MASK		(CS42L42_PAGE_13 + 0x1C)
436 #define CS42L42_SRCPL_ADC_LK_SHIFT	0
437 #define CS42L42_SRCPL_ADC_LK_MASK	(1 << CS42L42_SRCPL_ADC_LK_SHIFT)
438 #define CS42L42_SRCPL_DAC_LK_SHIFT	2
439 #define CS42L42_SRCPL_DAC_LK_MASK	(1 << CS42L42_SRCPL_DAC_LK_SHIFT)
440 #define CS42L42_SRCPL_ADC_UNLK_SHIFT	5
441 #define CS42L42_SRCPL_ADC_UNLK_MASK	(1 << CS42L42_SRCPL_ADC_UNLK_SHIFT)
442 #define CS42L42_SRCPL_DAC_UNLK_SHIFT	6
443 #define CS42L42_SRCPL_DAC_UNLK_MASK	(1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)
444 #define CS42L42_SRCPL_VAL_MASK		(CS42L42_SRCPL_ADC_LK_MASK | \
445 					CS42L42_SRCPL_DAC_LK_MASK | \
446 					CS42L42_SRCPL_ADC_UNLK_MASK | \
447 					CS42L42_SRCPL_DAC_UNLK_MASK)
448 
449 #define CS42L42_VPMON_INT_MASK		(CS42L42_PAGE_13 + 0x1E)
450 #define CS42L42_VPMON_SHIFT		0
451 #define CS42L42_VPMON_MASK		(1 << CS42L42_VPMON_SHIFT)
452 #define CS42L42_VPMON_VAL_MASK		CS42L42_VPMON_MASK
453 
454 #define CS42L42_PLL_LOCK_INT_MASK	(CS42L42_PAGE_13 + 0x1F)
455 #define CS42L42_PLL_LOCK_SHIFT		0
456 #define CS42L42_PLL_LOCK_MASK		(1 << CS42L42_PLL_LOCK_SHIFT)
457 #define CS42L42_PLL_LOCK_VAL_MASK	CS42L42_PLL_LOCK_MASK
458 
459 #define CS42L42_TSRS_PLUG_INT_MASK	(CS42L42_PAGE_13 + 0x20)
460 #define CS42L42_RS_PLUG_SHIFT		0
461 #define CS42L42_RS_PLUG_MASK		(1 << CS42L42_RS_PLUG_SHIFT)
462 #define CS42L42_RS_UNPLUG_SHIFT		1
463 #define CS42L42_RS_UNPLUG_MASK		(1 << CS42L42_RS_UNPLUG_SHIFT)
464 #define CS42L42_TS_PLUG_SHIFT		2
465 #define CS42L42_TS_PLUG_MASK		(1 << CS42L42_TS_PLUG_SHIFT)
466 #define CS42L42_TS_UNPLUG_SHIFT		3
467 #define CS42L42_TS_UNPLUG_MASK		(1 << CS42L42_TS_UNPLUG_SHIFT)
468 #define CS42L42_TSRS_PLUG_VAL_MASK	(CS42L42_RS_PLUG_MASK | \
469 					CS42L42_RS_UNPLUG_MASK | \
470 					CS42L42_TS_PLUG_MASK | \
471 					CS42L42_TS_UNPLUG_MASK)
472 #define CS42L42_TS_PLUG			3
473 #define CS42L42_TS_UNPLUG		0
474 #define CS42L42_TS_TRANS		1
475 
476 /*
477  * NOTE: PLL_START must be 0 while both ADC_PDN=1 and HP_PDN=1.
478  * Otherwise it will prevent FILT+ from charging properly.
479  */
480 #define CS42L42_PLL_CTL1		(CS42L42_PAGE_15 + 0x01)
481 #define CS42L42_PLL_START_SHIFT		0
482 #define CS42L42_PLL_START_MASK		(1 << CS42L42_PLL_START_SHIFT)
483 
484 #define CS42L42_PLL_DIV_FRAC0		(CS42L42_PAGE_15 + 0x02)
485 #define CS42L42_PLL_DIV_FRAC_SHIFT	0
486 #define CS42L42_PLL_DIV_FRAC_MASK	(0xff << CS42L42_PLL_DIV_FRAC_SHIFT)
487 
488 #define CS42L42_PLL_DIV_FRAC1		(CS42L42_PAGE_15 + 0x03)
489 #define CS42L42_PLL_DIV_FRAC2		(CS42L42_PAGE_15 + 0x04)
490 
491 #define CS42L42_PLL_DIV_INT		(CS42L42_PAGE_15 + 0x05)
492 #define CS42L42_PLL_DIV_INT_SHIFT	0
493 #define CS42L42_PLL_DIV_INT_MASK	(0xff << CS42L42_PLL_DIV_INT_SHIFT)
494 
495 #define CS42L42_PLL_CTL3		(CS42L42_PAGE_15 + 0x08)
496 #define CS42L42_PLL_DIVOUT_SHIFT	0
497 #define CS42L42_PLL_DIVOUT_MASK		(0xff << CS42L42_PLL_DIVOUT_SHIFT)
498 
499 #define CS42L42_PLL_CAL_RATIO		(CS42L42_PAGE_15 + 0x0A)
500 #define CS42L42_PLL_CAL_RATIO_SHIFT	0
501 #define CS42L42_PLL_CAL_RATIO_MASK	(0xff << CS42L42_PLL_CAL_RATIO_SHIFT)
502 
503 #define CS42L42_PLL_CTL4		(CS42L42_PAGE_15 + 0x1B)
504 #define CS42L42_PLL_MODE_SHIFT		0
505 #define CS42L42_PLL_MODE_MASK		(3 << CS42L42_PLL_MODE_SHIFT)
506 
507 /* Page 0x19 HP Load Detect Registers */
508 #define CS42L42_LOAD_DET_RCSTAT		(CS42L42_PAGE_19 + 0x25)
509 #define CS42L42_RLA_STAT_SHIFT		0
510 #define CS42L42_RLA_STAT_MASK		(3 << CS42L42_RLA_STAT_SHIFT)
511 #define CS42L42_RLA_STAT_15_OHM		0
512 
513 #define CS42L42_LOAD_DET_DONE		(CS42L42_PAGE_19 + 0x26)
514 #define CS42L42_HPLOAD_DET_DONE_SHIFT	0
515 #define CS42L42_HPLOAD_DET_DONE_MASK	(1 << CS42L42_HPLOAD_DET_DONE_SHIFT)
516 
517 #define CS42L42_LOAD_DET_EN		(CS42L42_PAGE_19 + 0x27)
518 #define CS42L42_HP_LD_EN_SHIFT		0
519 #define CS42L42_HP_LD_EN_MASK		(1 << CS42L42_HP_LD_EN_SHIFT)
520 
521 /* Page 0x1B Headset Interface Registers */
522 #define CS42L42_HSBIAS_SC_AUTOCTL		(CS42L42_PAGE_1B + 0x70)
523 #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT		0
524 #define CS42L42_HSBIAS_SENSE_TRIP_MASK		(7 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)
525 #define CS42L42_TIP_SENSE_EN_SHIFT		5
526 #define CS42L42_TIP_SENSE_EN_MASK		(1 << CS42L42_TIP_SENSE_EN_SHIFT)
527 #define CS42L42_AUTO_HSBIAS_HIZ_SHIFT		6
528 #define CS42L42_AUTO_HSBIAS_HIZ_MASK		(1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT)
529 #define CS42L42_HSBIAS_SENSE_EN_SHIFT		7
530 #define CS42L42_HSBIAS_SENSE_EN_MASK		(1 << CS42L42_HSBIAS_SENSE_EN_SHIFT)
531 
532 #define CS42L42_WAKE_CTL		(CS42L42_PAGE_1B + 0x71)
533 #define CS42L42_WAKEB_CLEAR_SHIFT	0
534 #define CS42L42_WAKEB_CLEAR_MASK	(1 << CS42L42_WAKEB_CLEAR_SHIFT)
535 #define CS42L42_WAKEB_MODE_SHIFT	5
536 #define CS42L42_WAKEB_MODE_MASK		(1 << CS42L42_WAKEB_MODE_SHIFT)
537 #define CS42L42_M_HP_WAKE_SHIFT		6
538 #define CS42L42_M_HP_WAKE_MASK		(1 << CS42L42_M_HP_WAKE_SHIFT)
539 #define CS42L42_M_MIC_WAKE_SHIFT	7
540 #define CS42L42_M_MIC_WAKE_MASK		(1 << CS42L42_M_MIC_WAKE_SHIFT)
541 
542 #define CS42L42_ADC_DISABLE_MUTE		(CS42L42_PAGE_1B + 0x72)
543 #define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT	7
544 #define CS42L42_ADC_DISABLE_S0_MUTE_MASK	(1 << CS42L42_ADC_DISABLE_S0_MUTE_SHIFT)
545 
546 #define CS42L42_TIPSENSE_CTL			(CS42L42_PAGE_1B + 0x73)
547 #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT	0
548 #define CS42L42_TIP_SENSE_DEBOUNCE_MASK		(3 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)
549 #define CS42L42_TIP_SENSE_INV_SHIFT		5
550 #define CS42L42_TIP_SENSE_INV_MASK		(1 << CS42L42_TIP_SENSE_INV_SHIFT)
551 #define CS42L42_TIP_SENSE_CTRL_SHIFT		6
552 #define CS42L42_TIP_SENSE_CTRL_MASK		(3 << CS42L42_TIP_SENSE_CTRL_SHIFT)
553 
554 /*
555  * NOTE: DETECT_MODE must be 0 while both ADC_PDN=1 and HP_PDN=1.
556  * Otherwise it will prevent FILT+ from charging properly.
557  */
558 #define CS42L42_MISC_DET_CTL		(CS42L42_PAGE_1B + 0x74)
559 #define CS42L42_PDN_MIC_LVL_DET_SHIFT	0
560 #define CS42L42_PDN_MIC_LVL_DET_MASK	(1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)
561 #define CS42L42_HSBIAS_CTL_SHIFT	1
562 #define CS42L42_HSBIAS_CTL_MASK		(3 << CS42L42_HSBIAS_CTL_SHIFT)
563 #define CS42L42_DETECT_MODE_SHIFT	3
564 #define CS42L42_DETECT_MODE_MASK	(3 << CS42L42_DETECT_MODE_SHIFT)
565 
566 #define CS42L42_MIC_DET_CTL1		(CS42L42_PAGE_1B + 0x75)
567 #define CS42L42_HS_DET_LEVEL_SHIFT	0
568 #define CS42L42_HS_DET_LEVEL_MASK	(0x3F << CS42L42_HS_DET_LEVEL_SHIFT)
569 #define CS42L42_EVENT_STAT_SEL_SHIFT	6
570 #define CS42L42_EVENT_STAT_SEL_MASK	(1 << CS42L42_EVENT_STAT_SEL_SHIFT)
571 #define CS42L42_LATCH_TO_VP_SHIFT	7
572 #define CS42L42_LATCH_TO_VP_MASK	(1 << CS42L42_LATCH_TO_VP_SHIFT)
573 
574 #define CS42L42_MIC_DET_CTL2		(CS42L42_PAGE_1B + 0x76)
575 #define CS42L42_DEBOUNCE_TIME_SHIFT	5
576 #define CS42L42_DEBOUNCE_TIME_MASK	(0x07 << CS42L42_DEBOUNCE_TIME_SHIFT)
577 
578 #define CS42L42_DET_STATUS1		(CS42L42_PAGE_1B + 0x77)
579 #define CS42L42_HSBIAS_HIZ_MODE_SHIFT	6
580 #define CS42L42_HSBIAS_HIZ_MODE_MASK	(1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT)
581 #define CS42L42_TIP_SENSE_SHIFT		7
582 #define CS42L42_TIP_SENSE_MASK		(1 << CS42L42_TIP_SENSE_SHIFT)
583 
584 #define CS42L42_DET_STATUS2		(CS42L42_PAGE_1B + 0x78)
585 #define CS42L42_SHORT_TRUE_SHIFT	0
586 #define CS42L42_SHORT_TRUE_MASK		(1 << CS42L42_SHORT_TRUE_SHIFT)
587 #define CS42L42_HS_TRUE_SHIFT	1
588 #define CS42L42_HS_TRUE_MASK		(1 << CS42L42_HS_TRUE_SHIFT)
589 
590 #define CS42L42_DET_INT1_MASK		(CS42L42_PAGE_1B + 0x79)
591 #define CS42L42_TIP_SENSE_UNPLUG_SHIFT	5
592 #define CS42L42_TIP_SENSE_UNPLUG_MASK	(1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT)
593 #define CS42L42_TIP_SENSE_PLUG_SHIFT	6
594 #define CS42L42_TIP_SENSE_PLUG_MASK	(1 << CS42L42_TIP_SENSE_PLUG_SHIFT)
595 #define CS42L42_HSBIAS_SENSE_SHIFT	7
596 #define CS42L42_HSBIAS_SENSE_MASK	(1 << CS42L42_HSBIAS_SENSE_SHIFT)
597 #define CS42L42_DET_INT_VAL1_MASK	(CS42L42_TIP_SENSE_UNPLUG_MASK | \
598 					CS42L42_TIP_SENSE_PLUG_MASK | \
599 					CS42L42_HSBIAS_SENSE_MASK)
600 
601 #define CS42L42_DET_INT2_MASK		(CS42L42_PAGE_1B + 0x7A)
602 #define CS42L42_M_SHORT_DET_SHIFT	0
603 #define CS42L42_M_SHORT_DET_MASK	(1 << CS42L42_M_SHORT_DET_SHIFT)
604 #define CS42L42_M_SHORT_RLS_SHIFT	1
605 #define CS42L42_M_SHORT_RLS_MASK	(1 << CS42L42_M_SHORT_RLS_SHIFT)
606 #define CS42L42_M_HSBIAS_HIZ_SHIFT	2
607 #define CS42L42_M_HSBIAS_HIZ_MASK	(1 << CS42L42_M_HSBIAS_HIZ_SHIFT)
608 #define CS42L42_M_DETECT_FT_SHIFT	6
609 #define CS42L42_M_DETECT_FT_MASK	(1 << CS42L42_M_DETECT_FT_SHIFT)
610 #define CS42L42_M_DETECT_TF_SHIFT	7
611 #define CS42L42_M_DETECT_TF_MASK	(1 << CS42L42_M_DETECT_TF_SHIFT)
612 #define CS42L42_DET_INT_VAL2_MASK	(CS42L42_M_SHORT_DET_MASK | \
613 					CS42L42_M_SHORT_RLS_MASK | \
614 					CS42L42_M_HSBIAS_HIZ_MASK | \
615 					CS42L42_M_DETECT_FT_MASK | \
616 					CS42L42_M_DETECT_TF_MASK)
617 
618 /* Page 0x1C Headset Bias Registers */
619 #define CS42L42_HS_BIAS_CTL		(CS42L42_PAGE_1C + 0x03)
620 #define CS42L42_HSBIAS_RAMP_SHIFT	0
621 #define CS42L42_HSBIAS_RAMP_MASK	(3 << CS42L42_HSBIAS_RAMP_SHIFT)
622 #define CS42L42_HSBIAS_PD_SHIFT		4
623 #define CS42L42_HSBIAS_PD_MASK		(1 << CS42L42_HSBIAS_PD_SHIFT)
624 #define CS42L42_HSBIAS_CAPLESS_SHIFT	7
625 #define CS42L42_HSBIAS_CAPLESS_MASK	(1 << CS42L42_HSBIAS_CAPLESS_SHIFT)
626 
627 /* Page 0x1D ADC Registers */
628 #define CS42L42_ADC_CTL			(CS42L42_PAGE_1D + 0x01)
629 #define CS42L42_ADC_NOTCH_DIS_SHIFT		5
630 #define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT	4
631 #define CS42L42_ADC_INV_SHIFT			2
632 #define CS42L42_ADC_DIG_BOOST_SHIFT		0
633 
634 #define CS42L42_ADC_VOLUME		(CS42L42_PAGE_1D + 0x03)
635 #define CS42L42_ADC_VOL_SHIFT		0
636 
637 #define CS42L42_ADC_WNF_HPF_CTL		(CS42L42_PAGE_1D + 0x04)
638 #define CS42L42_ADC_WNF_CF_SHIFT	4
639 #define CS42L42_ADC_WNF_EN_SHIFT	3
640 #define CS42L42_ADC_HPF_CF_SHIFT	1
641 #define CS42L42_ADC_HPF_EN_SHIFT	0
642 
643 /* Page 0x1F DAC Registers */
644 #define CS42L42_DAC_CTL1		(CS42L42_PAGE_1F + 0x01)
645 #define CS42L42_DACB_INV_SHIFT		1
646 #define CS42L42_DACA_INV_SHIFT		0
647 
648 #define CS42L42_DAC_CTL2		(CS42L42_PAGE_1F + 0x06)
649 #define CS42L42_HPOUT_PULLDOWN_SHIFT	4
650 #define CS42L42_HPOUT_PULLDOWN_MASK	(15 << CS42L42_HPOUT_PULLDOWN_SHIFT)
651 #define CS42L42_HPOUT_LOAD_SHIFT	3
652 #define CS42L42_HPOUT_LOAD_MASK		(1 << CS42L42_HPOUT_LOAD_SHIFT)
653 #define CS42L42_HPOUT_CLAMP_SHIFT	2
654 #define CS42L42_HPOUT_CLAMP_MASK	(1 << CS42L42_HPOUT_CLAMP_SHIFT)
655 #define CS42L42_DAC_HPF_EN_SHIFT	1
656 #define CS42L42_DAC_HPF_EN_MASK		(1 << CS42L42_DAC_HPF_EN_SHIFT)
657 #define CS42L42_DAC_MON_EN_SHIFT	0
658 #define CS42L42_DAC_MON_EN_MASK		(1 << CS42L42_DAC_MON_EN_SHIFT)
659 
660 /* Page 0x20 HP CTL Registers */
661 #define CS42L42_HP_CTL			(CS42L42_PAGE_20 + 0x01)
662 #define CS42L42_HP_ANA_BMUTE_SHIFT	3
663 #define CS42L42_HP_ANA_BMUTE_MASK	(1 << CS42L42_HP_ANA_BMUTE_SHIFT)
664 #define CS42L42_HP_ANA_AMUTE_SHIFT	2
665 #define CS42L42_HP_ANA_AMUTE_MASK	(1 << CS42L42_HP_ANA_AMUTE_SHIFT)
666 #define CS42L42_HP_FULL_SCALE_VOL_SHIFT	1
667 #define CS42L42_HP_FULL_SCALE_VOL_MASK	(1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT)
668 
669 /* Page 0x21 Class H Registers */
670 #define CS42L42_CLASSH_CTL		(CS42L42_PAGE_21 + 0x01)
671 
672 /* Page 0x23 Mixer Volume Registers */
673 #define CS42L42_MIXER_CHA_VOL		(CS42L42_PAGE_23 + 0x01)
674 #define CS42L42_MIXER_ADC_VOL		(CS42L42_PAGE_23 + 0x02)
675 
676 #define CS42L42_MIXER_CHB_VOL		(CS42L42_PAGE_23 + 0x03)
677 #define CS42L42_MIXER_CH_VOL_SHIFT	0
678 #define CS42L42_MIXER_CH_VOL_MASK	(0x3f << CS42L42_MIXER_CH_VOL_SHIFT)
679 
680 /* Page 0x24 EQ Registers */
681 #define CS42L42_EQ_COEF_IN0		(CS42L42_PAGE_24 + 0x01)
682 #define CS42L42_EQ_COEF_IN1		(CS42L42_PAGE_24 + 0x02)
683 #define CS42L42_EQ_COEF_IN2		(CS42L42_PAGE_24 + 0x03)
684 #define CS42L42_EQ_COEF_IN3		(CS42L42_PAGE_24 + 0x04)
685 #define CS42L42_EQ_COEF_RW		(CS42L42_PAGE_24 + 0x06)
686 #define CS42L42_EQ_COEF_OUT0		(CS42L42_PAGE_24 + 0x07)
687 #define CS42L42_EQ_COEF_OUT1		(CS42L42_PAGE_24 + 0x08)
688 #define CS42L42_EQ_COEF_OUT2		(CS42L42_PAGE_24 + 0x09)
689 #define CS42L42_EQ_COEF_OUT3		(CS42L42_PAGE_24 + 0x0A)
690 #define CS42L42_EQ_INIT_STAT		(CS42L42_PAGE_24 + 0x0B)
691 #define CS42L42_EQ_START_FILT		(CS42L42_PAGE_24 + 0x0C)
692 #define CS42L42_EQ_MUTE_CTL		(CS42L42_PAGE_24 + 0x0E)
693 
694 /* Page 0x25 Audio Port Registers */
695 #define CS42L42_SP_RX_CH_SEL		(CS42L42_PAGE_25 + 0x01)
696 #define CS42L42_SP_RX_CHB_SEL_SHIFT	2
697 #define CS42L42_SP_RX_CHB_SEL_MASK	(3 << CS42L42_SP_RX_CHB_SEL_SHIFT)
698 
699 #define CS42L42_SP_RX_ISOC_CTL		(CS42L42_PAGE_25 + 0x02)
700 #define CS42L42_SP_RX_RSYNC_SHIFT	6
701 #define CS42L42_SP_RX_RSYNC_MASK	(1 << CS42L42_SP_RX_RSYNC_SHIFT)
702 #define CS42L42_SP_RX_NSB_POS_SHIFT	3
703 #define CS42L42_SP_RX_NSB_POS_MASK	(7 << CS42L42_SP_RX_NSB_POS_SHIFT)
704 #define CS42L42_SP_RX_NFS_NSBB_SHIFT	2
705 #define CS42L42_SP_RX_NFS_NSBB_MASK	(1 << CS42L42_SP_RX_NFS_NSBB_SHIFT)
706 #define CS42L42_SP_RX_ISOC_MODE_SHIFT	0
707 #define CS42L42_SP_RX_ISOC_MODE_MASK	(3 << CS42L42_SP_RX_ISOC_MODE_SHIFT)
708 
709 #define CS42L42_SP_RX_FS		(CS42L42_PAGE_25 + 0x03)
710 #define CS42l42_SPDIF_CH_SEL		(CS42L42_PAGE_25 + 0x04)
711 #define CS42L42_SP_TX_ISOC_CTL		(CS42L42_PAGE_25 + 0x05)
712 #define CS42L42_SP_TX_FS		(CS42L42_PAGE_25 + 0x06)
713 #define CS42L42_SPDIF_SW_CTL1		(CS42L42_PAGE_25 + 0x07)
714 
715 /* Page 0x26 SRC Registers */
716 #define CS42L42_SRC_SDIN_FS		(CS42L42_PAGE_26 + 0x01)
717 #define CS42L42_SRC_SDIN_FS_SHIFT	0
718 #define CS42L42_SRC_SDIN_FS_MASK	(0x1f << CS42L42_SRC_SDIN_FS_SHIFT)
719 
720 #define CS42L42_SRC_SDOUT_FS		(CS42L42_PAGE_26 + 0x09)
721 
722 /* Page 0x28 S/PDIF Registers */
723 #define CS42L42_SPDIF_CTL1		(CS42L42_PAGE_28 + 0x01)
724 #define CS42L42_SPDIF_CTL2		(CS42L42_PAGE_28 + 0x02)
725 #define CS42L42_SPDIF_CTL3		(CS42L42_PAGE_28 + 0x03)
726 #define CS42L42_SPDIF_CTL4		(CS42L42_PAGE_28 + 0x04)
727 
728 /* Page 0x29 Serial Port TX Registers */
729 #define CS42L42_ASP_TX_SZ_EN		(CS42L42_PAGE_29 + 0x01)
730 #define CS42L42_ASP_TX_EN_SHIFT		0
731 #define CS42L42_ASP_TX_CH_EN		(CS42L42_PAGE_29 + 0x02)
732 #define CS42L42_ASP_TX0_CH2_SHIFT	1
733 #define CS42L42_ASP_TX0_CH1_SHIFT	0
734 
735 #define CS42L42_ASP_TX_CH_AP_RES	(CS42L42_PAGE_29 + 0x03)
736 #define CS42L42_ASP_TX_CH1_AP_SHIFT	7
737 #define CS42L42_ASP_TX_CH1_AP_MASK	(1 << CS42L42_ASP_TX_CH1_AP_SHIFT)
738 #define CS42L42_ASP_TX_CH2_AP_SHIFT	6
739 #define CS42L42_ASP_TX_CH2_AP_MASK	(1 << CS42L42_ASP_TX_CH2_AP_SHIFT)
740 #define CS42L42_ASP_TX_CH2_RES_SHIFT	2
741 #define CS42L42_ASP_TX_CH2_RES_MASK	(3 << CS42L42_ASP_TX_CH2_RES_SHIFT)
742 #define CS42L42_ASP_TX_CH1_RES_SHIFT	0
743 #define CS42L42_ASP_TX_CH1_RES_MASK	(3 << CS42L42_ASP_TX_CH1_RES_SHIFT)
744 #define CS42L42_ASP_TX_CH1_BIT_MSB	(CS42L42_PAGE_29 + 0x04)
745 #define CS42L42_ASP_TX_CH1_BIT_LSB	(CS42L42_PAGE_29 + 0x05)
746 #define CS42L42_ASP_TX_HIZ_DLY_CFG	(CS42L42_PAGE_29 + 0x06)
747 #define CS42L42_ASP_TX_CH2_BIT_MSB	(CS42L42_PAGE_29 + 0x0A)
748 #define CS42L42_ASP_TX_CH2_BIT_LSB	(CS42L42_PAGE_29 + 0x0B)
749 
750 /* Page 0x2A Serial Port RX Registers */
751 #define CS42L42_ASP_RX_DAI0_EN		(CS42L42_PAGE_2A + 0x01)
752 #define CS42L42_ASP_RX0_CH_EN_SHIFT	2
753 #define CS42L42_ASP_RX0_CH_EN_MASK	(0xf << CS42L42_ASP_RX0_CH_EN_SHIFT)
754 #define CS42L42_ASP_RX0_CH1_SHIFT	2
755 #define CS42L42_ASP_RX0_CH2_SHIFT	3
756 #define CS42L42_ASP_RX0_CH3_SHIFT	4
757 #define CS42L42_ASP_RX0_CH4_SHIFT	5
758 
759 #define CS42L42_ASP_RX_DAI0_CH1_AP_RES	(CS42L42_PAGE_2A + 0x02)
760 #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB	(CS42L42_PAGE_2A + 0x03)
761 #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB	(CS42L42_PAGE_2A + 0x04)
762 #define CS42L42_ASP_RX_DAI0_CH2_AP_RES	(CS42L42_PAGE_2A + 0x05)
763 #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB	(CS42L42_PAGE_2A + 0x06)
764 #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB	(CS42L42_PAGE_2A + 0x07)
765 #define CS42L42_ASP_RX_DAI0_CH3_AP_RES	(CS42L42_PAGE_2A + 0x08)
766 #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB	(CS42L42_PAGE_2A + 0x09)
767 #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB	(CS42L42_PAGE_2A + 0x0A)
768 #define CS42L42_ASP_RX_DAI0_CH4_AP_RES	(CS42L42_PAGE_2A + 0x0B)
769 #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB	(CS42L42_PAGE_2A + 0x0C)
770 #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB	(CS42L42_PAGE_2A + 0x0D)
771 #define CS42L42_ASP_RX_DAI1_CH1_AP_RES	(CS42L42_PAGE_2A + 0x0E)
772 #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB	(CS42L42_PAGE_2A + 0x0F)
773 #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB	(CS42L42_PAGE_2A + 0x10)
774 #define CS42L42_ASP_RX_DAI1_CH2_AP_RES	(CS42L42_PAGE_2A + 0x11)
775 #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB	(CS42L42_PAGE_2A + 0x12)
776 #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB	(CS42L42_PAGE_2A + 0x13)
777 
778 #define CS42L42_ASP_RX_CH_AP_SHIFT	6
779 #define CS42L42_ASP_RX_CH_AP_MASK	(1 << CS42L42_ASP_RX_CH_AP_SHIFT)
780 #define CS42L42_ASP_RX_CH_AP_LOW	0
781 #define CS42L42_ASP_RX_CH_AP_HI		1
782 #define CS42L42_ASP_RX_CH_RES_SHIFT	0
783 #define CS42L42_ASP_RX_CH_RES_MASK	(3 << CS42L42_ASP_RX_CH_RES_SHIFT)
784 #define CS42L42_ASP_RX_CH_RES_32	3
785 #define CS42L42_ASP_RX_CH_RES_16	1
786 #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT	0
787 #define CS42L42_ASP_RX_CH_BIT_ST_MASK	(0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT)
788 
789 /* Page 0x30 ID Registers */
790 #define CS42L42_SUB_REVID		(CS42L42_PAGE_30 + 0x14)
791 #define CS42L42_MAX_REGISTER		(CS42L42_PAGE_30 + 0x14)
792 
793 /* Defines for fracturing values spread across multiple registers */
794 #define CS42L42_FRAC0_VAL(val)	((val) & 0x0000ff)
795 #define CS42L42_FRAC1_VAL(val)	(((val) & 0x00ff00) >> 8)
796 #define CS42L42_FRAC2_VAL(val)	(((val) & 0xff0000) >> 16)
797 
798 #define CS42L42_NUM_SUPPLIES	5
799 #define CS42L42_BOOT_TIME_US	3000
800 #define CS42L42_PLL_DIVOUT_TIME_US	800
801 #define CS42L42_CLOCK_SWITCH_DELAY_US 150
802 #define CS42L42_PLL_LOCK_POLL_US	250
803 #define CS42L42_PLL_LOCK_TIMEOUT_US	1250
804 #define CS42L42_HP_ADC_EN_TIME_US	20000
805 #define CS42L42_PDN_DONE_POLL_US	1000
806 #define CS42L42_PDN_DONE_TIMEOUT_US	200000
807 #define CS42L42_PDN_DONE_TIME_MS	100
808 #define CS42L42_FILT_DISCHARGE_TIME_MS	46
809 
810 #endif /* __CS42L42_H */
811