1 #ifndef __ASM_SH_PROCESSOR_H 2 #define __ASM_SH_PROCESSOR_H 3 4 #include <asm/cpu-features.h> 5 #include <asm/segment.h> 6 #include <asm/cache.h> 7 8 #ifndef __ASSEMBLY__ 9 /* 10 * CPU type and hardware bug flags. Kept separately for each CPU. 11 * 12 * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry 13 * in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c 14 * for parsing the subtype in get_cpu_subtype(). 15 */ 16 enum cpu_type { 17 /* SH-2 types */ 18 CPU_SH7619, 19 20 /* SH-2A types */ 21 CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG, 22 23 /* SH-3 types */ 24 CPU_SH7705, CPU_SH7706, CPU_SH7707, 25 CPU_SH7708, CPU_SH7708S, CPU_SH7708R, 26 CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, 27 CPU_SH7720, CPU_SH7721, CPU_SH7729, 28 29 /* SH-4 types */ 30 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, 31 CPU_SH7760, CPU_SH4_202, CPU_SH4_501, 32 33 /* SH-4A types */ 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 35 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3, 36 37 /* SH4AL-DSP types */ 38 CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372, 39 40 /* SH-5 types */ 41 CPU_SH5_101, CPU_SH5_103, 42 43 /* Unknown subtype */ 44 CPU_SH_NONE 45 }; 46 47 enum cpu_family { 48 CPU_FAMILY_SH2, 49 CPU_FAMILY_SH2A, 50 CPU_FAMILY_SH3, 51 CPU_FAMILY_SH4, 52 CPU_FAMILY_SH4A, 53 CPU_FAMILY_SH4AL_DSP, 54 CPU_FAMILY_SH5, 55 CPU_FAMILY_UNKNOWN, 56 }; 57 58 /* 59 * TLB information structure 60 * 61 * Defined for both I and D tlb, per-processor. 62 */ 63 struct tlb_info { 64 unsigned long long next; 65 unsigned long long first; 66 unsigned long long last; 67 68 unsigned int entries; 69 unsigned int step; 70 71 unsigned long flags; 72 }; 73 74 struct sh_cpuinfo { 75 unsigned int type, family; 76 int cut_major, cut_minor; 77 unsigned long loops_per_jiffy; 78 unsigned long asid_cache; 79 80 struct cache_info icache; /* Primary I-cache */ 81 struct cache_info dcache; /* Primary D-cache */ 82 struct cache_info scache; /* Secondary cache */ 83 84 /* TLB info */ 85 struct tlb_info itlb; 86 struct tlb_info dtlb; 87 88 #ifdef CONFIG_SMP 89 struct task_struct *idle; 90 #endif 91 92 unsigned int phys_bits; 93 unsigned long flags; 94 } __attribute__ ((aligned(L1_CACHE_BYTES))); 95 96 extern struct sh_cpuinfo cpu_data[]; 97 #define boot_cpu_data cpu_data[0] 98 #define current_cpu_data cpu_data[smp_processor_id()] 99 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] 100 101 #define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory") 102 #define cpu_relax() barrier() 103 104 void default_idle(void); 105 void cpu_idle_wait(void); 106 void stop_this_cpu(void *); 107 108 /* Forward decl */ 109 struct seq_operations; 110 struct task_struct; 111 112 extern struct pt_regs fake_swapper_regs; 113 114 extern void cpu_init(void); 115 extern void cpu_probe(void); 116 117 /* arch/sh/kernel/process.c */ 118 extern unsigned int xstate_size; 119 extern void free_thread_xstate(struct task_struct *); 120 extern struct kmem_cache *task_xstate_cachep; 121 122 /* arch/sh/mm/alignment.c */ 123 extern int get_unalign_ctl(struct task_struct *, unsigned long addr); 124 extern int set_unalign_ctl(struct task_struct *, unsigned int val); 125 126 #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) 127 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 128 129 /* arch/sh/mm/init.c */ 130 extern unsigned int mem_init_done; 131 132 /* arch/sh/kernel/setup.c */ 133 const char *get_cpu_subtype(struct sh_cpuinfo *c); 134 extern const struct seq_operations cpuinfo_op; 135 136 /* thread_struct flags */ 137 #define SH_THREAD_UAC_NOPRINT (1 << 0) 138 #define SH_THREAD_UAC_SIGBUS (1 << 1) 139 #define SH_THREAD_UAC_MASK (SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS) 140 141 /* processor boot mode configuration */ 142 #define MODE_PIN0 (1 << 0) 143 #define MODE_PIN1 (1 << 1) 144 #define MODE_PIN2 (1 << 2) 145 #define MODE_PIN3 (1 << 3) 146 #define MODE_PIN4 (1 << 4) 147 #define MODE_PIN5 (1 << 5) 148 #define MODE_PIN6 (1 << 6) 149 #define MODE_PIN7 (1 << 7) 150 #define MODE_PIN8 (1 << 8) 151 #define MODE_PIN9 (1 << 9) 152 #define MODE_PIN10 (1 << 10) 153 #define MODE_PIN11 (1 << 11) 154 #define MODE_PIN12 (1 << 12) 155 #define MODE_PIN13 (1 << 13) 156 #define MODE_PIN14 (1 << 14) 157 #define MODE_PIN15 (1 << 15) 158 159 int generic_mode_pins(void); 160 int test_mode_pin(int pin); 161 162 #ifdef CONFIG_VSYSCALL 163 int vsyscall_init(void); 164 #else 165 #define vsyscall_init() do { } while (0) 166 #endif 167 168 /* 169 * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks. 170 */ 171 #ifdef CONFIG_CPU_SH2A 172 extern unsigned int instruction_size(unsigned int insn); 173 #elif defined(CONFIG_SUPERH32) 174 #define instruction_size(insn) (2) 175 #else 176 #define instruction_size(insn) (4) 177 #endif 178 179 #endif /* __ASSEMBLY__ */ 180 181 #ifdef CONFIG_SUPERH32 182 # include "processor_32.h" 183 #else 184 # include "processor_64.h" 185 #endif 186 187 #endif /* __ASM_SH_PROCESSOR_H */ 188