1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2020 HabanaLabs Ltd. 4 * All Rights Reserved. 5 */ 6 7 #ifndef __GAUDI2_ARC_COMMON_PACKETS_H__ 8 #define __GAUDI2_ARC_COMMON_PACKETS_H__ 9 10 /* 11 * CPU IDs for each ARC CPUs 12 */ 13 14 #define CPU_ID_SCHED_ARC0 0 /* FARM_ARC0 */ 15 #define CPU_ID_SCHED_ARC1 1 /* FARM_ARC1 */ 16 #define CPU_ID_SCHED_ARC2 2 /* FARM_ARC2 */ 17 #define CPU_ID_SCHED_ARC3 3 /* FARM_ARC3 */ 18 /* Dcore1 MME Engine ARC instance used as scheduler */ 19 #define CPU_ID_SCHED_ARC4 4 /* DCORE1_MME0 */ 20 /* Dcore3 MME Engine ARC instance used as scheduler */ 21 #define CPU_ID_SCHED_ARC5 5 /* DCORE3_MME0 */ 22 23 #define CPU_ID_TPC_QMAN_ARC0 6 /* DCORE0_TPC0 */ 24 #define CPU_ID_TPC_QMAN_ARC1 7 /* DCORE0_TPC1 */ 25 #define CPU_ID_TPC_QMAN_ARC2 8 /* DCORE0_TPC2 */ 26 #define CPU_ID_TPC_QMAN_ARC3 9 /* DCORE0_TPC3 */ 27 #define CPU_ID_TPC_QMAN_ARC4 10 /* DCORE0_TPC4 */ 28 #define CPU_ID_TPC_QMAN_ARC5 11 /* DCORE0_TPC5 */ 29 #define CPU_ID_TPC_QMAN_ARC6 12 /* DCORE1_TPC0 */ 30 #define CPU_ID_TPC_QMAN_ARC7 13 /* DCORE1_TPC1 */ 31 #define CPU_ID_TPC_QMAN_ARC8 14 /* DCORE1_TPC2 */ 32 #define CPU_ID_TPC_QMAN_ARC9 15 /* DCORE1_TPC3 */ 33 #define CPU_ID_TPC_QMAN_ARC10 16 /* DCORE1_TPC4 */ 34 #define CPU_ID_TPC_QMAN_ARC11 17 /* DCORE1_TPC5 */ 35 #define CPU_ID_TPC_QMAN_ARC12 18 /* DCORE2_TPC0 */ 36 #define CPU_ID_TPC_QMAN_ARC13 19 /* DCORE2_TPC1 */ 37 #define CPU_ID_TPC_QMAN_ARC14 20 /* DCORE2_TPC2 */ 38 #define CPU_ID_TPC_QMAN_ARC15 21 /* DCORE2_TPC3 */ 39 #define CPU_ID_TPC_QMAN_ARC16 22 /* DCORE2_TPC4 */ 40 #define CPU_ID_TPC_QMAN_ARC17 23 /* DCORE2_TPC5 */ 41 #define CPU_ID_TPC_QMAN_ARC18 24 /* DCORE3_TPC0 */ 42 #define CPU_ID_TPC_QMAN_ARC19 25 /* DCORE3_TPC1 */ 43 #define CPU_ID_TPC_QMAN_ARC20 26 /* DCORE3_TPC2 */ 44 #define CPU_ID_TPC_QMAN_ARC21 27 /* DCORE3_TPC3 */ 45 #define CPU_ID_TPC_QMAN_ARC22 28 /* DCORE3_TPC4 */ 46 #define CPU_ID_TPC_QMAN_ARC23 29 /* DCORE3_TPC5 */ 47 #define CPU_ID_TPC_QMAN_ARC24 30 /* DCORE0_TPC6 - Never present */ 48 49 #define CPU_ID_MME_QMAN_ARC0 31 /* DCORE0_MME0 */ 50 #define CPU_ID_MME_QMAN_ARC1 32 /* DCORE2_MME0 */ 51 52 #define CPU_ID_EDMA_QMAN_ARC0 33 /* DCORE0_EDMA0 */ 53 #define CPU_ID_EDMA_QMAN_ARC1 34 /* DCORE0_EDMA1 */ 54 #define CPU_ID_EDMA_QMAN_ARC2 35 /* DCORE1_EDMA0 */ 55 #define CPU_ID_EDMA_QMAN_ARC3 36 /* DCORE1_EDMA1 */ 56 #define CPU_ID_EDMA_QMAN_ARC4 37 /* DCORE2_EDMA0 */ 57 #define CPU_ID_EDMA_QMAN_ARC5 38 /* DCORE2_EDMA1 */ 58 #define CPU_ID_EDMA_QMAN_ARC6 39 /* DCORE3_EDMA0 */ 59 #define CPU_ID_EDMA_QMAN_ARC7 40 /* DCORE3_EDMA1 */ 60 61 #define CPU_ID_PDMA_QMAN_ARC0 41 /* DCORE0_PDMA0 */ 62 #define CPU_ID_PDMA_QMAN_ARC1 42 /* DCORE0_PDMA1 */ 63 64 #define CPU_ID_ROT_QMAN_ARC0 43 /* ROT0 */ 65 #define CPU_ID_ROT_QMAN_ARC1 44 /* ROT1 */ 66 67 #define CPU_ID_NIC_QMAN_ARC0 45 /* NIC0_0 */ 68 #define CPU_ID_NIC_QMAN_ARC1 46 /* NIC0_1 */ 69 #define CPU_ID_NIC_QMAN_ARC2 47 /* NIC1_0 */ 70 #define CPU_ID_NIC_QMAN_ARC3 48 /* NIC1_1 */ 71 #define CPU_ID_NIC_QMAN_ARC4 49 /* NIC2_0 */ 72 #define CPU_ID_NIC_QMAN_ARC5 50 /* NIC2_1 */ 73 #define CPU_ID_NIC_QMAN_ARC6 51 /* NIC3_0 */ 74 #define CPU_ID_NIC_QMAN_ARC7 52 /* NIC3_1 */ 75 #define CPU_ID_NIC_QMAN_ARC8 53 /* NIC4_0 */ 76 #define CPU_ID_NIC_QMAN_ARC9 54 /* NIC4_1 */ 77 #define CPU_ID_NIC_QMAN_ARC10 55 /* NIC5_0 */ 78 #define CPU_ID_NIC_QMAN_ARC11 56 /* NIC5_1 */ 79 #define CPU_ID_NIC_QMAN_ARC12 57 /* NIC6_0 */ 80 #define CPU_ID_NIC_QMAN_ARC13 58 /* NIC6_1 */ 81 #define CPU_ID_NIC_QMAN_ARC14 59 /* NIC7_0 */ 82 #define CPU_ID_NIC_QMAN_ARC15 60 /* NIC7_1 */ 83 #define CPU_ID_NIC_QMAN_ARC16 61 /* NIC8_0 */ 84 #define CPU_ID_NIC_QMAN_ARC17 62 /* NIC8_1 */ 85 #define CPU_ID_NIC_QMAN_ARC18 63 /* NIC9_0 */ 86 #define CPU_ID_NIC_QMAN_ARC19 64 /* NIC9_1 */ 87 #define CPU_ID_NIC_QMAN_ARC20 65 /* NIC10_0 */ 88 #define CPU_ID_NIC_QMAN_ARC21 66 /* NIC10_1 */ 89 #define CPU_ID_NIC_QMAN_ARC22 67 /* NIC11_0 */ 90 #define CPU_ID_NIC_QMAN_ARC23 68 /* NIC11_1 */ 91 92 #define CPU_ID_MAX 69 93 #define CPU_ID_SCHED_MAX 6 94 95 #define CPU_ID_ALL 0xFE 96 #define CPU_ID_INVALID 0xFF 97 98 enum arc_regions_t { 99 ARC_REGION0_UNSED = 0, 100 /* 101 * Extension registers 102 * None 103 */ 104 ARC_REGION1_SRAM = 1, 105 /* 106 * Extension registers 107 * AUX_SRAM_LSB_ADDR 108 * AUX_SRAM_MSB_ADDR 109 * ARC Address: 0x1000_0000 110 */ 111 ARC_REGION2_CFG = 2, 112 /* 113 * Extension registers 114 * AUX_CFG_LSB_ADDR 115 * AUX_CFG_MSB_ADDR 116 * ARC Address: 0x2000_0000 117 */ 118 ARC_REGION3_GENERAL = 3, 119 /* 120 * Extension registers 121 * AUX_GENERAL_PURPOSE_LSB_ADDR_0 122 * AUX_GENERAL_PURPOSE_MSB_ADDR_0 123 * ARC Address: 0x3000_0000 124 */ 125 ARC_REGION4_HBM0_FW = 4, 126 /* 127 * Extension registers 128 * AUX_HBM0_LSB_ADDR 129 * AUX_HBM0_MSB_ADDR 130 * AUX_HBM0_OFFSET 131 * ARC Address: 0x4000_0000 132 */ 133 ARC_REGION5_HBM1_GC_DATA = 5, 134 /* 135 * Extension registers 136 * AUX_HBM1_LSB_ADDR 137 * AUX_HBM1_MSB_ADDR 138 * AUX_HBM1_OFFSET 139 * ARC Address: 0x5000_0000 140 */ 141 ARC_REGION6_HBM2_GC_DATA = 6, 142 /* 143 * Extension registers 144 * AUX_HBM2_LSB_ADDR 145 * AUX_HBM2_MSB_ADDR 146 * AUX_HBM2_OFFSET 147 * ARC Address: 0x6000_0000 148 */ 149 ARC_REGION7_HBM3_GC_DATA = 7, 150 /* 151 * Extension registers 152 * AUX_HBM3_LSB_ADDR 153 * AUX_HBM3_MSB_ADDR 154 * AUX_HBM3_OFFSET 155 * ARC Address: 0x7000_0000 156 */ 157 ARC_REGION8_DCCM = 8, 158 /* 159 * Extension registers 160 * None 161 * ARC Address: 0x8000_0000 162 */ 163 ARC_REGION9_PCIE = 9, 164 /* 165 * Extension registers 166 * AUX_PCIE_LSB_ADDR 167 * AUX_PCIE_MSB_ADDR 168 * ARC Address: 0x9000_0000 169 */ 170 ARC_REGION10_GENERAL = 10, 171 /* 172 * Extension registers 173 * AUX_GENERAL_PURPOSE_LSB_ADDR_1 174 * AUX_GENERAL_PURPOSE_MSB_ADDR_1 175 * ARC Address: 0xA000_0000 176 */ 177 ARC_REGION11_GENERAL = 11, 178 /* 179 * Extension registers 180 * AUX_GENERAL_PURPOSE_LSB_ADDR_2 181 * AUX_GENERAL_PURPOSE_MSB_ADDR_2 182 * ARC Address: 0xB000_0000 183 */ 184 ARC_REGION12_GENERAL = 12, 185 /* 186 * Extension registers 187 * AUX_GENERAL_PURPOSE_LSB_ADDR_3 188 * AUX_GENERAL_PURPOSE_MSB_ADDR_3 189 * ARC Address: 0xC000_0000 190 */ 191 ARC_REGION13_GENERAL = 13, 192 /* 193 * Extension registers 194 * AUX_GENERAL_PURPOSE_LSB_ADDR_4 195 * AUX_GENERAL_PURPOSE_MSB_ADDR_4 196 * ARC Address: 0xD000_0000 197 */ 198 ARC_REGION14_GENERAL = 14, 199 /* 200 * Extension registers 201 * AUX_GENERAL_PURPOSE_LSB_ADDR_5 202 * AUX_GENERAL_PURPOSE_MSB_ADDR_5 203 * ARC Address: 0xE000_0000 204 */ 205 ARC_REGION15_LBU = 15 206 /* 207 * Extension registers 208 * None 209 * ARC Address: 0xF000_0000 210 */ 211 }; 212 213 #endif /* __GAUDI2_ARC_COMMON_PACKETS_H__ */ 214