1 /* 2 * include/asm-ppc/cputable.h 3 * 4 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #ifndef __ASM_PPC_CPUTABLE_H 13 #define __ASM_PPC_CPUTABLE_H 14 15 /* Exposed to userland CPU features */ 16 #define PPC_FEATURE_32 0x80000000 17 #define PPC_FEATURE_64 0x40000000 18 #define PPC_FEATURE_601_INSTR 0x20000000 19 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000 20 #define PPC_FEATURE_HAS_FPU 0x08000000 21 #define PPC_FEATURE_HAS_MMU 0x04000000 22 #define PPC_FEATURE_HAS_4xxMAC 0x02000000 23 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000 24 25 #ifdef __KERNEL__ 26 27 #ifndef __ASSEMBLY__ 28 29 /* This structure can grow, it's real size is used by head.S code 30 * via the mkdefs mecanism. 31 */ 32 struct cpu_spec; 33 34 typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 35 36 struct cpu_spec { 37 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 38 unsigned int pvr_mask; 39 unsigned int pvr_value; 40 41 char *cpu_name; 42 unsigned int cpu_features; /* Kernel features */ 43 unsigned int cpu_user_features; /* Userland features */ 44 45 /* cache line sizes */ 46 unsigned int icache_bsize; 47 unsigned int dcache_bsize; 48 49 /* this is called to initialize various CPU bits like L1 cache, 50 * BHT, SPD, etc... from head.S before branching to identify_machine 51 */ 52 cpu_setup_t cpu_setup; 53 }; 54 55 extern struct cpu_spec cpu_specs[]; 56 extern struct cpu_spec *cur_cpu_spec[]; 57 58 #endif /* __ASSEMBLY__ */ 59 60 /* CPU kernel features */ 61 #define CPU_FTR_SPLIT_ID_CACHE 0x00000001 62 #define CPU_FTR_L2CR 0x00000002 63 #define CPU_FTR_SPEC7450 0x00000004 64 #define CPU_FTR_ALTIVEC 0x00000008 65 #define CPU_FTR_TAU 0x00000010 66 #define CPU_FTR_CAN_DOZE 0x00000020 67 #define CPU_FTR_USE_TB 0x00000040 68 #define CPU_FTR_604_PERF_MON 0x00000080 69 #define CPU_FTR_601 0x00000100 70 #define CPU_FTR_HPTE_TABLE 0x00000200 71 #define CPU_FTR_CAN_NAP 0x00000400 72 #define CPU_FTR_L3CR 0x00000800 73 #define CPU_FTR_L3_DISABLE_NAP 0x00001000 74 #define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000 75 #define CPU_FTR_750FX 0x00004000 76 #define CPU_FTR_NO_DPM 0x00008000 77 #define CPU_FTR_HAS_HIGH_BATS 0x00010000 78 #define CPU_FTR_NEED_COHERENT 0x00020000 79 80 #ifdef __ASSEMBLY__ 81 82 #define BEGIN_FTR_SECTION 98: 83 84 #define END_FTR_SECTION(msk, val) \ 85 99: \ 86 .section __ftr_fixup,"a"; \ 87 .align 2; \ 88 .long msk; \ 89 .long val; \ 90 .long 98b; \ 91 .long 99b; \ 92 .previous 93 94 #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk)) 95 #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0) 96 97 #endif /* __ASSEMBLY__ */ 98 99 #endif /* __KERNEL__ */ 100 #endif /* __ASM_PPC_CPUTABLE_H */ 101 102