1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2020-2021 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef CPUCP_IF_H 9 #define CPUCP_IF_H 10 11 #include <linux/types.h> 12 #include <linux/if_ether.h> 13 14 #include "hl_boot_if.h" 15 16 #define NUM_HBM_PSEUDO_CH 2 17 #define NUM_HBM_CH_PER_DEV 8 18 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0 19 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001 20 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1 21 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002 22 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2 23 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004 24 #define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3 25 #define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008 26 #define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4 27 #define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010 28 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5 29 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020 30 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6 31 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0 32 33 #define PLL_MAP_MAX_BITS 128 34 #define PLL_MAP_LEN (PLL_MAP_MAX_BITS / 8) 35 36 /* 37 * info of the pkt queue pointers in the first async occurrence 38 */ 39 struct cpucp_pkt_sync_err { 40 __le32 pi; 41 __le32 ci; 42 }; 43 44 struct hl_eq_hbm_ecc_data { 45 /* SERR counter */ 46 __le32 sec_cnt; 47 /* DERR counter */ 48 __le32 dec_cnt; 49 /* Supplemental Information according to the mask bits */ 50 __le32 hbm_ecc_info; 51 /* Address in hbm where the ecc happened */ 52 __le32 first_addr; 53 /* SERR continuous address counter */ 54 __le32 sec_cont_cnt; 55 __le32 pad; 56 }; 57 58 /* 59 * EVENT QUEUE 60 */ 61 62 struct hl_eq_header { 63 __le32 reserved; 64 __le32 ctl; 65 }; 66 67 struct hl_eq_ecc_data { 68 __le64 ecc_address; 69 __le64 ecc_syndrom; 70 __u8 memory_wrapper_idx; 71 __u8 pad[7]; 72 }; 73 74 enum hl_sm_sei_cause { 75 SM_SEI_SO_OVERFLOW, 76 SM_SEI_LBW_4B_UNALIGNED, 77 SM_SEI_AXI_RESPONSE_ERR 78 }; 79 80 struct hl_eq_sm_sei_data { 81 __le32 sei_log; 82 /* enum hl_sm_sei_cause */ 83 __u8 sei_cause; 84 __u8 pad[3]; 85 }; 86 87 enum hl_fw_alive_severity { 88 FW_ALIVE_SEVERITY_MINOR, 89 FW_ALIVE_SEVERITY_CRITICAL 90 }; 91 92 struct hl_eq_fw_alive { 93 __le64 uptime_seconds; 94 __le32 process_id; 95 __le32 thread_id; 96 /* enum hl_fw_alive_severity */ 97 __u8 severity; 98 __u8 pad[7]; 99 }; 100 101 enum hl_pcie_addr_dec_cause { 102 PCIE_ADDR_DEC_HBW_ERR_RESP, 103 PCIE_ADDR_DEC_LBW_ERR_RESP, 104 PCIE_ADDR_DEC_TLP_BLOCKED_BY_RR 105 }; 106 107 struct hl_eq_pcie_addr_dec_data { 108 /* enum hl_pcie_addr_dec_cause */ 109 __u8 addr_dec_cause; 110 __u8 pad[7]; 111 }; 112 113 struct hl_eq_entry { 114 struct hl_eq_header hdr; 115 union { 116 struct hl_eq_ecc_data ecc_data; 117 struct hl_eq_hbm_ecc_data hbm_ecc_data; 118 struct hl_eq_sm_sei_data sm_sei_data; 119 struct cpucp_pkt_sync_err pkt_sync_err; 120 struct hl_eq_fw_alive fw_alive; 121 struct hl_eq_pcie_addr_dec_data pcie_addr_dec_data; 122 __le64 data[7]; 123 }; 124 }; 125 126 #define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry) 127 128 #define EQ_CTL_READY_SHIFT 31 129 #define EQ_CTL_READY_MASK 0x80000000 130 131 #define EQ_CTL_EVENT_TYPE_SHIFT 16 132 #define EQ_CTL_EVENT_TYPE_MASK 0x0FFF0000 133 134 #define EQ_CTL_INDEX_SHIFT 0 135 #define EQ_CTL_INDEX_MASK 0x0000FFFF 136 137 enum pq_init_status { 138 PQ_INIT_STATUS_NA = 0, 139 PQ_INIT_STATUS_READY_FOR_CP, 140 PQ_INIT_STATUS_READY_FOR_HOST, 141 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI, 142 PQ_INIT_STATUS_LEN_NOT_POWER_OF_TWO_ERR, 143 PQ_INIT_STATUS_ILLEGAL_Q_ADDR_ERR 144 }; 145 146 /* 147 * CpuCP Primary Queue Packets 148 * 149 * During normal operation, the host's kernel driver needs to send various 150 * messages to CpuCP, usually either to SET some value into a H/W periphery or 151 * to GET the current value of some H/W periphery. For example, SET the 152 * frequency of MME/TPC and GET the value of the thermal sensor. 153 * 154 * These messages can be initiated either by the User application or by the 155 * host's driver itself, e.g. power management code. In either case, the 156 * communication from the host's driver to CpuCP will *always* be in 157 * synchronous mode, meaning that the host will send a single message and poll 158 * until the message was acknowledged and the results are ready (if results are 159 * needed). 160 * 161 * This means that only a single message can be sent at a time and the host's 162 * driver must wait for its result before sending the next message. Having said 163 * that, because these are control messages which are sent in a relatively low 164 * frequency, this limitation seems acceptable. It's important to note that 165 * in case of multiple devices, messages to different devices *can* be sent 166 * at the same time. 167 * 168 * The message, inputs/outputs (if relevant) and fence object will be located 169 * on the device DDR at an address that will be determined by the host's driver. 170 * During device initialization phase, the host will pass to CpuCP that address. 171 * Most of the message types will contain inputs/outputs inside the message 172 * itself. The common part of each message will contain the opcode of the 173 * message (its type) and a field representing a fence object. 174 * 175 * When the host's driver wishes to send a message to CPU CP, it will write the 176 * message contents to the device DDR, clear the fence object and then write to 177 * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU. 178 * 179 * Upon receiving the interrupt (#121), CpuCP will read the message from the 180 * DDR. In case the message is a SET operation, CpuCP will first perform the 181 * operation and then write to the fence object on the device DDR. In case the 182 * message is a GET operation, CpuCP will first fill the results section on the 183 * device DDR and then write to the fence object. If an error occurred, CpuCP 184 * will fill the rc field with the right error code. 185 * 186 * In the meantime, the host's driver will poll on the fence object. Once the 187 * host sees that the fence object is signaled, it will read the results from 188 * the device DDR (if relevant) and resume the code execution in the host's 189 * driver. 190 * 191 * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 192 * so the value being put by the host's driver matches the value read by CpuCP 193 * 194 * Non-QMAN packets should be limited to values 1 through (2^8 - 1) 195 * 196 * Detailed description: 197 * 198 * CPUCP_PACKET_DISABLE_PCI_ACCESS - 199 * After receiving this packet the embedded CPU must NOT issue PCI 200 * transactions (read/write) towards the Host CPU. This also include 201 * sending MSI-X interrupts. 202 * This packet is usually sent before the device is moved to D3Hot state. 203 * 204 * CPUCP_PACKET_ENABLE_PCI_ACCESS - 205 * After receiving this packet the embedded CPU is allowed to issue PCI 206 * transactions towards the Host CPU, including sending MSI-X interrupts. 207 * This packet is usually send after the device is moved to D0 state. 208 * 209 * CPUCP_PACKET_TEMPERATURE_GET - 210 * Fetch the current temperature / Max / Max Hyst / Critical / 211 * Critical Hyst of a specified thermal sensor. The packet's 212 * arguments specify the desired sensor and the field to get. 213 * 214 * CPUCP_PACKET_VOLTAGE_GET - 215 * Fetch the voltage / Max / Min of a specified sensor. The packet's 216 * arguments specify the sensor and type. 217 * 218 * CPUCP_PACKET_CURRENT_GET - 219 * Fetch the current / Max / Min of a specified sensor. The packet's 220 * arguments specify the sensor and type. 221 * 222 * CPUCP_PACKET_FAN_SPEED_GET - 223 * Fetch the speed / Max / Min of a specified fan. The packet's 224 * arguments specify the sensor and type. 225 * 226 * CPUCP_PACKET_PWM_GET - 227 * Fetch the pwm value / mode of a specified pwm. The packet's 228 * arguments specify the sensor and type. 229 * 230 * CPUCP_PACKET_PWM_SET - 231 * Set the pwm value / mode of a specified pwm. The packet's 232 * arguments specify the sensor, type and value. 233 * 234 * CPUCP_PACKET_FREQUENCY_SET - 235 * Set the frequency of a specified PLL. The packet's arguments specify 236 * the PLL and the desired frequency. The actual frequency in the device 237 * might differ from the requested frequency. 238 * 239 * CPUCP_PACKET_FREQUENCY_GET - 240 * Fetch the frequency of a specified PLL. The packet's arguments specify 241 * the PLL. 242 * 243 * CPUCP_PACKET_LED_SET - 244 * Set the state of a specified led. The packet's arguments 245 * specify the led and the desired state. 246 * 247 * CPUCP_PACKET_I2C_WR - 248 * Write 32-bit value to I2C device. The packet's arguments specify the 249 * I2C bus, address and value. 250 * 251 * CPUCP_PACKET_I2C_RD - 252 * Read 32-bit value from I2C device. The packet's arguments specify the 253 * I2C bus and address. 254 * 255 * CPUCP_PACKET_INFO_GET - 256 * Fetch information from the device as specified in the packet's 257 * structure. The host's driver passes the max size it allows the CpuCP to 258 * write to the structure, to prevent data corruption in case of 259 * mismatched driver/FW versions. 260 * 261 * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed 262 * 263 * CPUCP_PACKET_UNMASK_RAZWI_IRQ - 264 * Unmask the given IRQ. The IRQ number is specified in the value field. 265 * The packet is sent after receiving an interrupt and printing its 266 * relevant information. 267 * 268 * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - 269 * Unmask the given IRQs. The IRQs numbers are specified in an array right 270 * after the cpucp_packet structure, where its first element is the array 271 * length. The packet is sent after a soft reset was done in order to 272 * handle any interrupts that were sent during the reset process. 273 * 274 * CPUCP_PACKET_TEST - 275 * Test packet for CpuCP connectivity. The CPU will put the fence value 276 * in the result field. 277 * 278 * CPUCP_PACKET_FREQUENCY_CURR_GET - 279 * Fetch the current frequency of a specified PLL. The packet's arguments 280 * specify the PLL. 281 * 282 * CPUCP_PACKET_MAX_POWER_GET - 283 * Fetch the maximal power of the device. 284 * 285 * CPUCP_PACKET_MAX_POWER_SET - 286 * Set the maximal power of the device. The packet's arguments specify 287 * the power. 288 * 289 * CPUCP_PACKET_EEPROM_DATA_GET - 290 * Get EEPROM data from the CpuCP kernel. The buffer is specified in the 291 * addr field. The CPU will put the returned data size in the result 292 * field. In addition, the host's driver passes the max size it allows the 293 * CpuCP to write to the structure, to prevent data corruption in case of 294 * mismatched driver/FW versions. 295 * 296 * CPUCP_PACKET_NIC_INFO_GET - 297 * Fetch information from the device regarding the NIC. the host's driver 298 * passes the max size it allows the CpuCP to write to the structure, to 299 * prevent data corruption in case of mismatched driver/FW versions. 300 * 301 * CPUCP_PACKET_TEMPERATURE_SET - 302 * Set the value of the offset property of a specified thermal sensor. 303 * The packet's arguments specify the desired sensor and the field to 304 * set. 305 * 306 * CPUCP_PACKET_VOLTAGE_SET - 307 * Trigger the reset_history property of a specified voltage sensor. 308 * The packet's arguments specify the desired sensor and the field to 309 * set. 310 * 311 * CPUCP_PACKET_CURRENT_SET - 312 * Trigger the reset_history property of a specified current sensor. 313 * The packet's arguments specify the desired sensor and the field to 314 * set. 315 * 316 * CPUCP_PACKET_PCIE_THROUGHPUT_GET - 317 * Get throughput of PCIe. 318 * The packet's arguments specify the transaction direction (TX/RX). 319 * The window measurement is 10[msec], and the return value is in KB/sec. 320 * 321 * CPUCP_PACKET_PCIE_REPLAY_CNT_GET 322 * Replay count measures number of "replay" events, which is basicly 323 * number of retries done by PCIe. 324 * 325 * CPUCP_PACKET_TOTAL_ENERGY_GET - 326 * Total Energy is measurement of energy from the time FW Linux 327 * is loaded. It is calculated by multiplying the average power 328 * by time (passed from armcp start). The units are in MilliJouls. 329 * 330 * CPUCP_PACKET_PLL_INFO_GET - 331 * Fetch frequencies of PLL from the required PLL IP. 332 * The packet's arguments specify the device PLL type 333 * Pll type is the PLL from device pll_index enum. 334 * The result is composed of 4 outputs, each is 16-bit 335 * frequency in MHz. 336 * 337 * CPUCP_PACKET_POWER_GET - 338 * Fetch the present power consumption of the device (Current * Voltage). 339 * 340 * CPUCP_PACKET_NIC_PFC_SET - 341 * Enable/Disable the NIC PFC feature. The packet's arguments specify the 342 * NIC port, relevant lanes to configure and one bit indication for 343 * enable/disable. 344 * 345 * CPUCP_PACKET_NIC_FAULT_GET - 346 * Fetch the current indication for local/remote faults from the NIC MAC. 347 * The result is 32-bit value of the relevant register. 348 * 349 * CPUCP_PACKET_NIC_LPBK_SET - 350 * Enable/Disable the MAC loopback feature. The packet's arguments specify 351 * the NIC port, relevant lanes to configure and one bit indication for 352 * enable/disable. 353 * 354 * CPUCP_PACKET_NIC_MAC_INIT - 355 * Configure the NIC MAC channels. The packet's arguments specify the 356 * NIC port and the speed. 357 * 358 * CPUCP_PACKET_MSI_INFO_SET - 359 * set the index number for each supported msi type going from 360 * host to device 361 * 362 * CPUCP_PACKET_NIC_XPCS91_REGS_GET - 363 * Fetch the un/correctable counters values from the NIC MAC. 364 * 365 * CPUCP_PACKET_NIC_STAT_REGS_GET - 366 * Fetch various NIC MAC counters from the NIC STAT. 367 * 368 * CPUCP_PACKET_NIC_STAT_REGS_CLR - 369 * Clear the various NIC MAC counters in the NIC STAT. 370 * 371 * CPUCP_PACKET_NIC_STAT_REGS_ALL_GET - 372 * Fetch all NIC MAC counters from the NIC STAT. 373 * 374 * CPUCP_PACKET_IS_IDLE_CHECK - 375 * Check if the device is IDLE in regard to the DMA/compute engines 376 * and QMANs. The f/w will return a bitmask where each bit represents 377 * a different engine or QMAN according to enum cpucp_idle_mask. 378 * The bit will be 1 if the engine is NOT idle. 379 * 380 * CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET - 381 * Fetch all HBM replaced-rows and prending to be replaced rows data. 382 * 383 * CPUCP_PACKET_HBM_PENDING_ROWS_STATUS - 384 * Fetch status of HBM rows pending replacement and need a reboot to 385 * be replaced. 386 * 387 * CPUCP_PACKET_POWER_SET - 388 * Resets power history of device to 0 389 * 390 * CPUCP_PACKET_ENGINE_CORE_ASID_SET - 391 * Packet to perform engine core ASID configuration 392 * 393 * CPUCP_PACKET_MONITOR_DUMP_GET - 394 * Get monitors registers dump from the CpuCP kernel. 395 * The CPU will put the registers dump in the a buffer allocated by the driver 396 * which address is passed via the CpuCp packet. In addition, the host's driver 397 * passes the max size it allows the CpuCP to write to the structure, to prevent 398 * data corruption in case of mismatched driver/FW versions. 399 * Relevant only to Gaudi. 400 */ 401 402 enum cpucp_packet_id { 403 CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ 404 CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ 405 CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */ 406 CPUCP_PACKET_VOLTAGE_GET, /* sysfs */ 407 CPUCP_PACKET_CURRENT_GET, /* sysfs */ 408 CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */ 409 CPUCP_PACKET_PWM_GET, /* sysfs */ 410 CPUCP_PACKET_PWM_SET, /* sysfs */ 411 CPUCP_PACKET_FREQUENCY_SET, /* sysfs */ 412 CPUCP_PACKET_FREQUENCY_GET, /* sysfs */ 413 CPUCP_PACKET_LED_SET, /* debugfs */ 414 CPUCP_PACKET_I2C_WR, /* debugfs */ 415 CPUCP_PACKET_I2C_RD, /* debugfs */ 416 CPUCP_PACKET_INFO_GET, /* IOCTL */ 417 CPUCP_PACKET_FLASH_PROGRAM_REMOVED, 418 CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ 419 CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ 420 CPUCP_PACKET_TEST, /* internal */ 421 CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ 422 CPUCP_PACKET_MAX_POWER_GET, /* sysfs */ 423 CPUCP_PACKET_MAX_POWER_SET, /* sysfs */ 424 CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */ 425 CPUCP_PACKET_NIC_INFO_GET, /* internal */ 426 CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */ 427 CPUCP_PACKET_VOLTAGE_SET, /* sysfs */ 428 CPUCP_PACKET_CURRENT_SET, /* sysfs */ 429 CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ 430 CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ 431 CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ 432 CPUCP_PACKET_PLL_INFO_GET, /* internal */ 433 CPUCP_PACKET_NIC_STATUS, /* internal */ 434 CPUCP_PACKET_POWER_GET, /* internal */ 435 CPUCP_PACKET_NIC_PFC_SET, /* internal */ 436 CPUCP_PACKET_NIC_FAULT_GET, /* internal */ 437 CPUCP_PACKET_NIC_LPBK_SET, /* internal */ 438 CPUCP_PACKET_NIC_MAC_CFG, /* internal */ 439 CPUCP_PACKET_MSI_INFO_SET, /* internal */ 440 CPUCP_PACKET_NIC_XPCS91_REGS_GET, /* internal */ 441 CPUCP_PACKET_NIC_STAT_REGS_GET, /* internal */ 442 CPUCP_PACKET_NIC_STAT_REGS_CLR, /* internal */ 443 CPUCP_PACKET_NIC_STAT_REGS_ALL_GET, /* internal */ 444 CPUCP_PACKET_IS_IDLE_CHECK, /* internal */ 445 CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET,/* internal */ 446 CPUCP_PACKET_HBM_PENDING_ROWS_STATUS, /* internal */ 447 CPUCP_PACKET_POWER_SET, /* internal */ 448 CPUCP_PACKET_RESERVED, /* not used */ 449 CPUCP_PACKET_ENGINE_CORE_ASID_SET, /* internal */ 450 CPUCP_PACKET_RESERVED2, /* not used */ 451 CPUCP_PACKET_RESERVED3, /* not used */ 452 CPUCP_PACKET_RESERVED4, /* not used */ 453 CPUCP_PACKET_RESERVED5, /* not used */ 454 CPUCP_PACKET_MONITOR_DUMP_GET, /* debugfs */ 455 }; 456 457 #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 458 459 #define CPUCP_PKT_CTL_RC_SHIFT 12 460 #define CPUCP_PKT_CTL_RC_MASK 0x0000F000 461 462 #define CPUCP_PKT_CTL_OPCODE_SHIFT 16 463 #define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 464 465 #define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0 466 #define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull 467 #define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16 468 #define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull 469 #define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32 470 #define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull 471 #define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48 472 #define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull 473 474 #define CPUCP_PKT_VAL_PFC_IN1_SHIFT 0 475 #define CPUCP_PKT_VAL_PFC_IN1_MASK 0x0000000000000001ull 476 #define CPUCP_PKT_VAL_PFC_IN2_SHIFT 1 477 #define CPUCP_PKT_VAL_PFC_IN2_MASK 0x000000000000001Eull 478 479 #define CPUCP_PKT_VAL_LPBK_IN1_SHIFT 0 480 #define CPUCP_PKT_VAL_LPBK_IN1_MASK 0x0000000000000001ull 481 #define CPUCP_PKT_VAL_LPBK_IN2_SHIFT 1 482 #define CPUCP_PKT_VAL_LPBK_IN2_MASK 0x000000000000001Eull 483 484 #define CPUCP_PKT_VAL_MAC_CNT_IN1_SHIFT 0 485 #define CPUCP_PKT_VAL_MAC_CNT_IN1_MASK 0x0000000000000001ull 486 #define CPUCP_PKT_VAL_MAC_CNT_IN2_SHIFT 1 487 #define CPUCP_PKT_VAL_MAC_CNT_IN2_MASK 0x00000000FFFFFFFEull 488 489 /* heartbeat status bits */ 490 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT 0 491 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK 0x00000001 492 493 struct cpucp_packet { 494 union { 495 __le64 value; /* For SET packets */ 496 __le64 result; /* For GET packets */ 497 __le64 addr; /* For PQ */ 498 }; 499 500 __le32 ctl; 501 502 __le32 fence; /* Signal to host that message is completed */ 503 504 union { 505 struct {/* For temperature/current/voltage/fan/pwm get/set */ 506 __le16 sensor_index; 507 __le16 type; 508 }; 509 510 struct { /* For I2C read/write */ 511 __u8 i2c_bus; 512 __u8 i2c_addr; 513 __u8 i2c_reg; 514 /* 515 * In legacy implemetations, i2c_len was not present, 516 * was unused and just added as pad. 517 * So if i2c_len is 0, it is treated as legacy 518 * and r/w 1 Byte, else if i2c_len is specified, 519 * its treated as new multibyte r/w support. 520 */ 521 __u8 i2c_len; 522 }; 523 524 struct {/* For PLL info fetch */ 525 __le16 pll_type; 526 /* TODO pll_reg is kept temporary before removal */ 527 __le16 pll_reg; 528 }; 529 530 /* For any general request */ 531 __le32 index; 532 533 /* For frequency get/set */ 534 __le32 pll_index; 535 536 /* For led set */ 537 __le32 led_index; 538 539 /* For get CpuCP info/EEPROM data/NIC info */ 540 __le32 data_max_size; 541 542 /* 543 * For any general status bitmask. Shall be used whenever the 544 * result cannot be used to hold general purpose data. 545 */ 546 __le32 status_mask; 547 }; 548 549 /* For NIC requests */ 550 __le32 port_index; 551 }; 552 553 struct cpucp_unmask_irq_arr_packet { 554 struct cpucp_packet cpucp_pkt; 555 __le32 length; 556 __le32 irqs[]; 557 }; 558 559 struct cpucp_nic_status_packet { 560 struct cpucp_packet cpucp_pkt; 561 __le32 length; 562 __le32 data[]; 563 }; 564 565 struct cpucp_array_data_packet { 566 struct cpucp_packet cpucp_pkt; 567 __le32 length; 568 __le32 data[]; 569 }; 570 571 enum cpucp_led_index { 572 CPUCP_LED0_INDEX = 0, 573 CPUCP_LED1_INDEX, 574 CPUCP_LED2_INDEX 575 }; 576 577 enum cpucp_packet_rc { 578 cpucp_packet_success, 579 cpucp_packet_invalid, 580 cpucp_packet_fault 581 }; 582 583 /* 584 * cpucp_temp_type should adhere to hwmon_temp_attributes 585 * defined in Linux kernel hwmon.h file 586 */ 587 enum cpucp_temp_type { 588 cpucp_temp_input, 589 cpucp_temp_min = 4, 590 cpucp_temp_min_hyst, 591 cpucp_temp_max = 6, 592 cpucp_temp_max_hyst, 593 cpucp_temp_crit, 594 cpucp_temp_crit_hyst, 595 cpucp_temp_offset = 19, 596 cpucp_temp_lowest = 21, 597 cpucp_temp_highest = 22, 598 cpucp_temp_reset_history = 23, 599 cpucp_temp_warn = 24, 600 cpucp_temp_max_crit = 25, 601 cpucp_temp_max_warn = 26, 602 }; 603 604 enum cpucp_in_attributes { 605 cpucp_in_input, 606 cpucp_in_min, 607 cpucp_in_max, 608 cpucp_in_lowest = 6, 609 cpucp_in_highest = 7, 610 cpucp_in_reset_history 611 }; 612 613 enum cpucp_curr_attributes { 614 cpucp_curr_input, 615 cpucp_curr_min, 616 cpucp_curr_max, 617 cpucp_curr_lowest = 6, 618 cpucp_curr_highest = 7, 619 cpucp_curr_reset_history 620 }; 621 622 enum cpucp_fan_attributes { 623 cpucp_fan_input, 624 cpucp_fan_min = 2, 625 cpucp_fan_max 626 }; 627 628 enum cpucp_pwm_attributes { 629 cpucp_pwm_input, 630 cpucp_pwm_enable 631 }; 632 633 enum cpucp_pcie_throughput_attributes { 634 cpucp_pcie_throughput_tx, 635 cpucp_pcie_throughput_rx 636 }; 637 638 /* TODO temporary kept before removal */ 639 enum cpucp_pll_reg_attributes { 640 cpucp_pll_nr_reg, 641 cpucp_pll_nf_reg, 642 cpucp_pll_od_reg, 643 cpucp_pll_div_factor_reg, 644 cpucp_pll_div_sel_reg 645 }; 646 647 /* TODO temporary kept before removal */ 648 enum cpucp_pll_type_attributes { 649 cpucp_pll_cpu, 650 cpucp_pll_pci, 651 }; 652 653 /* 654 * cpucp_power_type aligns with hwmon_power_attributes 655 * defined in Linux kernel hwmon.h file 656 */ 657 enum cpucp_power_type { 658 CPUCP_POWER_INPUT = 8, 659 CPUCP_POWER_INPUT_HIGHEST = 9, 660 CPUCP_POWER_RESET_INPUT_HISTORY = 11 661 }; 662 663 /* 664 * MSI type enumeration table for all ASICs and future SW versions. 665 * For future ASIC-LKD compatibility, we can only add new enumerations. 666 * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES). 667 * Changing the order of entries or removing entries is not allowed. 668 */ 669 enum cpucp_msi_type { 670 CPUCP_EVENT_QUEUE_MSI_TYPE, 671 CPUCP_NIC_PORT1_MSI_TYPE, 672 CPUCP_NIC_PORT3_MSI_TYPE, 673 CPUCP_NIC_PORT5_MSI_TYPE, 674 CPUCP_NIC_PORT7_MSI_TYPE, 675 CPUCP_NIC_PORT9_MSI_TYPE, 676 CPUCP_NUM_OF_MSI_TYPES 677 }; 678 679 /* 680 * PLL enumeration table used for all ASICs and future SW versions. 681 * For future ASIC-LKD compatibility, we can only add new enumerations. 682 * at the end of the table. 683 * Changing the order of entries or removing entries is not allowed. 684 */ 685 enum pll_index { 686 CPU_PLL = 0, 687 PCI_PLL = 1, 688 NIC_PLL = 2, 689 DMA_PLL = 3, 690 MESH_PLL = 4, 691 MME_PLL = 5, 692 TPC_PLL = 6, 693 IF_PLL = 7, 694 SRAM_PLL = 8, 695 NS_PLL = 9, 696 HBM_PLL = 10, 697 MSS_PLL = 11, 698 DDR_PLL = 12, 699 VID_PLL = 13, 700 BANK_PLL = 14, 701 MMU_PLL = 15, 702 IC_PLL = 16, 703 MC_PLL = 17, 704 EMMC_PLL = 18, 705 PLL_MAX 706 }; 707 708 enum rl_index { 709 TPC_RL = 0, 710 MME_RL, 711 EDMA_RL, 712 }; 713 714 enum pvt_index { 715 PVT_SW, 716 PVT_SE, 717 PVT_NW, 718 PVT_NE 719 }; 720 721 /* Event Queue Packets */ 722 723 struct eq_generic_event { 724 __le64 data[7]; 725 }; 726 727 /* 728 * CpuCP info 729 */ 730 731 #define CARD_NAME_MAX_LEN 16 732 #define CPUCP_MAX_SENSORS 128 733 #define CPUCP_MAX_NICS 128 734 #define CPUCP_LANES_PER_NIC 4 735 #define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024 736 #define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC) 737 #define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64) 738 #define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64) 739 #define CPUCP_HBM_ROW_REPLACE_MAX 32 740 741 struct cpucp_sensor { 742 __le32 type; 743 __le32 flags; 744 }; 745 746 /** 747 * struct cpucp_card_types - ASIC card type. 748 * @cpucp_card_type_pci: PCI card. 749 * @cpucp_card_type_pmc: PCI Mezzanine Card. 750 */ 751 enum cpucp_card_types { 752 cpucp_card_type_pci, 753 cpucp_card_type_pmc 754 }; 755 756 #define CPUCP_SEC_CONF_ENABLED_SHIFT 0 757 #define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001 758 759 #define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1 760 #define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002 761 762 #define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2 763 #define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004 764 765 /** 766 * struct cpucp_security_info - Security information. 767 * @config: configuration bit field 768 * @keys_num: number of stored keys 769 * @revoked_keys: revoked keys bit field 770 * @min_svn: minimal security version 771 */ 772 struct cpucp_security_info { 773 __u8 config; 774 __u8 keys_num; 775 __u8 revoked_keys; 776 __u8 min_svn; 777 }; 778 779 /** 780 * struct cpucp_info - Info from CpuCP that is necessary to the host's driver 781 * @sensors: available sensors description. 782 * @kernel_version: CpuCP linux kernel version. 783 * @reserved: reserved field. 784 * @card_type: card configuration type. 785 * @card_location: in a server, each card has different connections topology 786 * depending on its location (relevant for PMC card type) 787 * @cpld_version: CPLD programmed F/W version. 788 * @infineon_version: Infineon main DC-DC version. 789 * @fuse_version: silicon production FUSE information. 790 * @thermal_version: thermald S/W version. 791 * @cpucp_version: CpuCP S/W version. 792 * @infineon_second_stage_version: Infineon 2nd stage DC-DC version. 793 * @dram_size: available DRAM size. 794 * @card_name: card name that will be displayed in HWMON subsystem on the host 795 * @sec_info: security information 796 * @pll_map: Bit map of supported PLLs for current ASIC version. 797 * @mme_binning_mask: MME binning mask, 798 * (0 = functional, 1 = binned) 799 * @dram_binning_mask: DRAM binning mask, 1 bit per dram instance 800 * (0 = functional 1 = binned) 801 * @memory_repair_flag: eFuse flag indicating memory repair 802 * @edma_binning_mask: EDMA binning mask, 1 bit per EDMA instance 803 * (0 = functional 1 = binned) 804 * @xbar_binning_mask: Xbar binning mask, 1 bit per Xbar instance 805 * (0 = functional 1 = binned) 806 * @fw_os_version: Firmware OS Version 807 */ 808 struct cpucp_info { 809 struct cpucp_sensor sensors[CPUCP_MAX_SENSORS]; 810 __u8 kernel_version[VERSION_MAX_LEN]; 811 __le32 reserved; 812 __le32 card_type; 813 __le32 card_location; 814 __le32 cpld_version; 815 __le32 infineon_version; 816 __u8 fuse_version[VERSION_MAX_LEN]; 817 __u8 thermal_version[VERSION_MAX_LEN]; 818 __u8 cpucp_version[VERSION_MAX_LEN]; 819 __le32 infineon_second_stage_version; 820 __le64 dram_size; 821 char card_name[CARD_NAME_MAX_LEN]; 822 __le64 reserved3; 823 __le64 reserved4; 824 __u8 reserved5; 825 __u8 dram_binning_mask; 826 __u8 memory_repair_flag; 827 __u8 edma_binning_mask; 828 __u8 xbar_binning_mask; 829 __u8 pad[3]; 830 struct cpucp_security_info sec_info; 831 __le32 reserved6; 832 __u8 pll_map[PLL_MAP_LEN]; 833 __le64 mme_binning_mask; 834 __u8 fw_os_version[VERSION_MAX_LEN]; 835 }; 836 837 struct cpucp_mac_addr { 838 __u8 mac_addr[ETH_ALEN]; 839 }; 840 841 enum cpucp_serdes_type { 842 TYPE_1_SERDES_TYPE, 843 TYPE_2_SERDES_TYPE, 844 HLS1_SERDES_TYPE, 845 HLS1H_SERDES_TYPE, 846 HLS2_SERDES_TYPE, 847 UNKNOWN_SERDES_TYPE, 848 MAX_NUM_SERDES_TYPE = UNKNOWN_SERDES_TYPE 849 }; 850 851 struct cpucp_nic_info { 852 struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS]; 853 __le64 link_mask[CPUCP_NIC_MASK_ARR_LEN]; 854 __le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 855 __le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 856 __le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN]; 857 __u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN]; 858 __le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN]; 859 __le16 serdes_type; /* enum cpucp_serdes_type */ 860 __le16 tx_swap_map[CPUCP_MAX_NICS]; 861 __u8 reserved[6]; 862 }; 863 864 #define PAGE_DISCARD_MAX 64 865 866 struct page_discard_info { 867 __u8 num_entries; 868 __u8 reserved[7]; 869 __le32 mmu_page_idx[PAGE_DISCARD_MAX]; 870 }; 871 872 /* 873 * struct ser_val - the SER (symbol error rate) value is represented by "integer * 10 ^ -exp". 874 * @integer: the integer part of the SER value; 875 * @exp: the exponent part of the SER value. 876 */ 877 struct ser_val { 878 __le16 integer; 879 __le16 exp; 880 }; 881 882 /* 883 * struct cpucp_nic_status - describes the status of a NIC port. 884 * @port: NIC port index. 885 * @bad_format_cnt: e.g. CRC. 886 * @responder_out_of_sequence_psn_cnt: e.g NAK. 887 * @high_ber_reinit_cnt: link reinit due to high BER. 888 * @correctable_err_cnt: e.g. bit-flip. 889 * @uncorrectable_err_cnt: e.g. MAC errors. 890 * @retraining_cnt: re-training counter. 891 * @up: is port up. 892 * @pcs_link: has PCS link. 893 * @phy_ready: is PHY ready. 894 * @auto_neg: is Autoneg enabled. 895 * @timeout_retransmission_cnt: timeout retransmission events 896 * @high_ber_cnt: high ber events 897 */ 898 struct cpucp_nic_status { 899 __le32 port; 900 __le32 bad_format_cnt; 901 __le32 responder_out_of_sequence_psn_cnt; 902 __le32 high_ber_reinit; 903 __le32 correctable_err_cnt; 904 __le32 uncorrectable_err_cnt; 905 __le32 retraining_cnt; 906 __u8 up; 907 __u8 pcs_link; 908 __u8 phy_ready; 909 __u8 auto_neg; 910 __le32 timeout_retransmission_cnt; 911 __le32 high_ber_cnt; 912 }; 913 914 enum cpucp_hbm_row_replace_cause { 915 REPLACE_CAUSE_DOUBLE_ECC_ERR, 916 REPLACE_CAUSE_MULTI_SINGLE_ECC_ERR, 917 }; 918 919 struct cpucp_hbm_row_info { 920 __u8 hbm_idx; 921 __u8 pc; 922 __u8 sid; 923 __u8 bank_idx; 924 __le16 row_addr; 925 __u8 replaced_row_cause; /* enum cpucp_hbm_row_replace_cause */ 926 __u8 pad; 927 }; 928 929 struct cpucp_hbm_row_replaced_rows_info { 930 __le16 num_replaced_rows; 931 __u8 pad[6]; 932 struct cpucp_hbm_row_info replaced_rows[CPUCP_HBM_ROW_REPLACE_MAX]; 933 }; 934 935 /* 936 * struct dcore_monitor_regs_data - DCORE monitor regs data. 937 * the structure follows sync manager block layout. relevant only to Gaudi. 938 * @mon_pay_addrl: array of payload address low bits. 939 * @mon_pay_addrh: array of payload address high bits. 940 * @mon_pay_data: array of payload data. 941 * @mon_arm: array of monitor arm. 942 * @mon_status: array of monitor status. 943 */ 944 struct dcore_monitor_regs_data { 945 __le32 mon_pay_addrl[512]; 946 __le32 mon_pay_addrh[512]; 947 __le32 mon_pay_data[512]; 948 __le32 mon_arm[512]; 949 __le32 mon_status[512]; 950 }; 951 952 /* contains SM data for each SYNC_MNGR (relevant only to Gaudi) */ 953 struct cpucp_monitor_dump { 954 struct dcore_monitor_regs_data sync_mngr_w_s; 955 struct dcore_monitor_regs_data sync_mngr_e_s; 956 struct dcore_monitor_regs_data sync_mngr_w_n; 957 struct dcore_monitor_regs_data sync_mngr_e_n; 958 }; 959 960 #endif /* CPUCP_IF_H */ 961