1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Macros for accessing system registers with older binutils.
4  *
5  * Copyright (C) 2014 ARM Ltd.
6  * Author: Catalin Marinas <catalin.marinas@arm.com>
7  */
8 
9 #ifndef __ASM_SYSREG_H
10 #define __ASM_SYSREG_H
11 
12 #include <linux/bits.h>
13 #include <linux/stringify.h>
14 #include <linux/kasan-tags.h>
15 
16 #include <asm/gpr-num.h>
17 
18 /*
19  * ARMv8 ARM reserves the following encoding for system registers:
20  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
21  *  C5.2, version:ARM DDI 0487A.f)
22  *	[20-19] : Op0
23  *	[18-16] : Op1
24  *	[15-12] : CRn
25  *	[11-8]  : CRm
26  *	[7-5]   : Op2
27  */
28 #define Op0_shift	19
29 #define Op0_mask	0x3
30 #define Op1_shift	16
31 #define Op1_mask	0x7
32 #define CRn_shift	12
33 #define CRn_mask	0xf
34 #define CRm_shift	8
35 #define CRm_mask	0xf
36 #define Op2_shift	5
37 #define Op2_mask	0x7
38 
39 #define sys_reg(op0, op1, crn, crm, op2) \
40 	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
41 	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
42 	 ((op2) << Op2_shift))
43 
44 #define sys_insn	sys_reg
45 
46 #define sys_reg_Op0(id)	(((id) >> Op0_shift) & Op0_mask)
47 #define sys_reg_Op1(id)	(((id) >> Op1_shift) & Op1_mask)
48 #define sys_reg_CRn(id)	(((id) >> CRn_shift) & CRn_mask)
49 #define sys_reg_CRm(id)	(((id) >> CRm_shift) & CRm_mask)
50 #define sys_reg_Op2(id)	(((id) >> Op2_shift) & Op2_mask)
51 
52 #ifndef CONFIG_BROKEN_GAS_INST
53 
54 #ifdef __ASSEMBLY__
55 // The space separator is omitted so that __emit_inst(x) can be parsed as
56 // either an assembler directive or an assembler macro argument.
57 #define __emit_inst(x)			.inst(x)
58 #else
59 #define __emit_inst(x)			".inst " __stringify((x)) "\n\t"
60 #endif
61 
62 #else  /* CONFIG_BROKEN_GAS_INST */
63 
64 #ifndef CONFIG_CPU_BIG_ENDIAN
65 #define __INSTR_BSWAP(x)		(x)
66 #else  /* CONFIG_CPU_BIG_ENDIAN */
67 #define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
68 					 (((x) <<  8) & 0x00ff0000)	| \
69 					 (((x) >>  8) & 0x0000ff00)	| \
70 					 (((x) >> 24) & 0x000000ff))
71 #endif	/* CONFIG_CPU_BIG_ENDIAN */
72 
73 #ifdef __ASSEMBLY__
74 #define __emit_inst(x)			.long __INSTR_BSWAP(x)
75 #else  /* __ASSEMBLY__ */
76 #define __emit_inst(x)			".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
77 #endif	/* __ASSEMBLY__ */
78 
79 #endif	/* CONFIG_BROKEN_GAS_INST */
80 
81 /*
82  * Instructions for modifying PSTATE fields.
83  * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
84  * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
85  * for accessing PSTATE fields have the following encoding:
86  *	Op0 = 0, CRn = 4
87  *	Op1, Op2 encodes the PSTATE field modified and defines the constraints.
88  *	CRm = Imm4 for the instruction.
89  *	Rt = 0x1f
90  */
91 #define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
92 #define PSTATE_Imm_shift		CRm_shift
93 
94 #define PSTATE_PAN			pstate_field(0, 4)
95 #define PSTATE_UAO			pstate_field(0, 3)
96 #define PSTATE_SSBS			pstate_field(3, 1)
97 #define PSTATE_TCO			pstate_field(3, 4)
98 
99 #define SET_PSTATE_PAN(x)		__emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
100 #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
101 #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
102 #define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
103 
104 #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
105 #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
106 #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
107 
108 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
109 	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
110 
111 #define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
112 
113 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
114 #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
115 #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
116 
117 /*
118  * Automatically generated definitions for system registers, the
119  * manual encodings below are in the process of being converted to
120  * come from here. The header relies on the definition of sys_reg()
121  * earlier in this file.
122  */
123 #include "asm/sysreg-defs.h"
124 
125 /*
126  * System registers, organised loosely by encoding but grouped together
127  * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
128  */
129 #define SYS_SVCR_SMSTOP_SM_EL0		sys_reg(0, 3, 4, 2, 3)
130 #define SYS_SVCR_SMSTART_SM_EL0		sys_reg(0, 3, 4, 3, 3)
131 #define SYS_SVCR_SMSTOP_SMZA_EL0	sys_reg(0, 3, 4, 6, 3)
132 
133 #define SYS_OSDTRRX_EL1			sys_reg(2, 0, 0, 0, 2)
134 #define SYS_MDCCINT_EL1			sys_reg(2, 0, 0, 2, 0)
135 #define SYS_MDSCR_EL1			sys_reg(2, 0, 0, 2, 2)
136 #define SYS_OSDTRTX_EL1			sys_reg(2, 0, 0, 3, 2)
137 #define SYS_OSECCR_EL1			sys_reg(2, 0, 0, 6, 2)
138 #define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
139 #define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
140 #define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
141 #define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
142 #define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
143 
144 #define SYS_OSLAR_EL1			sys_reg(2, 0, 1, 0, 4)
145 #define SYS_OSLAR_OSLK			BIT(0)
146 
147 #define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
148 #define SYS_OSLSR_OSLM_MASK		(BIT(3) | BIT(0))
149 #define SYS_OSLSR_OSLM_NI		0
150 #define SYS_OSLSR_OSLM_IMPLEMENTED	BIT(3)
151 #define SYS_OSLSR_OSLK			BIT(1)
152 
153 #define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
154 #define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
155 #define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
156 #define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
157 #define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
158 #define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
159 #define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
160 #define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
161 #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
162 #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
163 
164 #define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
165 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
166 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
167 
168 #define SYS_ID_PFR0_EL1			sys_reg(3, 0, 0, 1, 0)
169 #define SYS_ID_PFR1_EL1			sys_reg(3, 0, 0, 1, 1)
170 #define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)
171 #define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
172 #define SYS_ID_DFR1_EL1			sys_reg(3, 0, 0, 3, 5)
173 #define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)
174 #define SYS_ID_MMFR0_EL1		sys_reg(3, 0, 0, 1, 4)
175 #define SYS_ID_MMFR1_EL1		sys_reg(3, 0, 0, 1, 5)
176 #define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)
177 #define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)
178 #define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)
179 #define SYS_ID_MMFR5_EL1		sys_reg(3, 0, 0, 3, 6)
180 
181 #define SYS_ID_ISAR0_EL1		sys_reg(3, 0, 0, 2, 0)
182 #define SYS_ID_ISAR1_EL1		sys_reg(3, 0, 0, 2, 1)
183 #define SYS_ID_ISAR2_EL1		sys_reg(3, 0, 0, 2, 2)
184 #define SYS_ID_ISAR3_EL1		sys_reg(3, 0, 0, 2, 3)
185 #define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)
186 #define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)
187 #define SYS_ID_ISAR6_EL1		sys_reg(3, 0, 0, 2, 7)
188 
189 #define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
190 #define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
191 #define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
192 
193 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
194 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
195 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
196 
197 #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
198 
199 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
200 
201 #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
202 #define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
203 #define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
204 #define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
205 
206 #define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
207 #define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
208 #define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
209 #define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
210 
211 #define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
212 #define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
213 
214 #define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
215 #define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
216 
217 #define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
218 
219 #define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
220 #define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
221 #define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
222 
223 #define SYS_ERRIDR_EL1			sys_reg(3, 0, 5, 3, 0)
224 #define SYS_ERRSELR_EL1			sys_reg(3, 0, 5, 3, 1)
225 #define SYS_ERXFR_EL1			sys_reg(3, 0, 5, 4, 0)
226 #define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)
227 #define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)
228 #define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
229 #define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
230 #define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
231 #define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
232 #define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
233 
234 #define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
235 
236 #define SYS_PAR_EL1_F			BIT(0)
237 #define SYS_PAR_EL1_FST			GENMASK(6, 1)
238 
239 /*** Statistical Profiling Extension ***/
240 /* ID registers */
241 #define SYS_PMSIDR_EL1			sys_reg(3, 0, 9, 9, 7)
242 #define SYS_PMSIDR_EL1_FE_SHIFT		0
243 #define SYS_PMSIDR_EL1_FT_SHIFT		1
244 #define SYS_PMSIDR_EL1_FL_SHIFT		2
245 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT	3
246 #define SYS_PMSIDR_EL1_LDS_SHIFT	4
247 #define SYS_PMSIDR_EL1_ERND_SHIFT	5
248 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT	8
249 #define SYS_PMSIDR_EL1_INTERVAL_MASK	0xfUL
250 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT	12
251 #define SYS_PMSIDR_EL1_MAXSIZE_MASK	0xfUL
252 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT	16
253 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK	0xfUL
254 
255 #define SYS_PMBIDR_EL1			sys_reg(3, 0, 9, 10, 7)
256 #define SYS_PMBIDR_EL1_ALIGN_SHIFT	0
257 #define SYS_PMBIDR_EL1_ALIGN_MASK	0xfU
258 #define SYS_PMBIDR_EL1_P_SHIFT		4
259 #define SYS_PMBIDR_EL1_F_SHIFT		5
260 
261 /* Sampling controls */
262 #define SYS_PMSCR_EL1			sys_reg(3, 0, 9, 9, 0)
263 #define SYS_PMSCR_EL1_E0SPE_SHIFT	0
264 #define SYS_PMSCR_EL1_E1SPE_SHIFT	1
265 #define SYS_PMSCR_EL1_CX_SHIFT		3
266 #define SYS_PMSCR_EL1_PA_SHIFT		4
267 #define SYS_PMSCR_EL1_TS_SHIFT		5
268 #define SYS_PMSCR_EL1_PCT_SHIFT		6
269 
270 #define SYS_PMSCR_EL2			sys_reg(3, 4, 9, 9, 0)
271 #define SYS_PMSCR_EL2_E0HSPE_SHIFT	0
272 #define SYS_PMSCR_EL2_E2SPE_SHIFT	1
273 #define SYS_PMSCR_EL2_CX_SHIFT		3
274 #define SYS_PMSCR_EL2_PA_SHIFT		4
275 #define SYS_PMSCR_EL2_TS_SHIFT		5
276 #define SYS_PMSCR_EL2_PCT_SHIFT		6
277 
278 #define SYS_PMSICR_EL1			sys_reg(3, 0, 9, 9, 2)
279 
280 #define SYS_PMSIRR_EL1			sys_reg(3, 0, 9, 9, 3)
281 #define SYS_PMSIRR_EL1_RND_SHIFT	0
282 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT	8
283 #define SYS_PMSIRR_EL1_INTERVAL_MASK	0xffffffUL
284 
285 /* Filtering controls */
286 #define SYS_PMSNEVFR_EL1		sys_reg(3, 0, 9, 9, 1)
287 
288 #define SYS_PMSFCR_EL1			sys_reg(3, 0, 9, 9, 4)
289 #define SYS_PMSFCR_EL1_FE_SHIFT		0
290 #define SYS_PMSFCR_EL1_FT_SHIFT		1
291 #define SYS_PMSFCR_EL1_FL_SHIFT		2
292 #define SYS_PMSFCR_EL1_B_SHIFT		16
293 #define SYS_PMSFCR_EL1_LD_SHIFT		17
294 #define SYS_PMSFCR_EL1_ST_SHIFT		18
295 
296 #define SYS_PMSEVFR_EL1			sys_reg(3, 0, 9, 9, 5)
297 #define SYS_PMSEVFR_EL1_RES0_8_2	\
298 	(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
299 	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
300 #define SYS_PMSEVFR_EL1_RES0_8_3	\
301 	(SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
302 
303 #define SYS_PMSLATFR_EL1		sys_reg(3, 0, 9, 9, 6)
304 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT	0
305 
306 /* Buffer controls */
307 #define SYS_PMBLIMITR_EL1		sys_reg(3, 0, 9, 10, 0)
308 #define SYS_PMBLIMITR_EL1_E_SHIFT	0
309 #define SYS_PMBLIMITR_EL1_FM_SHIFT	1
310 #define SYS_PMBLIMITR_EL1_FM_MASK	0x3UL
311 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ	(0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
312 
313 #define SYS_PMBPTR_EL1			sys_reg(3, 0, 9, 10, 1)
314 
315 /* Buffer error reporting */
316 #define SYS_PMBSR_EL1			sys_reg(3, 0, 9, 10, 3)
317 #define SYS_PMBSR_EL1_COLL_SHIFT	16
318 #define SYS_PMBSR_EL1_S_SHIFT		17
319 #define SYS_PMBSR_EL1_EA_SHIFT		18
320 #define SYS_PMBSR_EL1_DL_SHIFT		19
321 #define SYS_PMBSR_EL1_EC_SHIFT		26
322 #define SYS_PMBSR_EL1_EC_MASK		0x3fUL
323 
324 #define SYS_PMBSR_EL1_EC_BUF		(0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
325 #define SYS_PMBSR_EL1_EC_FAULT_S1	(0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
326 #define SYS_PMBSR_EL1_EC_FAULT_S2	(0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
327 
328 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT	0
329 #define SYS_PMBSR_EL1_FAULT_FSC_MASK	0x3fUL
330 
331 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT	0
332 #define SYS_PMBSR_EL1_BUF_BSC_MASK	0x3fUL
333 
334 #define SYS_PMBSR_EL1_BUF_BSC_FULL	(0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
335 
336 /*** End of Statistical Profiling Extension ***/
337 
338 /*
339  * TRBE Registers
340  */
341 #define SYS_TRBLIMITR_EL1		sys_reg(3, 0, 9, 11, 0)
342 #define SYS_TRBPTR_EL1			sys_reg(3, 0, 9, 11, 1)
343 #define SYS_TRBBASER_EL1		sys_reg(3, 0, 9, 11, 2)
344 #define SYS_TRBSR_EL1			sys_reg(3, 0, 9, 11, 3)
345 #define SYS_TRBMAR_EL1			sys_reg(3, 0, 9, 11, 4)
346 #define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)
347 #define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)
348 
349 #define TRBLIMITR_LIMIT_MASK		GENMASK_ULL(51, 0)
350 #define TRBLIMITR_LIMIT_SHIFT		12
351 #define TRBLIMITR_NVM			BIT(5)
352 #define TRBLIMITR_TRIG_MODE_MASK	GENMASK(1, 0)
353 #define TRBLIMITR_TRIG_MODE_SHIFT	3
354 #define TRBLIMITR_FILL_MODE_MASK	GENMASK(1, 0)
355 #define TRBLIMITR_FILL_MODE_SHIFT	1
356 #define TRBLIMITR_ENABLE		BIT(0)
357 #define TRBPTR_PTR_MASK			GENMASK_ULL(63, 0)
358 #define TRBPTR_PTR_SHIFT		0
359 #define TRBBASER_BASE_MASK		GENMASK_ULL(51, 0)
360 #define TRBBASER_BASE_SHIFT		12
361 #define TRBSR_EC_MASK			GENMASK(5, 0)
362 #define TRBSR_EC_SHIFT			26
363 #define TRBSR_IRQ			BIT(22)
364 #define TRBSR_TRG			BIT(21)
365 #define TRBSR_WRAP			BIT(20)
366 #define TRBSR_ABORT			BIT(18)
367 #define TRBSR_STOP			BIT(17)
368 #define TRBSR_MSS_MASK			GENMASK(15, 0)
369 #define TRBSR_MSS_SHIFT			0
370 #define TRBSR_BSC_MASK			GENMASK(5, 0)
371 #define TRBSR_BSC_SHIFT			0
372 #define TRBSR_FSC_MASK			GENMASK(5, 0)
373 #define TRBSR_FSC_SHIFT			0
374 #define TRBMAR_SHARE_MASK		GENMASK(1, 0)
375 #define TRBMAR_SHARE_SHIFT		8
376 #define TRBMAR_OUTER_MASK		GENMASK(3, 0)
377 #define TRBMAR_OUTER_SHIFT		4
378 #define TRBMAR_INNER_MASK		GENMASK(3, 0)
379 #define TRBMAR_INNER_SHIFT		0
380 #define TRBTRG_TRG_MASK			GENMASK(31, 0)
381 #define TRBTRG_TRG_SHIFT		0
382 #define TRBIDR_FLAG			BIT(5)
383 #define TRBIDR_PROG			BIT(4)
384 #define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
385 #define TRBIDR_ALIGN_SHIFT		0
386 
387 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
388 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
389 
390 #define SYS_PMMIR_EL1			sys_reg(3, 0, 9, 14, 6)
391 
392 #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
393 #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
394 
395 #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
396 #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
397 
398 #define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
399 #define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
400 #define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
401 #define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
402 #define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
403 #define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)
404 #define SYS_ICC_AP0R1_EL1		SYS_ICC_AP0Rn_EL1(1)
405 #define SYS_ICC_AP0R2_EL1		SYS_ICC_AP0Rn_EL1(2)
406 #define SYS_ICC_AP0R3_EL1		SYS_ICC_AP0Rn_EL1(3)
407 #define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
408 #define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)
409 #define SYS_ICC_AP1R1_EL1		SYS_ICC_AP1Rn_EL1(1)
410 #define SYS_ICC_AP1R2_EL1		SYS_ICC_AP1Rn_EL1(2)
411 #define SYS_ICC_AP1R3_EL1		SYS_ICC_AP1Rn_EL1(3)
412 #define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
413 #define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
414 #define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
415 #define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
416 #define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
417 #define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
418 #define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
419 #define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
420 #define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
421 #define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
422 #define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
423 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
424 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
425 
426 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
427 
428 #define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
429 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
430 
431 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
432 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
433 
434 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
435 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
436 #define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
437 #define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
438 #define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
439 #define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
440 #define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
441 #define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
442 #define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
443 #define SYS_PMXEVTYPER_EL0		sys_reg(3, 3, 9, 13, 1)
444 #define SYS_PMXEVCNTR_EL0		sys_reg(3, 3, 9, 13, 2)
445 #define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
446 #define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
447 
448 #define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
449 #define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
450 #define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
451 
452 #define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
453 
454 /* Definitions for system register interface to AMU for ARMv8.4 onwards */
455 #define SYS_AM_EL0(crm, op2)		sys_reg(3, 3, 13, (crm), (op2))
456 #define SYS_AMCR_EL0			SYS_AM_EL0(2, 0)
457 #define SYS_AMCFGR_EL0			SYS_AM_EL0(2, 1)
458 #define SYS_AMCGCR_EL0			SYS_AM_EL0(2, 2)
459 #define SYS_AMUSERENR_EL0		SYS_AM_EL0(2, 3)
460 #define SYS_AMCNTENCLR0_EL0		SYS_AM_EL0(2, 4)
461 #define SYS_AMCNTENSET0_EL0		SYS_AM_EL0(2, 5)
462 #define SYS_AMCNTENCLR1_EL0		SYS_AM_EL0(3, 0)
463 #define SYS_AMCNTENSET1_EL0		SYS_AM_EL0(3, 1)
464 
465 /*
466  * Group 0 of activity monitors (architected):
467  *                op0  op1  CRn   CRm       op2
468  * Counter:       11   011  1101  010:n<3>  n<2:0>
469  * Type:          11   011  1101  011:n<3>  n<2:0>
470  * n: 0-15
471  *
472  * Group 1 of activity monitors (auxiliary):
473  *                op0  op1  CRn   CRm       op2
474  * Counter:       11   011  1101  110:n<3>  n<2:0>
475  * Type:          11   011  1101  111:n<3>  n<2:0>
476  * n: 0-15
477  */
478 
479 #define SYS_AMEVCNTR0_EL0(n)		SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
480 #define SYS_AMEVTYPER0_EL0(n)		SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
481 #define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
482 #define SYS_AMEVTYPER1_EL0(n)		SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
483 
484 /* AMU v1: Fixed (architecturally defined) activity monitors */
485 #define SYS_AMEVCNTR0_CORE_EL0		SYS_AMEVCNTR0_EL0(0)
486 #define SYS_AMEVCNTR0_CONST_EL0		SYS_AMEVCNTR0_EL0(1)
487 #define SYS_AMEVCNTR0_INST_RET_EL0	SYS_AMEVCNTR0_EL0(2)
488 #define SYS_AMEVCNTR0_MEM_STALL		SYS_AMEVCNTR0_EL0(3)
489 
490 #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
491 
492 #define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
493 #define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
494 
495 #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
496 #define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
497 #define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
498 
499 #define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)
500 #define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)
501 
502 #define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
503 #define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
504 #define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
505 
506 #define __PMEV_op2(n)			((n) & 0x7)
507 #define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
508 #define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
509 #define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
510 #define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
511 
512 #define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
513 
514 #define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
515 #define SYS_HFGRTR_EL2			sys_reg(3, 4, 1, 1, 4)
516 #define SYS_HFGWTR_EL2			sys_reg(3, 4, 1, 1, 5)
517 #define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)
518 #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
519 #define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
520 #define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
521 #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
522 #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
523 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
524 #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
525 #define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
526 #define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
527 #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
528 #define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
529 
530 #define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1,  1)
531 #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
532 #define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
533 #define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
534 #define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
535 #define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
536 
537 #define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
538 #define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
539 #define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
540 #define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
541 #define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
542 
543 #define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
544 #define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
545 #define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
546 #define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
547 #define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
548 #define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
549 #define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
550 #define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
551 
552 #define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
553 #define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
554 #define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
555 #define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
556 #define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
557 #define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
558 #define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
559 #define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
560 #define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
561 
562 #define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
563 #define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
564 #define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
565 #define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
566 #define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
567 #define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
568 #define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
569 #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
570 #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
571 
572 /* VHE encodings for architectural EL0/1 system registers */
573 #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
574 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
575 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
576 #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
577 #define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
578 #define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
579 #define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
580 #define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
581 #define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
582 #define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
583 #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
584 #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
585 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
586 #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
587 #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
588 #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
589 #define SYS_CNTP_CVAL_EL02		sys_reg(3, 5, 14, 2, 2)
590 #define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
591 #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
592 #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
593 
594 /* Common SCTLR_ELx flags. */
595 #define SCTLR_ELx_ENTP2	(BIT(60))
596 #define SCTLR_ELx_DSSBS	(BIT(44))
597 #define SCTLR_ELx_ATA	(BIT(43))
598 
599 #define SCTLR_ELx_ENIA_SHIFT	31
600 
601 #define SCTLR_ELx_ITFSB	 (BIT(37))
602 #define SCTLR_ELx_ENIA	 (BIT(SCTLR_ELx_ENIA_SHIFT))
603 #define SCTLR_ELx_ENIB	 (BIT(30))
604 #define SCTLR_ELx_LSMAOE (BIT(29))
605 #define SCTLR_ELx_nTLSMD (BIT(28))
606 #define SCTLR_ELx_ENDA	 (BIT(27))
607 #define SCTLR_ELx_EE     (BIT(25))
608 #define SCTLR_ELx_EIS	 (BIT(22))
609 #define SCTLR_ELx_IESB	 (BIT(21))
610 #define SCTLR_ELx_TSCXT	 (BIT(20))
611 #define SCTLR_ELx_WXN	 (BIT(19))
612 #define SCTLR_ELx_ENDB	 (BIT(13))
613 #define SCTLR_ELx_I	 (BIT(12))
614 #define SCTLR_ELx_EOS	 (BIT(11))
615 #define SCTLR_ELx_SA	 (BIT(3))
616 #define SCTLR_ELx_C	 (BIT(2))
617 #define SCTLR_ELx_A	 (BIT(1))
618 #define SCTLR_ELx_M	 (BIT(0))
619 
620 /* SCTLR_EL2 specific flags. */
621 #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
622 			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
623 			 (BIT(29)))
624 
625 #ifdef CONFIG_CPU_BIG_ENDIAN
626 #define ENDIAN_SET_EL2		SCTLR_ELx_EE
627 #else
628 #define ENDIAN_SET_EL2		0
629 #endif
630 
631 #define INIT_SCTLR_EL2_MMU_ON						\
632 	(SCTLR_ELx_M  | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I |	\
633 	 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 |		\
634 	 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
635 
636 #define INIT_SCTLR_EL2_MMU_OFF \
637 	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
638 
639 /* SCTLR_EL1 specific flags. */
640 #ifdef CONFIG_CPU_BIG_ENDIAN
641 #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
642 #else
643 #define ENDIAN_SET_EL1		0
644 #endif
645 
646 #define INIT_SCTLR_EL1_MMU_OFF \
647 	(ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
648 	 SCTLR_EL1_EIS  | SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
649 
650 #define INIT_SCTLR_EL1_MMU_ON \
651 	(SCTLR_ELx_M      | SCTLR_ELx_C      | SCTLR_ELx_SA    | \
652 	 SCTLR_EL1_SA0    | SCTLR_EL1_SED    | SCTLR_ELx_I     | \
653 	 SCTLR_EL1_DZE    | SCTLR_EL1_UCT    | SCTLR_EL1_nTWE  | \
654 	 SCTLR_ELx_IESB   | SCTLR_EL1_SPAN   | SCTLR_ELx_ITFSB | \
655 	 ENDIAN_SET_EL1   | SCTLR_EL1_UCI    | SCTLR_EL1_EPAN  | \
656 	 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS   | \
657 	 SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
658 
659 /* MAIR_ELx memory attributes (used by Linux) */
660 #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
661 #define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
662 #define MAIR_ATTR_NORMAL_NC		UL(0x44)
663 #define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)
664 #define MAIR_ATTR_NORMAL		UL(0xff)
665 #define MAIR_ATTR_MASK			UL(0xff)
666 
667 /* Position the attr at the correct index */
668 #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
669 
670 /* id_aa64pfr0 */
671 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1
672 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2
673 
674 /* id_aa64mmfr0 */
675 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
676 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
677 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
678 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
679 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
680 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
681 
682 #define ARM64_MIN_PARANGE_BITS		32
683 
684 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0
685 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1
686 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2
687 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7
688 
689 #ifdef CONFIG_ARM64_PA_BITS_52
690 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_52
691 #else
692 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48
693 #endif
694 
695 #define ID_DFR0_PERFMON_SHIFT		24
696 
697 #define ID_DFR0_PERFMON_8_0		0x3
698 #define ID_DFR0_PERFMON_8_1		0x4
699 #define ID_DFR0_PERFMON_8_4		0x5
700 #define ID_DFR0_PERFMON_8_5		0x6
701 
702 #define ID_ISAR4_SWP_FRAC_SHIFT		28
703 #define ID_ISAR4_PSR_M_SHIFT		24
704 #define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT	20
705 #define ID_ISAR4_BARRIER_SHIFT		16
706 #define ID_ISAR4_SMC_SHIFT		12
707 #define ID_ISAR4_WRITEBACK_SHIFT	8
708 #define ID_ISAR4_WITHSHIFTS_SHIFT	4
709 #define ID_ISAR4_UNPRIV_SHIFT		0
710 
711 #define ID_DFR1_MTPMU_SHIFT		0
712 
713 #define ID_ISAR0_DIVIDE_SHIFT		24
714 #define ID_ISAR0_DEBUG_SHIFT		20
715 #define ID_ISAR0_COPROC_SHIFT		16
716 #define ID_ISAR0_CMPBRANCH_SHIFT	12
717 #define ID_ISAR0_BITFIELD_SHIFT		8
718 #define ID_ISAR0_BITCOUNT_SHIFT		4
719 #define ID_ISAR0_SWAP_SHIFT		0
720 
721 #define ID_ISAR5_RDM_SHIFT		24
722 #define ID_ISAR5_CRC32_SHIFT		16
723 #define ID_ISAR5_SHA2_SHIFT		12
724 #define ID_ISAR5_SHA1_SHIFT		8
725 #define ID_ISAR5_AES_SHIFT		4
726 #define ID_ISAR5_SEVL_SHIFT		0
727 
728 #define ID_ISAR6_I8MM_SHIFT		24
729 #define ID_ISAR6_BF16_SHIFT		20
730 #define ID_ISAR6_SPECRES_SHIFT		16
731 #define ID_ISAR6_SB_SHIFT		12
732 #define ID_ISAR6_FHM_SHIFT		8
733 #define ID_ISAR6_DP_SHIFT		4
734 #define ID_ISAR6_JSCVT_SHIFT		0
735 
736 #define ID_MMFR0_INNERSHR_SHIFT		28
737 #define ID_MMFR0_FCSE_SHIFT		24
738 #define ID_MMFR0_AUXREG_SHIFT		20
739 #define ID_MMFR0_TCM_SHIFT		16
740 #define ID_MMFR0_SHARELVL_SHIFT		12
741 #define ID_MMFR0_OUTERSHR_SHIFT		8
742 #define ID_MMFR0_PMSA_SHIFT		4
743 #define ID_MMFR0_VMSA_SHIFT		0
744 
745 #define ID_MMFR4_EVT_SHIFT		28
746 #define ID_MMFR4_CCIDX_SHIFT		24
747 #define ID_MMFR4_LSM_SHIFT		20
748 #define ID_MMFR4_HPDS_SHIFT		16
749 #define ID_MMFR4_CNP_SHIFT		12
750 #define ID_MMFR4_XNX_SHIFT		8
751 #define ID_MMFR4_AC2_SHIFT		4
752 #define ID_MMFR4_SPECSEI_SHIFT		0
753 
754 #define ID_MMFR5_ETS_SHIFT		0
755 
756 #define ID_PFR0_DIT_SHIFT		24
757 #define ID_PFR0_CSV2_SHIFT		16
758 #define ID_PFR0_STATE3_SHIFT		12
759 #define ID_PFR0_STATE2_SHIFT		8
760 #define ID_PFR0_STATE1_SHIFT		4
761 #define ID_PFR0_STATE0_SHIFT		0
762 
763 #define ID_DFR0_PERFMON_SHIFT		24
764 #define ID_DFR0_MPROFDBG_SHIFT		20
765 #define ID_DFR0_MMAPTRC_SHIFT		16
766 #define ID_DFR0_COPTRC_SHIFT		12
767 #define ID_DFR0_MMAPDBG_SHIFT		8
768 #define ID_DFR0_COPSDBG_SHIFT		4
769 #define ID_DFR0_COPDBG_SHIFT		0
770 
771 #define ID_PFR2_SSBS_SHIFT		4
772 #define ID_PFR2_CSV3_SHIFT		0
773 
774 #define MVFR0_FPROUND_SHIFT		28
775 #define MVFR0_FPSHVEC_SHIFT		24
776 #define MVFR0_FPSQRT_SHIFT		20
777 #define MVFR0_FPDIVIDE_SHIFT		16
778 #define MVFR0_FPTRAP_SHIFT		12
779 #define MVFR0_FPDP_SHIFT		8
780 #define MVFR0_FPSP_SHIFT		4
781 #define MVFR0_SIMD_SHIFT		0
782 
783 #define MVFR1_SIMDFMAC_SHIFT		28
784 #define MVFR1_FPHP_SHIFT		24
785 #define MVFR1_SIMDHP_SHIFT		20
786 #define MVFR1_SIMDSP_SHIFT		16
787 #define MVFR1_SIMDINT_SHIFT		12
788 #define MVFR1_SIMDLS_SHIFT		8
789 #define MVFR1_FPDNAN_SHIFT		4
790 #define MVFR1_FPFTZ_SHIFT		0
791 
792 #define ID_PFR1_GIC_SHIFT		28
793 #define ID_PFR1_VIRT_FRAC_SHIFT		24
794 #define ID_PFR1_SEC_FRAC_SHIFT		20
795 #define ID_PFR1_GENTIMER_SHIFT		16
796 #define ID_PFR1_VIRTUALIZATION_SHIFT	12
797 #define ID_PFR1_MPROGMOD_SHIFT		8
798 #define ID_PFR1_SECURITY_SHIFT		4
799 #define ID_PFR1_PROGMOD_SHIFT		0
800 
801 #if defined(CONFIG_ARM64_4K_PAGES)
802 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT
803 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
804 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
805 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
806 #elif defined(CONFIG_ARM64_16K_PAGES)
807 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_SHIFT
808 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
809 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
810 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
811 #elif defined(CONFIG_ARM64_64K_PAGES)
812 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_SHIFT
813 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
814 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
815 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
816 #endif
817 
818 #define MVFR2_FPMISC_SHIFT		4
819 #define MVFR2_SIMDMISC_SHIFT		0
820 
821 #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
822 #define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
823 
824 #define CPACR_EL1_SMEN_EL1EN	(BIT(24)) /* enable EL1 access */
825 #define CPACR_EL1_SMEN_EL0EN	(BIT(25)) /* enable EL0 access, if EL1EN set */
826 
827 #define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
828 #define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
829 
830 /* GCR_EL1 Definitions */
831 #define SYS_GCR_EL1_RRND	(BIT(16))
832 #define SYS_GCR_EL1_EXCL_MASK	0xffffUL
833 
834 #ifdef CONFIG_KASAN_HW_TAGS
835 /*
836  * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
837  * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
838  */
839 #define __MTE_TAG_MIN		(KASAN_TAG_MIN & 0xf)
840 #define __MTE_TAG_MAX		(KASAN_TAG_MAX & 0xf)
841 #define __MTE_TAG_INCL		GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
842 #define KERNEL_GCR_EL1_EXCL	(SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
843 #else
844 #define KERNEL_GCR_EL1_EXCL	SYS_GCR_EL1_EXCL_MASK
845 #endif
846 
847 #define KERNEL_GCR_EL1		(SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
848 
849 /* RGSR_EL1 Definitions */
850 #define SYS_RGSR_EL1_TAG_MASK	0xfUL
851 #define SYS_RGSR_EL1_SEED_SHIFT	8
852 #define SYS_RGSR_EL1_SEED_MASK	0xffffUL
853 
854 /* GMID_EL1 field definitions */
855 #define GMID_EL1_BS_SHIFT	0
856 #define GMID_EL1_BS_SIZE	4
857 
858 /* TFSR{,E0}_EL1 bit definitions */
859 #define SYS_TFSR_EL1_TF0_SHIFT	0
860 #define SYS_TFSR_EL1_TF1_SHIFT	1
861 #define SYS_TFSR_EL1_TF0	(UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
862 #define SYS_TFSR_EL1_TF1	(UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
863 
864 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
865 #define SYS_MPIDR_SAFE_VAL	(BIT(31))
866 
867 #define TRFCR_ELx_TS_SHIFT		5
868 #define TRFCR_ELx_TS_MASK		((0x3UL) << TRFCR_ELx_TS_SHIFT)
869 #define TRFCR_ELx_TS_VIRTUAL		((0x1UL) << TRFCR_ELx_TS_SHIFT)
870 #define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2UL) << TRFCR_ELx_TS_SHIFT)
871 #define TRFCR_ELx_TS_PHYSICAL		((0x3UL) << TRFCR_ELx_TS_SHIFT)
872 #define TRFCR_EL2_CX			BIT(3)
873 #define TRFCR_ELx_ExTRE			BIT(1)
874 #define TRFCR_ELx_E0TRE			BIT(0)
875 
876 /* GIC Hypervisor interface registers */
877 /* ICH_MISR_EL2 bit definitions */
878 #define ICH_MISR_EOI		(1 << 0)
879 #define ICH_MISR_U		(1 << 1)
880 
881 /* ICH_LR*_EL2 bit definitions */
882 #define ICH_LR_VIRTUAL_ID_MASK	((1ULL << 32) - 1)
883 
884 #define ICH_LR_EOI		(1ULL << 41)
885 #define ICH_LR_GROUP		(1ULL << 60)
886 #define ICH_LR_HW		(1ULL << 61)
887 #define ICH_LR_STATE		(3ULL << 62)
888 #define ICH_LR_PENDING_BIT	(1ULL << 62)
889 #define ICH_LR_ACTIVE_BIT	(1ULL << 63)
890 #define ICH_LR_PHYS_ID_SHIFT	32
891 #define ICH_LR_PHYS_ID_MASK	(0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
892 #define ICH_LR_PRIORITY_SHIFT	48
893 #define ICH_LR_PRIORITY_MASK	(0xffULL << ICH_LR_PRIORITY_SHIFT)
894 
895 /* ICH_HCR_EL2 bit definitions */
896 #define ICH_HCR_EN		(1 << 0)
897 #define ICH_HCR_UIE		(1 << 1)
898 #define ICH_HCR_NPIE		(1 << 3)
899 #define ICH_HCR_TC		(1 << 10)
900 #define ICH_HCR_TALL0		(1 << 11)
901 #define ICH_HCR_TALL1		(1 << 12)
902 #define ICH_HCR_TDIR		(1 << 14)
903 #define ICH_HCR_EOIcount_SHIFT	27
904 #define ICH_HCR_EOIcount_MASK	(0x1f << ICH_HCR_EOIcount_SHIFT)
905 
906 /* ICH_VMCR_EL2 bit definitions */
907 #define ICH_VMCR_ACK_CTL_SHIFT	2
908 #define ICH_VMCR_ACK_CTL_MASK	(1 << ICH_VMCR_ACK_CTL_SHIFT)
909 #define ICH_VMCR_FIQ_EN_SHIFT	3
910 #define ICH_VMCR_FIQ_EN_MASK	(1 << ICH_VMCR_FIQ_EN_SHIFT)
911 #define ICH_VMCR_CBPR_SHIFT	4
912 #define ICH_VMCR_CBPR_MASK	(1 << ICH_VMCR_CBPR_SHIFT)
913 #define ICH_VMCR_EOIM_SHIFT	9
914 #define ICH_VMCR_EOIM_MASK	(1 << ICH_VMCR_EOIM_SHIFT)
915 #define ICH_VMCR_BPR1_SHIFT	18
916 #define ICH_VMCR_BPR1_MASK	(7 << ICH_VMCR_BPR1_SHIFT)
917 #define ICH_VMCR_BPR0_SHIFT	21
918 #define ICH_VMCR_BPR0_MASK	(7 << ICH_VMCR_BPR0_SHIFT)
919 #define ICH_VMCR_PMR_SHIFT	24
920 #define ICH_VMCR_PMR_MASK	(0xffUL << ICH_VMCR_PMR_SHIFT)
921 #define ICH_VMCR_ENG0_SHIFT	0
922 #define ICH_VMCR_ENG0_MASK	(1 << ICH_VMCR_ENG0_SHIFT)
923 #define ICH_VMCR_ENG1_SHIFT	1
924 #define ICH_VMCR_ENG1_MASK	(1 << ICH_VMCR_ENG1_SHIFT)
925 
926 /* ICH_VTR_EL2 bit definitions */
927 #define ICH_VTR_PRI_BITS_SHIFT	29
928 #define ICH_VTR_PRI_BITS_MASK	(7 << ICH_VTR_PRI_BITS_SHIFT)
929 #define ICH_VTR_ID_BITS_SHIFT	23
930 #define ICH_VTR_ID_BITS_MASK	(7 << ICH_VTR_ID_BITS_SHIFT)
931 #define ICH_VTR_SEIS_SHIFT	22
932 #define ICH_VTR_SEIS_MASK	(1 << ICH_VTR_SEIS_SHIFT)
933 #define ICH_VTR_A3V_SHIFT	21
934 #define ICH_VTR_A3V_MASK	(1 << ICH_VTR_A3V_SHIFT)
935 #define ICH_VTR_TDS_SHIFT	19
936 #define ICH_VTR_TDS_MASK	(1 << ICH_VTR_TDS_SHIFT)
937 
938 /* HFG[WR]TR_EL2 bit definitions */
939 #define HFGxTR_EL2_nTPIDR2_EL0_SHIFT	55
940 #define HFGxTR_EL2_nTPIDR2_EL0_MASK	BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT)
941 #define HFGxTR_EL2_nSMPRI_EL1_SHIFT	54
942 #define HFGxTR_EL2_nSMPRI_EL1_MASK	BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT)
943 
944 #define ARM64_FEATURE_FIELD_BITS	4
945 
946 /* Create a mask for the feature bits of the specified feature. */
947 #define ARM64_FEATURE_MASK(x)	(GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
948 
949 #ifdef __ASSEMBLY__
950 
951 	.macro	mrs_s, rt, sreg
952 	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
953 	.endm
954 
955 	.macro	msr_s, sreg, rt
956 	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
957 	.endm
958 
959 #else
960 
961 #include <linux/bitfield.h>
962 #include <linux/build_bug.h>
963 #include <linux/types.h>
964 #include <asm/alternative.h>
965 
966 #define DEFINE_MRS_S						\
967 	__DEFINE_ASM_GPR_NUMS					\
968 "	.macro	mrs_s, rt, sreg\n"				\
969 	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
970 "	.endm\n"
971 
972 #define DEFINE_MSR_S						\
973 	__DEFINE_ASM_GPR_NUMS					\
974 "	.macro	msr_s, sreg, rt\n"				\
975 	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
976 "	.endm\n"
977 
978 #define UNDEFINE_MRS_S						\
979 "	.purgem	mrs_s\n"
980 
981 #define UNDEFINE_MSR_S						\
982 "	.purgem	msr_s\n"
983 
984 #define __mrs_s(v, r)						\
985 	DEFINE_MRS_S						\
986 "	mrs_s " v ", " __stringify(r) "\n"			\
987 	UNDEFINE_MRS_S
988 
989 #define __msr_s(r, v)						\
990 	DEFINE_MSR_S						\
991 "	msr_s " __stringify(r) ", " v "\n"			\
992 	UNDEFINE_MSR_S
993 
994 /*
995  * Unlike read_cpuid, calls to read_sysreg are never expected to be
996  * optimized away or replaced with synthetic values.
997  */
998 #define read_sysreg(r) ({					\
999 	u64 __val;						\
1000 	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
1001 	__val;							\
1002 })
1003 
1004 /*
1005  * The "Z" constraint normally means a zero immediate, but when combined with
1006  * the "%x0" template means XZR.
1007  */
1008 #define write_sysreg(v, r) do {					\
1009 	u64 __val = (u64)(v);					\
1010 	asm volatile("msr " __stringify(r) ", %x0"		\
1011 		     : : "rZ" (__val));				\
1012 } while (0)
1013 
1014 /*
1015  * For registers without architectural names, or simply unsupported by
1016  * GAS.
1017  */
1018 #define read_sysreg_s(r) ({						\
1019 	u64 __val;							\
1020 	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
1021 	__val;								\
1022 })
1023 
1024 #define write_sysreg_s(v, r) do {					\
1025 	u64 __val = (u64)(v);						\
1026 	asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));		\
1027 } while (0)
1028 
1029 /*
1030  * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
1031  * set mask are set. Other bits are left as-is.
1032  */
1033 #define sysreg_clear_set(sysreg, clear, set) do {			\
1034 	u64 __scs_val = read_sysreg(sysreg);				\
1035 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
1036 	if (__scs_new != __scs_val)					\
1037 		write_sysreg(__scs_new, sysreg);			\
1038 } while (0)
1039 
1040 #define sysreg_clear_set_s(sysreg, clear, set) do {			\
1041 	u64 __scs_val = read_sysreg_s(sysreg);				\
1042 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
1043 	if (__scs_new != __scs_val)					\
1044 		write_sysreg_s(__scs_new, sysreg);			\
1045 } while (0)
1046 
1047 #define read_sysreg_par() ({						\
1048 	u64 par;							\
1049 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
1050 	par = read_sysreg(par_el1);					\
1051 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
1052 	par;								\
1053 })
1054 
1055 #define SYS_FIELD_GET(reg, field, val)		\
1056 		 FIELD_GET(reg##_##field##_MASK, val)
1057 
1058 #define SYS_FIELD_PREP(reg, field, val)		\
1059 		 FIELD_PREP(reg##_##field##_MASK, val)
1060 
1061 #define SYS_FIELD_PREP_ENUM(reg, field, val)		\
1062 		 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
1063 
1064 #endif
1065 
1066 #endif	/* __ASM_SYSREG_H */
1067