1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2012, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef _LINUX_CORESIGHT_H
7 #define _LINUX_CORESIGHT_H
8 
9 #include <linux/amba/bus.h>
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/io.h>
13 #include <linux/perf_event.h>
14 #include <linux/sched.h>
15 
16 /* Peripheral id registers (0xFD0-0xFEC) */
17 #define CORESIGHT_PERIPHIDR4	0xfd0
18 #define CORESIGHT_PERIPHIDR5	0xfd4
19 #define CORESIGHT_PERIPHIDR6	0xfd8
20 #define CORESIGHT_PERIPHIDR7	0xfdC
21 #define CORESIGHT_PERIPHIDR0	0xfe0
22 #define CORESIGHT_PERIPHIDR1	0xfe4
23 #define CORESIGHT_PERIPHIDR2	0xfe8
24 #define CORESIGHT_PERIPHIDR3	0xfeC
25 /* Component id registers (0xFF0-0xFFC) */
26 #define CORESIGHT_COMPIDR0	0xff0
27 #define CORESIGHT_COMPIDR1	0xff4
28 #define CORESIGHT_COMPIDR2	0xff8
29 #define CORESIGHT_COMPIDR3	0xffC
30 
31 #define ETM_ARCH_V3_3		0x23
32 #define ETM_ARCH_V3_5		0x25
33 #define PFT_ARCH_V1_0		0x30
34 #define PFT_ARCH_V1_1		0x31
35 
36 #define CORESIGHT_UNLOCK	0xc5acce55
37 
38 extern struct bus_type coresight_bustype;
39 
40 enum coresight_dev_type {
41 	CORESIGHT_DEV_TYPE_SINK,
42 	CORESIGHT_DEV_TYPE_LINK,
43 	CORESIGHT_DEV_TYPE_LINKSINK,
44 	CORESIGHT_DEV_TYPE_SOURCE,
45 	CORESIGHT_DEV_TYPE_HELPER,
46 	CORESIGHT_DEV_TYPE_MAX
47 };
48 
49 enum coresight_dev_subtype_sink {
50 	CORESIGHT_DEV_SUBTYPE_SINK_DUMMY,
51 	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
52 	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
53 	CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
54 	CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
55 };
56 
57 enum coresight_dev_subtype_link {
58 	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
59 	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
60 	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
61 };
62 
63 enum coresight_dev_subtype_source {
64 	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
65 	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
66 	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
67 	CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS,
68 };
69 
70 enum coresight_dev_subtype_helper {
71 	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
72 	CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI
73 };
74 
75 /**
76  * union coresight_dev_subtype - further characterisation of a type
77  * @sink_subtype:	type of sink this component is, as defined
78  *			by @coresight_dev_subtype_sink.
79  * @link_subtype:	type of link this component is, as defined
80  *			by @coresight_dev_subtype_link.
81  * @source_subtype:	type of source this component is, as defined
82  *			by @coresight_dev_subtype_source.
83  * @helper_subtype:	type of helper this component is, as defined
84  *			by @coresight_dev_subtype_helper.
85  */
86 union coresight_dev_subtype {
87 	/* We have some devices which acts as LINK and SINK */
88 	struct {
89 		enum coresight_dev_subtype_sink sink_subtype;
90 		enum coresight_dev_subtype_link link_subtype;
91 	};
92 	enum coresight_dev_subtype_source source_subtype;
93 	enum coresight_dev_subtype_helper helper_subtype;
94 };
95 
96 /**
97  * struct coresight_platform_data - data harvested from the firmware
98  * specification.
99  *
100  * @nr_inconns: Number of elements for the input connections.
101  * @nr_outconns: Number of elements for the output connections.
102  * @out_conns: Array of nr_outconns pointers to connections from this
103  *	       component.
104  * @in_conns: Sparse array of pointers to input connections. Sparse
105  *            because the source device owns the connection so when it's
106  *            unloaded the connection leaves an empty slot.
107  */
108 struct coresight_platform_data {
109 	int nr_inconns;
110 	int nr_outconns;
111 	struct coresight_connection **out_conns;
112 	struct coresight_connection **in_conns;
113 };
114 
115 /**
116  * struct csdev_access - Abstraction of a CoreSight device access.
117  *
118  * @io_mem	: True if the device has memory mapped I/O
119  * @base	: When io_mem == true, base address of the component
120  * @read	: Read from the given "offset" of the given instance.
121  * @write	: Write "val" to the given "offset".
122  */
123 struct csdev_access {
124 	bool io_mem;
125 	union {
126 		void __iomem *base;
127 		struct {
128 			u64 (*read)(u32 offset, bool relaxed, bool _64bit);
129 			void (*write)(u64 val, u32 offset, bool relaxed,
130 				      bool _64bit);
131 		};
132 	};
133 };
134 
135 #define CSDEV_ACCESS_IOMEM(_addr)		\
136 	((struct csdev_access)	{		\
137 		.io_mem		= true,		\
138 		.base		= (_addr),	\
139 	})
140 
141 /**
142  * struct coresight_desc - description of a component required from drivers
143  * @type:	as defined by @coresight_dev_type.
144  * @subtype:	as defined by @coresight_dev_subtype.
145  * @ops:	generic operations for this component, as defined
146  *		by @coresight_ops.
147  * @pdata:	platform data collected from DT.
148  * @dev:	The device entity associated to this component.
149  * @groups:	operations specific to this component. These will end up
150  *		in the component's sysfs sub-directory.
151  * @name:	name for the coresight device, also shown under sysfs.
152  * @access:	Describe access to the device
153  */
154 struct coresight_desc {
155 	enum coresight_dev_type type;
156 	union coresight_dev_subtype subtype;
157 	const struct coresight_ops *ops;
158 	struct coresight_platform_data *pdata;
159 	struct device *dev;
160 	const struct attribute_group **groups;
161 	const char *name;
162 	struct csdev_access access;
163 };
164 
165 /**
166  * struct coresight_connection - representation of a single connection
167  * @src_port:	a connection's output port number.
168  * @dest_port:	destination's input port number @src_port is connected to.
169  * @dest_fwnode: destination component's fwnode handle.
170  * @dest_dev:	a @coresight_device representation of the component
171 		connected to @src_port. NULL until the device is created
172  * @link: Representation of the connection as a sysfs link.
173  *
174  * The full connection structure looks like this, where in_conns store
175  * references to same connection as the source device's out_conns.
176  *
177  * +-----------------------------+   +-----------------------------+
178  * |coresight_device             |   |coresight_connection         |
179  * |-----------------------------|   |-----------------------------|
180  * |                             |   |                             |
181  * |                             |   |                    dest_dev*|<--
182  * |pdata->out_conns[nr_outconns]|<->|src_dev*                     |   |
183  * |                             |   |                             |   |
184  * +-----------------------------+   +-----------------------------+   |
185  *                                                                     |
186  *                                   +-----------------------------+   |
187  *                                   |coresight_device             |   |
188  *                                   |------------------------------   |
189  *                                   |                             |   |
190  *                                   |  pdata->in_conns[nr_inconns]|<--
191  *                                   |                             |
192  *                                   +-----------------------------+
193  */
194 struct coresight_connection {
195 	int src_port;
196 	int dest_port;
197 	struct fwnode_handle *dest_fwnode;
198 	struct coresight_device *dest_dev;
199 	struct coresight_sysfs_link *link;
200 	struct coresight_device *src_dev;
201 	atomic_t src_refcnt;
202 	atomic_t dest_refcnt;
203 };
204 
205 /**
206  * struct coresight_sysfs_link - representation of a connection in sysfs.
207  * @orig:		Originating (master) coresight device for the link.
208  * @orig_name:		Name to use for the link orig->target.
209  * @target:		Target (slave) coresight device for the link.
210  * @target_name:	Name to use for the link target->orig.
211  */
212 struct coresight_sysfs_link {
213 	struct coresight_device *orig;
214 	const char *orig_name;
215 	struct coresight_device *target;
216 	const char *target_name;
217 };
218 
219 /**
220  * struct coresight_device - representation of a device as used by the framework
221  * @pdata:	Platform data with device connections associated to this device.
222  * @type:	as defined by @coresight_dev_type.
223  * @subtype:	as defined by @coresight_dev_subtype.
224  * @ops:	generic operations for this component, as defined
225  *		by @coresight_ops.
226  * @access:	Device i/o access abstraction for this device.
227  * @dev:	The device entity associated to this component.
228  * @refcnt:	keep track of what is in use.
229  * @orphan:	true if the component has connections that haven't been linked.
230  * @enable:	'true' if component is currently part of an active path.
231  * @activated:	'true' only if a _sink_ has been activated.  A sink can be
232  *		activated but not yet enabled.  Enabling for a _sink_
233  *		happens when a source has been selected and a path is enabled
234  *		from source to that sink.
235  * @ea:		Device attribute for sink representation under PMU directory.
236  * @def_sink:	cached reference to default sink found for this device.
237  * @nr_links:   number of sysfs links created to other components from this
238  *		device. These will appear in the "connections" group.
239  * @has_conns_grp: Have added a "connections" group for sysfs links.
240  * @feature_csdev_list: List of complex feature programming added to the device.
241  * @config_csdev_list:  List of system configurations added to the device.
242  * @cscfg_csdev_lock:	Protect the lists of configurations and features.
243  * @active_cscfg_ctxt:  Context information for current active system configuration.
244  */
245 struct coresight_device {
246 	struct coresight_platform_data *pdata;
247 	enum coresight_dev_type type;
248 	union coresight_dev_subtype subtype;
249 	const struct coresight_ops *ops;
250 	struct csdev_access access;
251 	struct device dev;
252 	atomic_t refcnt;
253 	bool orphan;
254 	bool enable;	/* true only if configured as part of a path */
255 	/* sink specific fields */
256 	bool activated;	/* true only if a sink is part of a path */
257 	struct dev_ext_attribute *ea;
258 	struct coresight_device *def_sink;
259 	/* sysfs links between components */
260 	int nr_links;
261 	bool has_conns_grp;
262 	/* system configuration and feature lists */
263 	struct list_head feature_csdev_list;
264 	struct list_head config_csdev_list;
265 	spinlock_t cscfg_csdev_lock;
266 	void *active_cscfg_ctxt;
267 };
268 
269 /*
270  * coresight_dev_list - Mapping for devices to "name" index for device
271  * names.
272  *
273  * @nr_idx:		Number of entries already allocated.
274  * @pfx:		Prefix pattern for device name.
275  * @fwnode_list:	Array of fwnode_handles associated with each allocated
276  *			index, upto nr_idx entries.
277  */
278 struct coresight_dev_list {
279 	int			nr_idx;
280 	const char		*pfx;
281 	struct fwnode_handle	**fwnode_list;
282 };
283 
284 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx)				\
285 static struct coresight_dev_list (var) = {				\
286 						.pfx = dev_pfx,		\
287 						.nr_idx = 0,		\
288 						.fwnode_list = NULL,	\
289 }
290 
291 #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
292 
293 enum cs_mode {
294 	CS_MODE_DISABLED,
295 	CS_MODE_SYSFS,
296 	CS_MODE_PERF,
297 };
298 
299 #define source_ops(csdev)	csdev->ops->source_ops
300 #define sink_ops(csdev)		csdev->ops->sink_ops
301 #define link_ops(csdev)		csdev->ops->link_ops
302 #define helper_ops(csdev)	csdev->ops->helper_ops
303 #define ect_ops(csdev)		csdev->ops->ect_ops
304 
305 /**
306  * struct coresight_ops_sink - basic operations for a sink
307  * Operations available for sinks
308  * @enable:		enables the sink.
309  * @disable:		disables the sink.
310  * @alloc_buffer:	initialises perf's ring buffer for trace collection.
311  * @free_buffer:	release memory allocated in @get_config.
312  * @update_buffer:	update buffer pointers after a trace session.
313  */
314 struct coresight_ops_sink {
315 	int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
316 		      void *data);
317 	int (*disable)(struct coresight_device *csdev);
318 	void *(*alloc_buffer)(struct coresight_device *csdev,
319 			      struct perf_event *event, void **pages,
320 			      int nr_pages, bool overwrite);
321 	void (*free_buffer)(void *config);
322 	unsigned long (*update_buffer)(struct coresight_device *csdev,
323 			      struct perf_output_handle *handle,
324 			      void *sink_config);
325 };
326 
327 /**
328  * struct coresight_ops_link - basic operations for a link
329  * Operations available for links.
330  * @enable:	enables flow between iport and oport.
331  * @disable:	disables flow between iport and oport.
332  */
333 struct coresight_ops_link {
334 	int (*enable)(struct coresight_device *csdev,
335 		      struct coresight_connection *in,
336 		      struct coresight_connection *out);
337 	void (*disable)(struct coresight_device *csdev,
338 			struct coresight_connection *in,
339 			struct coresight_connection *out);
340 };
341 
342 /**
343  * struct coresight_ops_source - basic operations for a source
344  * Operations available for sources.
345  * @cpu_id:	returns the value of the CPU number this component
346  *		is associated to.
347  * @enable:	enables tracing for a source.
348  * @disable:	disables tracing for a source.
349  */
350 struct coresight_ops_source {
351 	int (*cpu_id)(struct coresight_device *csdev);
352 	int (*enable)(struct coresight_device *csdev, struct perf_event *event,
353 		      enum cs_mode mode);
354 	void (*disable)(struct coresight_device *csdev,
355 			struct perf_event *event);
356 };
357 
358 /**
359  * struct coresight_ops_helper - Operations for a helper device.
360  *
361  * All operations could pass in a device specific data, which could
362  * help the helper device to determine what to do.
363  *
364  * @enable	: Enable the device
365  * @disable	: Disable the device
366  */
367 struct coresight_ops_helper {
368 	int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
369 		      void *data);
370 	int (*disable)(struct coresight_device *csdev, void *data);
371 };
372 
373 struct coresight_ops {
374 	const struct coresight_ops_sink *sink_ops;
375 	const struct coresight_ops_link *link_ops;
376 	const struct coresight_ops_source *source_ops;
377 	const struct coresight_ops_helper *helper_ops;
378 };
379 
380 #if IS_ENABLED(CONFIG_CORESIGHT)
381 
csdev_access_relaxed_read32(struct csdev_access * csa,u32 offset)382 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
383 					      u32 offset)
384 {
385 	if (likely(csa->io_mem))
386 		return readl_relaxed(csa->base + offset);
387 
388 	return csa->read(offset, true, false);
389 }
390 
391 #define CORESIGHT_CIDRn(i)	(0xFF0 + ((i) * 4))
392 
coresight_get_cid(void __iomem * base)393 static inline u32 coresight_get_cid(void __iomem *base)
394 {
395 	u32 i, cid = 0;
396 
397 	for (i = 0; i < 4; i++)
398 		cid |= readl(base + CORESIGHT_CIDRn(i)) << (i * 8);
399 
400 	return cid;
401 }
402 
is_coresight_device(void __iomem * base)403 static inline bool is_coresight_device(void __iomem *base)
404 {
405 	u32 cid = coresight_get_cid(base);
406 
407 	return cid == CORESIGHT_CID;
408 }
409 
410 /*
411  * Attempt to find and enable "APB clock" for the given device
412  *
413  * Returns:
414  *
415  * clk   - Clock is found and enabled
416  * NULL  - clock is not found
417  * ERROR - Clock is found but failed to enable
418  */
coresight_get_enable_apb_pclk(struct device * dev)419 static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev)
420 {
421 	struct clk *pclk;
422 	int ret;
423 
424 	pclk = clk_get(dev, "apb_pclk");
425 	if (IS_ERR(pclk))
426 		return NULL;
427 
428 	ret = clk_prepare_enable(pclk);
429 	if (ret) {
430 		clk_put(pclk);
431 		return ERR_PTR(ret);
432 	}
433 	return pclk;
434 }
435 
436 #define CORESIGHT_PIDRn(i)	(0xFE0 + ((i) * 4))
437 
coresight_get_pid(struct csdev_access * csa)438 static inline u32 coresight_get_pid(struct csdev_access *csa)
439 {
440 	u32 i, pid = 0;
441 
442 	for (i = 0; i < 4; i++)
443 		pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8);
444 
445 	return pid;
446 }
447 
csdev_access_relaxed_read_pair(struct csdev_access * csa,u32 lo_offset,u32 hi_offset)448 static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa,
449 						 u32 lo_offset, u32 hi_offset)
450 {
451 	if (likely(csa->io_mem)) {
452 		return readl_relaxed(csa->base + lo_offset) |
453 			((u64)readl_relaxed(csa->base + hi_offset) << 32);
454 	}
455 
456 	return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32);
457 }
458 
csdev_access_relaxed_write_pair(struct csdev_access * csa,u64 val,u32 lo_offset,u32 hi_offset)459 static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val,
460 						   u32 lo_offset, u32 hi_offset)
461 {
462 	if (likely(csa->io_mem)) {
463 		writel_relaxed((u32)val, csa->base + lo_offset);
464 		writel_relaxed((u32)(val >> 32), csa->base + hi_offset);
465 	} else {
466 		csa->write((u32)val, lo_offset, true, false);
467 		csa->write((u32)(val >> 32), hi_offset, true, false);
468 	}
469 }
470 
csdev_access_read32(struct csdev_access * csa,u32 offset)471 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
472 {
473 	if (likely(csa->io_mem))
474 		return readl(csa->base + offset);
475 
476 	return csa->read(offset, false, false);
477 }
478 
csdev_access_relaxed_write32(struct csdev_access * csa,u32 val,u32 offset)479 static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
480 						u32 val, u32 offset)
481 {
482 	if (likely(csa->io_mem))
483 		writel_relaxed(val, csa->base + offset);
484 	else
485 		csa->write(val, offset, true, false);
486 }
487 
csdev_access_write32(struct csdev_access * csa,u32 val,u32 offset)488 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
489 {
490 	if (likely(csa->io_mem))
491 		writel(val, csa->base + offset);
492 	else
493 		csa->write(val, offset, false, false);
494 }
495 
496 #ifdef CONFIG_64BIT
497 
csdev_access_relaxed_read64(struct csdev_access * csa,u32 offset)498 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
499 					      u32 offset)
500 {
501 	if (likely(csa->io_mem))
502 		return readq_relaxed(csa->base + offset);
503 
504 	return csa->read(offset, true, true);
505 }
506 
csdev_access_read64(struct csdev_access * csa,u32 offset)507 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
508 {
509 	if (likely(csa->io_mem))
510 		return readq(csa->base + offset);
511 
512 	return csa->read(offset, false, true);
513 }
514 
csdev_access_relaxed_write64(struct csdev_access * csa,u64 val,u32 offset)515 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
516 						u64 val, u32 offset)
517 {
518 	if (likely(csa->io_mem))
519 		writeq_relaxed(val, csa->base + offset);
520 	else
521 		csa->write(val, offset, true, true);
522 }
523 
csdev_access_write64(struct csdev_access * csa,u64 val,u32 offset)524 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
525 {
526 	if (likely(csa->io_mem))
527 		writeq(val, csa->base + offset);
528 	else
529 		csa->write(val, offset, false, true);
530 }
531 
532 #else	/* !CONFIG_64BIT */
533 
csdev_access_relaxed_read64(struct csdev_access * csa,u32 offset)534 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
535 					      u32 offset)
536 {
537 	WARN_ON(1);
538 	return 0;
539 }
540 
csdev_access_read64(struct csdev_access * csa,u32 offset)541 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
542 {
543 	WARN_ON(1);
544 	return 0;
545 }
546 
csdev_access_relaxed_write64(struct csdev_access * csa,u64 val,u32 offset)547 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
548 						u64 val, u32 offset)
549 {
550 	WARN_ON(1);
551 }
552 
csdev_access_write64(struct csdev_access * csa,u64 val,u32 offset)553 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
554 {
555 	WARN_ON(1);
556 }
557 #endif	/* CONFIG_64BIT */
558 
coresight_is_percpu_source(struct coresight_device * csdev)559 static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
560 {
561 	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
562 	       (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
563 }
564 
coresight_is_percpu_sink(struct coresight_device * csdev)565 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
566 {
567 	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
568 	       (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
569 }
570 
571 extern struct coresight_device *
572 coresight_register(struct coresight_desc *desc);
573 extern void coresight_unregister(struct coresight_device *csdev);
574 extern int coresight_enable(struct coresight_device *csdev);
575 extern void coresight_disable(struct coresight_device *csdev);
576 extern int coresight_timeout(struct csdev_access *csa, u32 offset,
577 			     int position, int value);
578 
579 extern int coresight_claim_device(struct coresight_device *csdev);
580 extern int coresight_claim_device_unlocked(struct coresight_device *csdev);
581 
582 extern void coresight_disclaim_device(struct coresight_device *csdev);
583 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
584 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
585 					 struct device *dev);
586 
587 extern bool coresight_loses_context_with_cpu(struct device *dev);
588 
589 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
590 u32 coresight_read32(struct coresight_device *csdev, u32 offset);
591 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
592 void coresight_relaxed_write32(struct coresight_device *csdev,
593 			       u32 val, u32 offset);
594 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
595 u64 coresight_read64(struct coresight_device *csdev, u32 offset);
596 void coresight_relaxed_write64(struct coresight_device *csdev,
597 			       u64 val, u32 offset);
598 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
599 
600 #else
601 static inline struct coresight_device *
coresight_register(struct coresight_desc * desc)602 coresight_register(struct coresight_desc *desc) { return NULL; }
coresight_unregister(struct coresight_device * csdev)603 static inline void coresight_unregister(struct coresight_device *csdev) {}
604 static inline int
coresight_enable(struct coresight_device * csdev)605 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
coresight_disable(struct coresight_device * csdev)606 static inline void coresight_disable(struct coresight_device *csdev) {}
607 
coresight_timeout(struct csdev_access * csa,u32 offset,int position,int value)608 static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
609 				    int position, int value)
610 {
611 	return 1;
612 }
613 
coresight_claim_device_unlocked(struct coresight_device * csdev)614 static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
615 {
616 	return -EINVAL;
617 }
618 
coresight_claim_device(struct coresight_device * csdev)619 static inline int coresight_claim_device(struct coresight_device *csdev)
620 {
621 	return -EINVAL;
622 }
623 
coresight_disclaim_device(struct coresight_device * csdev)624 static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
coresight_disclaim_device_unlocked(struct coresight_device * csdev)625 static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}
626 
coresight_loses_context_with_cpu(struct device * dev)627 static inline bool coresight_loses_context_with_cpu(struct device *dev)
628 {
629 	return false;
630 }
631 
coresight_relaxed_read32(struct coresight_device * csdev,u32 offset)632 static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
633 {
634 	WARN_ON_ONCE(1);
635 	return 0;
636 }
637 
coresight_read32(struct coresight_device * csdev,u32 offset)638 static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
639 {
640 	WARN_ON_ONCE(1);
641 	return 0;
642 }
643 
coresight_write32(struct coresight_device * csdev,u32 val,u32 offset)644 static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
645 {
646 }
647 
coresight_relaxed_write32(struct coresight_device * csdev,u32 val,u32 offset)648 static inline void coresight_relaxed_write32(struct coresight_device *csdev,
649 					     u32 val, u32 offset)
650 {
651 }
652 
coresight_relaxed_read64(struct coresight_device * csdev,u32 offset)653 static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
654 					   u32 offset)
655 {
656 	WARN_ON_ONCE(1);
657 	return 0;
658 }
659 
coresight_read64(struct coresight_device * csdev,u32 offset)660 static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
661 {
662 	WARN_ON_ONCE(1);
663 	return 0;
664 }
665 
coresight_relaxed_write64(struct coresight_device * csdev,u64 val,u32 offset)666 static inline void coresight_relaxed_write64(struct coresight_device *csdev,
667 					     u64 val, u32 offset)
668 {
669 }
670 
coresight_write64(struct coresight_device * csdev,u64 val,u32 offset)671 static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
672 {
673 }
674 
675 #endif		/* IS_ENABLED(CONFIG_CORESIGHT) */
676 
677 extern int coresight_get_cpu(struct device *dev);
678 
679 struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
680 struct coresight_connection *
681 coresight_add_out_conn(struct device *dev,
682 		       struct coresight_platform_data *pdata,
683 		       const struct coresight_connection *new_conn);
684 int coresight_add_in_conn(struct coresight_connection *conn);
685 struct coresight_device *
686 coresight_find_input_type(struct coresight_platform_data *pdata,
687 			  enum coresight_dev_type type,
688 			  union coresight_dev_subtype subtype);
689 struct coresight_device *
690 coresight_find_output_type(struct coresight_platform_data *pdata,
691 			   enum coresight_dev_type type,
692 			   union coresight_dev_subtype subtype);
693 
694 #endif		/* _LINUX_COREISGHT_H */
695