1#
2# DMA engine configuration
3#
4
5menuconfig DMADEVICES
6	bool "DMA Engine support"
7	depends on HAS_DMA
8	help
9	  DMA engines can do asynchronous data transfers without
10	  involving the host CPU.  Currently, this framework can be
11	  used to offload memory copies in the network stack and
12	  RAID operations in the MD driver.  This menu only presents
13	  DMA Device drivers supported by the configured arch, it may
14	  be empty in some cases.
15
16config DMADEVICES_DEBUG
17        bool "DMA Engine debugging"
18        depends on DMADEVICES != n
19        help
20          This is an option for use by developers; most people should
21          say N here.  This enables DMA engine core and driver debugging.
22
23config DMADEVICES_VDEBUG
24        bool "DMA Engine verbose debugging"
25        depends on DMADEVICES_DEBUG != n
26        help
27          This is an option for use by developers; most people should
28          say N here.  This enables deeper (more verbose) debugging of
29          the DMA engine core and drivers.
30
31
32if DMADEVICES
33
34comment "DMA Devices"
35
36config INTEL_MID_DMAC
37	tristate "Intel MID DMA support for Peripheral DMA controllers"
38	depends on PCI && X86
39	select DMA_ENGINE
40	default n
41	help
42	  Enable support for the Intel(R) MID DMA engine present
43	  in Intel MID chipsets.
44
45	  Say Y here if you have such a chipset.
46
47	  If unsure, say N.
48
49config ASYNC_TX_ENABLE_CHANNEL_SWITCH
50	bool
51
52config AMBA_PL08X
53	bool "ARM PrimeCell PL080 or PL081 support"
54	depends on ARM_AMBA && EXPERIMENTAL
55	select DMA_ENGINE
56	help
57	  Platform has a PL08x DMAC device
58	  which can provide DMA engine support
59
60config INTEL_IOATDMA
61	tristate "Intel I/OAT DMA support"
62	depends on PCI && X86
63	select DMA_ENGINE
64	select DCA
65	select ASYNC_TX_DISABLE_PQ_VAL_DMA
66	select ASYNC_TX_DISABLE_XOR_VAL_DMA
67	help
68	  Enable support for the Intel(R) I/OAT DMA engine present
69	  in recent Intel Xeon chipsets.
70
71	  Say Y here if you have such a chipset.
72
73	  If unsure, say N.
74
75config INTEL_IOP_ADMA
76	tristate "Intel IOP ADMA support"
77	depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
78	select DMA_ENGINE
79	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
80	help
81	  Enable support for the Intel(R) IOP Series RAID engines.
82
83config DW_DMAC
84	tristate "Synopsys DesignWare AHB DMA support"
85	depends on HAVE_CLK
86	select DMA_ENGINE
87	default y if CPU_AT32AP7000
88	help
89	  Support the Synopsys DesignWare AHB DMA controller.  This
90	  can be integrated in chips such as the Atmel AT32ap7000.
91
92config AT_HDMAC
93	tristate "Atmel AHB DMA support"
94	depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
95	select DMA_ENGINE
96	help
97	  Support the Atmel AHB DMA controller.  This can be integrated in
98	  chips such as the Atmel AT91SAM9RL.
99
100config FSL_DMA
101	tristate "Freescale Elo and Elo Plus DMA support"
102	depends on FSL_SOC
103	select DMA_ENGINE
104	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
105	---help---
106	  Enable support for the Freescale Elo and Elo Plus DMA controllers.
107	  The Elo is the DMA controller on some 82xx and 83xx parts, and the
108	  Elo Plus is the DMA controller on 85xx and 86xx parts.
109
110config MPC512X_DMA
111	tristate "Freescale MPC512x built-in DMA engine support"
112	depends on PPC_MPC512x || PPC_MPC831x
113	select DMA_ENGINE
114	---help---
115	  Enable support for the Freescale MPC512x built-in DMA engine.
116
117config MV_XOR
118	bool "Marvell XOR engine support"
119	depends on PLAT_ORION
120	select DMA_ENGINE
121	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
122	---help---
123	  Enable support for the Marvell XOR engine.
124
125config MX3_IPU
126	bool "MX3x Image Processing Unit support"
127	depends on ARCH_MX3
128	select DMA_ENGINE
129	default y
130	help
131	  If you plan to use the Image Processing unit in the i.MX3x, say
132	  Y here. If unsure, select Y.
133
134config MX3_IPU_IRQS
135	int "Number of dynamically mapped interrupts for IPU"
136	depends on MX3_IPU
137	range 2 137
138	default 4
139	help
140	  Out of 137 interrupt sources on i.MX31 IPU only very few are used.
141	  To avoid bloating the irq_desc[] array we allocate a sufficient
142	  number of IRQ slots and map them dynamically to specific sources.
143
144config TXX9_DMAC
145	tristate "Toshiba TXx9 SoC DMA support"
146	depends on MACH_TX49XX || MACH_TX39XX
147	select DMA_ENGINE
148	help
149	  Support the TXx9 SoC internal DMA controller.  This can be
150	  integrated in chips such as the Toshiba TX4927/38/39.
151
152config SH_DMAE
153	tristate "Renesas SuperH DMAC support"
154	depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
155	depends on !SH_DMA_API
156	select DMA_ENGINE
157	help
158	  Enable support for the Renesas SuperH DMA controllers.
159
160config COH901318
161	bool "ST-Ericsson COH901318 DMA support"
162	select DMA_ENGINE
163	depends on ARCH_U300
164	help
165	  Enable support for ST-Ericsson COH 901 318 DMA.
166
167config STE_DMA40
168	bool "ST-Ericsson DMA40 support"
169	depends on ARCH_U8500
170	select DMA_ENGINE
171	help
172	  Support for ST-Ericsson DMA40 controller
173
174config AMCC_PPC440SPE_ADMA
175	tristate "AMCC PPC440SPe ADMA support"
176	depends on 440SPe || 440SP
177	select DMA_ENGINE
178	select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
179	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
180	help
181	  Enable support for the AMCC PPC440SPe RAID engines.
182
183config TIMB_DMA
184	tristate "Timberdale FPGA DMA support"
185	depends on MFD_TIMBERDALE || HAS_IOMEM
186	select DMA_ENGINE
187	help
188	  Enable support for the Timberdale FPGA DMA engine.
189
190config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
191	bool
192
193config PL330_DMA
194	tristate "DMA API Driver for PL330"
195	select DMA_ENGINE
196	depends on PL330
197	help
198	  Select if your platform has one or more PL330 DMACs.
199	  You need to provide platform specific settings via
200	  platform_data for a dma-pl330 device.
201
202config PCH_DMA
203	tristate "Intel EG20T PCH / OKI SEMICONDUCTOR ML7213 IOH DMA support"
204	depends on PCI && X86
205	select DMA_ENGINE
206	help
207	  Enable support for Intel EG20T PCH DMA engine.
208
209	  This driver also can be used for OKI SEMICONDUCTOR ML7213 IOH(Input/
210	  Output Hub) which is for IVI(In-Vehicle Infotainment) use.
211	  ML7213 is companion chip for Intel Atom E6xx series.
212	  ML7213 is completely compatible for Intel EG20T PCH.
213
214config IMX_SDMA
215	tristate "i.MX SDMA support"
216	depends on ARCH_MX25 || ARCH_MX3 || ARCH_MX5
217	select DMA_ENGINE
218	help
219	  Support the i.MX SDMA engine. This engine is integrated into
220	  Freescale i.MX25/31/35/51 chips.
221
222config IMX_DMA
223	tristate "i.MX DMA support"
224	depends on IMX_HAVE_DMA_V1
225	select DMA_ENGINE
226	help
227	  Support the i.MX DMA engine. This engine is integrated into
228	  Freescale i.MX1/21/27 chips.
229
230config MXS_DMA
231	bool "MXS DMA support"
232	depends on SOC_IMX23 || SOC_IMX28
233	select DMA_ENGINE
234	help
235	  Support the MXS DMA engine. This engine including APBH-DMA
236	  and APBX-DMA is integrated into Freescale i.MX23/28 chips.
237
238config DMA_ENGINE
239	bool
240
241comment "DMA Clients"
242	depends on DMA_ENGINE
243
244config NET_DMA
245	bool "Network: TCP receive copy offload"
246	depends on DMA_ENGINE && NET
247	default (INTEL_IOATDMA || FSL_DMA)
248	help
249	  This enables the use of DMA engines in the network stack to
250	  offload receive copy-to-user operations, freeing CPU cycles.
251
252	  Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
253	  say N.
254
255config ASYNC_TX_DMA
256	bool "Async_tx: Offload support for the async_tx api"
257	depends on DMA_ENGINE
258	help
259	  This allows the async_tx api to take advantage of offload engines for
260	  memcpy, memset, xor, and raid6 p+q operations.  If your platform has
261	  a dma engine that can perform raid operations and you have enabled
262	  MD_RAID456 say Y.
263
264	  If unsure, say N.
265
266config DMATEST
267	tristate "DMA Test client"
268	depends on DMA_ENGINE
269	help
270	  Simple DMA test client. Say N unless you're debugging a
271	  DMA Device driver.
272
273endif
274