1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on OF_IRQ 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 12 13config ARM_GIC_PM 14 bool 15 depends on PM 16 select ARM_GIC 17 18config ARM_GIC_MAX_NR 19 int 20 depends on ARM_GIC 21 default 2 if ARCH_REALVIEW 22 default 1 23 24config ARM_GIC_V2M 25 bool 26 depends on PCI 27 select ARM_GIC 28 select PCI_MSI 29 30config GIC_NON_BANKED 31 bool 32 33config ARM_GIC_V3 34 bool 35 select IRQ_DOMAIN_HIERARCHY 36 select PARTITION_PERCPU 37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 38 39config ARM_GIC_V3_ITS 40 bool 41 select GENERIC_MSI_IRQ_DOMAIN 42 default ARM_GIC_V3 43 44config ARM_GIC_V3_ITS_PCI 45 bool 46 depends on ARM_GIC_V3_ITS 47 depends on PCI 48 depends on PCI_MSI 49 default ARM_GIC_V3_ITS 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config ARMADA_370_XP_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select PCI_MSI if PCI 79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 80 81config ALPINE_MSI 82 bool 83 depends on PCI 84 select PCI_MSI 85 select GENERIC_IRQ_CHIP 86 87config AL_FIC 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 89 depends on OF || COMPILE_TEST 90 select GENERIC_IRQ_CHIP 91 select IRQ_DOMAIN 92 help 93 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 94 95config ATMEL_AIC_IRQ 96 bool 97 select GENERIC_IRQ_CHIP 98 select IRQ_DOMAIN 99 select SPARSE_IRQ 100 101config ATMEL_AIC5_IRQ 102 bool 103 select GENERIC_IRQ_CHIP 104 select IRQ_DOMAIN 105 select SPARSE_IRQ 106 107config I8259 108 bool 109 select IRQ_DOMAIN 110 111config BCM6345_L1_IRQ 112 bool 113 select GENERIC_IRQ_CHIP 114 select IRQ_DOMAIN 115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 116 117config BCM7038_L1_IRQ 118 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 119 depends on ARCH_BRCMSTB || BMIPS_GENERIC 120 default ARCH_BRCMSTB || BMIPS_GENERIC 121 select GENERIC_IRQ_CHIP 122 select IRQ_DOMAIN 123 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 124 125config BCM7120_L2_IRQ 126 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 127 depends on ARCH_BRCMSTB || BMIPS_GENERIC 128 default ARCH_BRCMSTB || BMIPS_GENERIC 129 select GENERIC_IRQ_CHIP 130 select IRQ_DOMAIN 131 132config BRCMSTB_L2_IRQ 133 tristate "Broadcom STB generic L2 interrupt controller driver" 134 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 135 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 136 select GENERIC_IRQ_CHIP 137 select IRQ_DOMAIN 138 139config DAVINCI_AINTC 140 bool 141 select GENERIC_IRQ_CHIP 142 select IRQ_DOMAIN 143 144config DAVINCI_CP_INTC 145 bool 146 select GENERIC_IRQ_CHIP 147 select IRQ_DOMAIN 148 149config DW_APB_ICTL 150 bool 151 select GENERIC_IRQ_CHIP 152 select IRQ_DOMAIN_HIERARCHY 153 154config FARADAY_FTINTC010 155 bool 156 select IRQ_DOMAIN 157 select SPARSE_IRQ 158 159config HISILICON_IRQ_MBIGEN 160 bool 161 select ARM_GIC_V3 162 select ARM_GIC_V3_ITS 163 164config IMGPDC_IRQ 165 bool 166 select GENERIC_IRQ_CHIP 167 select IRQ_DOMAIN 168 169config IXP4XX_IRQ 170 bool 171 select IRQ_DOMAIN 172 select SPARSE_IRQ 173 174config MADERA_IRQ 175 tristate 176 177config IRQ_MIPS_CPU 178 bool 179 select GENERIC_IRQ_CHIP 180 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 181 select IRQ_DOMAIN 182 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 183 184config CLPS711X_IRQCHIP 185 bool 186 depends on ARCH_CLPS711X 187 select IRQ_DOMAIN 188 select SPARSE_IRQ 189 default y 190 191config OMPIC 192 bool 193 194config OR1K_PIC 195 bool 196 select IRQ_DOMAIN 197 198config OMAP_IRQCHIP 199 bool 200 select GENERIC_IRQ_CHIP 201 select IRQ_DOMAIN 202 203config ORION_IRQCHIP 204 bool 205 select IRQ_DOMAIN 206 207config PIC32_EVIC 208 bool 209 select GENERIC_IRQ_CHIP 210 select IRQ_DOMAIN 211 212config JCORE_AIC 213 bool "J-Core integrated AIC" if COMPILE_TEST 214 depends on OF 215 select IRQ_DOMAIN 216 help 217 Support for the J-Core integrated AIC. 218 219config RDA_INTC 220 bool 221 select IRQ_DOMAIN 222 223config RENESAS_INTC_IRQPIN 224 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 225 select IRQ_DOMAIN 226 help 227 Enable support for the Renesas Interrupt Controller for external 228 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 229 230config RENESAS_IRQC 231 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 232 select GENERIC_IRQ_CHIP 233 select IRQ_DOMAIN 234 help 235 Enable support for the Renesas Interrupt Controller for external 236 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 237 238config RENESAS_RZA1_IRQC 239 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 240 select IRQ_DOMAIN_HIERARCHY 241 help 242 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 243 to 8 external interrupts with configurable sense select. 244 245config SL28CPLD_INTC 246 bool "Kontron sl28cpld IRQ controller" 247 depends on MFD_SL28CPLD=y || COMPILE_TEST 248 select REGMAP_IRQ 249 help 250 Interrupt controller driver for the board management controller 251 found on the Kontron sl28 CPLD. 252 253config ST_IRQCHIP 254 bool 255 select REGMAP 256 select MFD_SYSCON 257 help 258 Enables SysCfg Controlled IRQs on STi based platforms. 259 260config SUN4I_INTC 261 bool 262 263config SUN6I_R_INTC 264 bool 265 select IRQ_DOMAIN_HIERARCHY 266 select IRQ_FASTEOI_HIERARCHY_HANDLERS 267 268config SUNXI_NMI_INTC 269 bool 270 select GENERIC_IRQ_CHIP 271 272config TB10X_IRQC 273 bool 274 select IRQ_DOMAIN 275 select GENERIC_IRQ_CHIP 276 277config TS4800_IRQ 278 tristate "TS-4800 IRQ controller" 279 select IRQ_DOMAIN 280 depends on HAS_IOMEM 281 depends on SOC_IMX51 || COMPILE_TEST 282 help 283 Support for the TS-4800 FPGA IRQ controller 284 285config VERSATILE_FPGA_IRQ 286 bool 287 select IRQ_DOMAIN 288 289config VERSATILE_FPGA_IRQ_NR 290 int 291 default 4 292 depends on VERSATILE_FPGA_IRQ 293 294config XTENSA_MX 295 bool 296 select IRQ_DOMAIN 297 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 298 299config XILINX_INTC 300 bool "Xilinx Interrupt Controller IP" 301 depends on OF_ADDRESS 302 select IRQ_DOMAIN 303 help 304 Support for the Xilinx Interrupt Controller IP core. 305 This is used as a primary controller with MicroBlaze and can also 306 be used as a secondary chained controller on other platforms. 307 308config IRQ_CROSSBAR 309 bool 310 help 311 Support for a CROSSBAR ip that precedes the main interrupt controller. 312 The primary irqchip invokes the crossbar's callback which inturn allocates 313 a free irq and configures the IP. Thus the peripheral interrupts are 314 routed to one of the free irqchip interrupt lines. 315 316config KEYSTONE_IRQ 317 tristate "Keystone 2 IRQ controller IP" 318 depends on ARCH_KEYSTONE 319 help 320 Support for Texas Instruments Keystone 2 IRQ controller IP which 321 is part of the Keystone 2 IPC mechanism 322 323config MIPS_GIC 324 bool 325 select GENERIC_IRQ_IPI if SMP 326 select IRQ_DOMAIN_HIERARCHY 327 select MIPS_CM 328 329config INGENIC_IRQ 330 bool 331 depends on MACH_INGENIC 332 default y 333 334config INGENIC_TCU_IRQ 335 bool "Ingenic JZ47xx TCU interrupt controller" 336 default MACH_INGENIC 337 depends on MIPS || COMPILE_TEST 338 select MFD_SYSCON 339 select GENERIC_IRQ_CHIP 340 help 341 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 342 JZ47xx SoCs. 343 344 If unsure, say N. 345 346config IMX_GPCV2 347 bool 348 select IRQ_DOMAIN 349 help 350 Enables the wakeup IRQs for IMX platforms with GPCv2 block 351 352config IRQ_MXS 353 def_bool y if MACH_ASM9260 || ARCH_MXS 354 select IRQ_DOMAIN 355 select STMP_DEVICE 356 357config MSCC_OCELOT_IRQ 358 bool 359 select IRQ_DOMAIN 360 select GENERIC_IRQ_CHIP 361 362config MVEBU_GICP 363 bool 364 365config MVEBU_ICU 366 bool 367 368config MVEBU_ODMI 369 bool 370 select GENERIC_MSI_IRQ_DOMAIN 371 372config MVEBU_PIC 373 bool 374 375config MVEBU_SEI 376 bool 377 378config LS_EXTIRQ 379 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 380 select MFD_SYSCON 381 382config LS_SCFG_MSI 383 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 384 depends on PCI && PCI_MSI 385 386config PARTITION_PERCPU 387 bool 388 389config STM32_EXTI 390 bool 391 select IRQ_DOMAIN 392 select GENERIC_IRQ_CHIP 393 394config QCOM_IRQ_COMBINER 395 bool "QCOM IRQ combiner support" 396 depends on ARCH_QCOM && ACPI 397 select IRQ_DOMAIN_HIERARCHY 398 help 399 Say yes here to add support for the IRQ combiner devices embedded 400 in Qualcomm Technologies chips. 401 402config IRQ_UNIPHIER_AIDET 403 bool "UniPhier AIDET support" if COMPILE_TEST 404 depends on ARCH_UNIPHIER || COMPILE_TEST 405 default ARCH_UNIPHIER 406 select IRQ_DOMAIN_HIERARCHY 407 help 408 Support for the UniPhier AIDET (ARM Interrupt Detector). 409 410config MESON_IRQ_GPIO 411 tristate "Meson GPIO Interrupt Multiplexer" 412 depends on ARCH_MESON || COMPILE_TEST 413 default ARCH_MESON 414 select IRQ_DOMAIN_HIERARCHY 415 help 416 Support Meson SoC Family GPIO Interrupt Multiplexer 417 418config GOLDFISH_PIC 419 bool "Goldfish programmable interrupt controller" 420 depends on MIPS && (GOLDFISH || COMPILE_TEST) 421 select GENERIC_IRQ_CHIP 422 select IRQ_DOMAIN 423 help 424 Say yes here to enable Goldfish interrupt controller driver used 425 for Goldfish based virtual platforms. 426 427config QCOM_PDC 428 tristate "QCOM PDC" 429 depends on ARCH_QCOM 430 select IRQ_DOMAIN_HIERARCHY 431 help 432 Power Domain Controller driver to manage and configure wakeup 433 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 434 435config QCOM_MPM 436 tristate "QCOM MPM" 437 depends on ARCH_QCOM 438 depends on MAILBOX 439 select IRQ_DOMAIN_HIERARCHY 440 help 441 MSM Power Manager driver to manage and configure wakeup 442 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 443 444config CSKY_MPINTC 445 bool 446 depends on CSKY 447 help 448 Say yes here to enable C-SKY SMP interrupt controller driver used 449 for C-SKY SMP system. 450 In fact it's not mmio map in hardware and it uses ld/st to visit the 451 controller's register inside CPU. 452 453config CSKY_APB_INTC 454 bool "C-SKY APB Interrupt Controller" 455 depends on CSKY 456 help 457 Say yes here to enable C-SKY APB interrupt controller driver used 458 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 459 the controller's register. 460 461config IMX_IRQSTEER 462 bool "i.MX IRQSTEER support" 463 depends on ARCH_MXC || COMPILE_TEST 464 default ARCH_MXC 465 select IRQ_DOMAIN 466 help 467 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 468 469config IMX_INTMUX 470 bool "i.MX INTMUX support" if COMPILE_TEST 471 default y if ARCH_MXC 472 select IRQ_DOMAIN 473 help 474 Support for the i.MX INTMUX interrupt multiplexer. 475 476config LS1X_IRQ 477 bool "Loongson-1 Interrupt Controller" 478 depends on MACH_LOONGSON32 479 default y 480 select IRQ_DOMAIN 481 select GENERIC_IRQ_CHIP 482 help 483 Support for the Loongson-1 platform Interrupt Controller. 484 485config TI_SCI_INTR_IRQCHIP 486 bool 487 depends on TI_SCI_PROTOCOL 488 select IRQ_DOMAIN_HIERARCHY 489 help 490 This enables the irqchip driver support for K3 Interrupt router 491 over TI System Control Interface available on some new TI's SoCs. 492 If you wish to use interrupt router irq resources managed by the 493 TI System Controller, say Y here. Otherwise, say N. 494 495config TI_SCI_INTA_IRQCHIP 496 bool 497 depends on TI_SCI_PROTOCOL 498 select IRQ_DOMAIN_HIERARCHY 499 select TI_SCI_INTA_MSI_DOMAIN 500 help 501 This enables the irqchip driver support for K3 Interrupt aggregator 502 over TI System Control Interface available on some new TI's SoCs. 503 If you wish to use interrupt aggregator irq resources managed by the 504 TI System Controller, say Y here. Otherwise, say N. 505 506config TI_PRUSS_INTC 507 tristate 508 depends on TI_PRUSS 509 default TI_PRUSS 510 select IRQ_DOMAIN 511 help 512 This enables support for the PRU-ICSS Local Interrupt Controller 513 present within a PRU-ICSS subsystem present on various TI SoCs. 514 The PRUSS INTC enables various interrupts to be routed to multiple 515 different processors within the SoC. 516 517config RISCV_INTC 518 bool "RISC-V Local Interrupt Controller" 519 depends on RISCV 520 default y 521 help 522 This enables support for the per-HART local interrupt controller 523 found in standard RISC-V systems. The per-HART local interrupt 524 controller handles timer interrupts, software interrupts, and 525 hardware interrupts. Without a per-HART local interrupt controller, 526 a RISC-V system will be unable to handle any interrupts. 527 528 If you don't know what to do here, say Y. 529 530config SIFIVE_PLIC 531 bool "SiFive Platform-Level Interrupt Controller" 532 depends on RISCV 533 select IRQ_DOMAIN_HIERARCHY 534 help 535 This enables support for the PLIC chip found in SiFive (and 536 potentially other) RISC-V systems. The PLIC controls devices 537 interrupts and connects them to each core's local interrupt 538 controller. Aside from timer and software interrupts, all other 539 interrupt sources are subordinate to the PLIC. 540 541 If you don't know what to do here, say Y. 542 543config EXYNOS_IRQ_COMBINER 544 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 545 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 546 help 547 Say yes here to add support for the IRQ combiner devices embedded 548 in Samsung Exynos chips. 549 550config LOONGSON_LIOINTC 551 bool "Loongson Local I/O Interrupt Controller" 552 depends on MACH_LOONGSON64 553 default y 554 select IRQ_DOMAIN 555 select GENERIC_IRQ_CHIP 556 help 557 Support for the Loongson Local I/O Interrupt Controller. 558 559config LOONGSON_HTPIC 560 bool "Loongson3 HyperTransport PIC Controller" 561 depends on MACH_LOONGSON64 && MIPS 562 default y 563 select IRQ_DOMAIN 564 select GENERIC_IRQ_CHIP 565 help 566 Support for the Loongson-3 HyperTransport PIC Controller. 567 568config LOONGSON_HTVEC 569 bool "Loongson HyperTransport Interrupt Vector Controller" 570 depends on MACH_LOONGSON64 571 default MACH_LOONGSON64 572 select IRQ_DOMAIN_HIERARCHY 573 help 574 Support for the Loongson HyperTransport Interrupt Vector Controller. 575 576config LOONGSON_PCH_PIC 577 bool "Loongson PCH PIC Controller" 578 depends on MACH_LOONGSON64 || COMPILE_TEST 579 default MACH_LOONGSON64 580 select IRQ_DOMAIN_HIERARCHY 581 select IRQ_FASTEOI_HIERARCHY_HANDLERS 582 help 583 Support for the Loongson PCH PIC Controller. 584 585config LOONGSON_PCH_MSI 586 bool "Loongson PCH MSI Controller" 587 depends on MACH_LOONGSON64 || COMPILE_TEST 588 depends on PCI 589 default MACH_LOONGSON64 590 select IRQ_DOMAIN_HIERARCHY 591 select PCI_MSI 592 help 593 Support for the Loongson PCH MSI Controller. 594 595config MST_IRQ 596 bool "MStar Interrupt Controller" 597 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 598 default ARCH_MEDIATEK 599 select IRQ_DOMAIN 600 select IRQ_DOMAIN_HIERARCHY 601 help 602 Support MStar Interrupt Controller. 603 604config WPCM450_AIC 605 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 606 depends on ARCH_WPCM450 607 help 608 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 609 610config IRQ_IDT3243X 611 bool 612 select GENERIC_IRQ_CHIP 613 select IRQ_DOMAIN 614 615config APPLE_AIC 616 bool "Apple Interrupt Controller (AIC)" 617 depends on ARM64 618 depends on ARCH_APPLE || COMPILE_TEST 619 help 620 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 621 such as the M1. 622 623config MCHP_EIC 624 bool "Microchip External Interrupt Controller" 625 depends on ARCH_AT91 || COMPILE_TEST 626 select IRQ_DOMAIN 627 select IRQ_DOMAIN_HIERARCHY 628 help 629 Support for Microchip External Interrupt Controller. 630 631endmenu 632