1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 23 select ARCH_HAS_SYNC_DMA_FOR_CPU 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 28 select ARCH_HAS_GCOV_PROFILE_ALL 29 select ARCH_KEEP_MEMBLOCK 30 select ARCH_MIGHT_HAVE_PC_PARPORT 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 35 select ARCH_USE_BUILTIN_BSWAP 36 select ARCH_USE_CMPXCHG_LOCKREF 37 select ARCH_USE_MEMTEST 38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 39 select ARCH_WANT_GENERAL_HUGETLB 40 select ARCH_WANT_IPC_PARSE_VERSION 41 select ARCH_WANT_LD_ORPHAN_WARN 42 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 43 select BUILDTIME_TABLE_SORT if MMU 44 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 45 select CLONE_BACKWARDS 46 select CPU_PM if SUSPEND || CPU_IDLE 47 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 48 select DMA_DECLARE_COHERENT 49 select DMA_GLOBAL_POOL if !MMU 50 select DMA_OPS 51 select DMA_NONCOHERENT_MMAP if MMU 52 select EDAC_SUPPORT 53 select EDAC_ATOMIC_SCRUB 54 select GENERIC_ALLOCATOR 55 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 56 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 57 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 58 select GENERIC_IRQ_IPI if SMP 59 select GENERIC_CPU_AUTOPROBE 60 select GENERIC_EARLY_IOREMAP 61 select GENERIC_IDLE_POLL_SETUP 62 select GENERIC_IRQ_MULTI_HANDLER 63 select GENERIC_IRQ_PROBE 64 select GENERIC_IRQ_SHOW 65 select GENERIC_IRQ_SHOW_LEVEL 66 select GENERIC_LIB_DEVMEM_IS_ALLOWED 67 select GENERIC_PCI_IOMAP 68 select GENERIC_SCHED_CLOCK 69 select GENERIC_SMP_IDLE_THREAD 70 select HARDIRQS_SW_RESEND 71 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 72 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 73 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 74 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 75 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 76 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 77 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 78 select HAVE_ARCH_MMAP_RND_BITS if MMU 79 select HAVE_ARCH_PFN_VALID 80 select HAVE_ARCH_SECCOMP 81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 83 select HAVE_ARCH_TRACEHOOK 84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 85 select HAVE_ARM_SMCCC if CPU_V7 86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 87 select HAVE_CONTEXT_TRACKING_USER 88 select HAVE_C_RECORDMCOUNT 89 select HAVE_BUILDTIME_MCOUNT_SORT 90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 91 select HAVE_DMA_CONTIGUOUS if MMU 92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 95 select HAVE_EXIT_THREAD 96 select HAVE_FAST_GUP if ARM_LPAE 97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 98 select HAVE_FUNCTION_GRAPH_TRACER 99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 100 select HAVE_GCC_PLUGINS 101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 102 select HAVE_IRQ_TIME_ACCOUNTING 103 select HAVE_KERNEL_GZIP 104 select HAVE_KERNEL_LZ4 105 select HAVE_KERNEL_LZMA 106 select HAVE_KERNEL_LZO 107 select HAVE_KERNEL_XZ 108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 109 select HAVE_KRETPROBES if HAVE_KPROBES 110 select HAVE_MOD_ARCH_SPECIFIC 111 select HAVE_NMI 112 select HAVE_OPTPROBES if !THUMB2_KERNEL 113 select HAVE_PCI if MMU 114 select HAVE_PERF_EVENTS 115 select HAVE_PERF_REGS 116 select HAVE_PERF_USER_STACK_DUMP 117 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 118 select HAVE_REGS_AND_STACK_ACCESS_API 119 select HAVE_RSEQ 120 select HAVE_STACKPROTECTOR 121 select HAVE_SYSCALL_TRACEPOINTS 122 select HAVE_UID16 123 select HAVE_VIRT_CPU_ACCOUNTING_GEN 124 select IRQ_FORCED_THREADING 125 select MODULES_USE_ELF_REL 126 select NEED_DMA_MAP_STATE 127 select OF_EARLY_FLATTREE if OF 128 select OLD_SIGACTION 129 select OLD_SIGSUSPEND3 130 select PCI_DOMAINS_GENERIC if PCI 131 select PCI_SYSCALL if PCI 132 select PERF_USE_VMALLOC 133 select RTC_LIB 134 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 135 select SYS_SUPPORTS_APM_EMULATION 136 select THREAD_INFO_IN_TASK 137 select TIMER_OF if OF 138 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 139 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 140 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 141 # Above selects are sorted alphabetically; please add new ones 142 # according to that. Thanks. 143 help 144 The ARM series is a line of low-power-consumption RISC chip designs 145 licensed by ARM Ltd and targeted at embedded applications and 146 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 147 manufactured, but legacy ARM-based PC hardware remains popular in 148 Europe. There is an ARM Linux project with a web page at 149 <http://www.arm.linux.org.uk/>. 150 151config ARM_HAS_GROUP_RELOCS 152 def_bool y 153 depends on !LD_IS_LLD || LLD_VERSION >= 140000 154 depends on !COMPILE_TEST 155 help 156 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 157 relocations, which have been around for a long time, but were not 158 supported in LLD until version 14. The combined range is -/+ 256 MiB, 159 which is usually sufficient, but not for allyesconfig, so we disable 160 this feature when doing compile testing. 161 162config ARM_DMA_USE_IOMMU 163 bool 164 select NEED_SG_DMA_LENGTH 165 166if ARM_DMA_USE_IOMMU 167 168config ARM_DMA_IOMMU_ALIGNMENT 169 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 170 range 4 9 171 default 8 172 help 173 DMA mapping framework by default aligns all buffers to the smallest 174 PAGE_SIZE order which is greater than or equal to the requested buffer 175 size. This works well for buffers up to a few hundreds kilobytes, but 176 for larger buffers it just a waste of address space. Drivers which has 177 relatively small addressing window (like 64Mib) might run out of 178 virtual space with just a few allocations. 179 180 With this parameter you can specify the maximum PAGE_SIZE order for 181 DMA IOMMU buffers. Larger buffers will be aligned only to this 182 specified order. The order is expressed as a power of two multiplied 183 by the PAGE_SIZE. 184 185endif 186 187config SYS_SUPPORTS_APM_EMULATION 188 bool 189 190config HAVE_TCM 191 bool 192 select GENERIC_ALLOCATOR 193 194config HAVE_PROC_CPU 195 bool 196 197config NO_IOPORT_MAP 198 bool 199 200config SBUS 201 bool 202 203config STACKTRACE_SUPPORT 204 bool 205 default y 206 207config LOCKDEP_SUPPORT 208 bool 209 default y 210 211config ARCH_HAS_ILOG2_U32 212 bool 213 214config ARCH_HAS_ILOG2_U64 215 bool 216 217config ARCH_HAS_BANDGAP 218 bool 219 220config FIX_EARLYCON_MEM 221 def_bool y if MMU 222 223config GENERIC_HWEIGHT 224 bool 225 default y 226 227config GENERIC_CALIBRATE_DELAY 228 bool 229 default y 230 231config ARCH_MAY_HAVE_PC_FDC 232 bool 233 234config ARCH_SUPPORTS_UPROBES 235 def_bool y 236 237config GENERIC_ISA_DMA 238 bool 239 240config FIQ 241 bool 242 243config ARCH_MTD_XIP 244 bool 245 246config ARM_PATCH_PHYS_VIRT 247 bool "Patch physical to virtual translations at runtime" if EMBEDDED 248 default y 249 depends on MMU 250 help 251 Patch phys-to-virt and virt-to-phys translation functions at 252 boot and module load time according to the position of the 253 kernel in system memory. 254 255 This can only be used with non-XIP MMU kernels where the base 256 of physical memory is at a 2 MiB boundary. 257 258 Only disable this option if you know that you do not require 259 this feature (eg, building a kernel for a single machine) and 260 you need to shrink the kernel to the minimal size. 261 262config NEED_MACH_IO_H 263 bool 264 help 265 Select this when mach/io.h is required to provide special 266 definitions for this platform. The need for mach/io.h should 267 be avoided when possible. 268 269config NEED_MACH_MEMORY_H 270 bool 271 help 272 Select this when mach/memory.h is required to provide special 273 definitions for this platform. The need for mach/memory.h should 274 be avoided when possible. 275 276config PHYS_OFFSET 277 hex "Physical address of main memory" if MMU 278 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 279 default DRAM_BASE if !MMU 280 default 0x00000000 if ARCH_FOOTBRIDGE 281 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 282 default 0x30000000 if ARCH_S3C24XX 283 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 284 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 285 default 0 286 help 287 Please provide the physical address corresponding to the 288 location of main memory in your system. 289 290config GENERIC_BUG 291 def_bool y 292 depends on BUG 293 294config PGTABLE_LEVELS 295 int 296 default 3 if ARM_LPAE 297 default 2 298 299menu "System Type" 300 301config MMU 302 bool "MMU-based Paged Memory Management Support" 303 default y 304 help 305 Select if you want MMU-based virtualised addressing space 306 support by paged memory management. If unsure, say 'Y'. 307 308config ARM_SINGLE_ARMV7M 309 def_bool !MMU 310 select ARM_NVIC 311 select CPU_V7M 312 select NO_IOPORT_MAP 313 314config ARCH_MMAP_RND_BITS_MIN 315 default 8 316 317config ARCH_MMAP_RND_BITS_MAX 318 default 14 if PAGE_OFFSET=0x40000000 319 default 15 if PAGE_OFFSET=0x80000000 320 default 16 321 322config ARCH_MULTIPLATFORM 323 bool "Require kernel to be portable to multiple machines" if EXPERT 324 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 325 default y 326 help 327 In general, all Arm machines can be supported in a single 328 kernel image, covering either Armv4/v5 or Armv6/v7. 329 330 However, some configuration options require hardcoding machine 331 specific physical addresses or enable errata workarounds that may 332 break other machines. 333 334 Selecting N here allows using those options, including 335 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 336 337menu "Platform selection" 338 depends on MMU 339 340comment "CPU Core family selection" 341 342config ARCH_MULTI_V4 343 bool "ARMv4 based platforms (FA526, StrongARM)" 344 depends on !ARCH_MULTI_V6_V7 345 select ARCH_MULTI_V4_V5 346 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) 347 348config ARCH_MULTI_V4T 349 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 350 depends on !ARCH_MULTI_V6_V7 351 select ARCH_MULTI_V4_V5 352 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 353 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 354 CPU_ARM925T || CPU_ARM940T) 355 356config ARCH_MULTI_V5 357 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 358 depends on !ARCH_MULTI_V6_V7 359 select ARCH_MULTI_V4_V5 360 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 361 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 362 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 363 364config ARCH_MULTI_V4_V5 365 bool 366 367config ARCH_MULTI_V6 368 bool "ARMv6 based platforms (ARM11)" 369 select ARCH_MULTI_V6_V7 370 select CPU_V6K 371 372config ARCH_MULTI_V7 373 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 374 default y 375 select ARCH_MULTI_V6_V7 376 select CPU_V7 377 select HAVE_SMP 378 379config ARCH_MULTI_V6_V7 380 bool 381 select MIGHT_HAVE_CACHE_L2X0 382 383config ARCH_MULTI_CPU_AUTO 384 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 385 select ARCH_MULTI_V5 386 387endmenu 388 389config ARCH_VIRT 390 bool "Dummy Virtual Machine" 391 depends on ARCH_MULTI_V7 392 select ARM_AMBA 393 select ARM_GIC 394 select ARM_GIC_V2M if PCI 395 select ARM_GIC_V3 396 select ARM_GIC_V3_ITS if PCI 397 select ARM_PSCI 398 select HAVE_ARM_ARCH_TIMER 399 400config ARCH_AIROHA 401 bool "Airoha SoC Support" 402 depends on ARCH_MULTI_V7 403 select ARM_AMBA 404 select ARM_GIC 405 select ARM_GIC_V3 406 select ARM_PSCI 407 select HAVE_ARM_ARCH_TIMER 408 help 409 Support for Airoha EN7523 SoCs 410 411# 412# This is sorted alphabetically by mach-* pathname. However, plat-* 413# Kconfigs may be included either alphabetically (according to the 414# plat- suffix) or along side the corresponding mach-* source. 415# 416source "arch/arm/mach-actions/Kconfig" 417 418source "arch/arm/mach-alpine/Kconfig" 419 420source "arch/arm/mach-artpec/Kconfig" 421 422source "arch/arm/mach-asm9260/Kconfig" 423 424source "arch/arm/mach-aspeed/Kconfig" 425 426source "arch/arm/mach-at91/Kconfig" 427 428source "arch/arm/mach-axxia/Kconfig" 429 430source "arch/arm/mach-bcm/Kconfig" 431 432source "arch/arm/mach-berlin/Kconfig" 433 434source "arch/arm/mach-clps711x/Kconfig" 435 436source "arch/arm/mach-cns3xxx/Kconfig" 437 438source "arch/arm/mach-davinci/Kconfig" 439 440source "arch/arm/mach-digicolor/Kconfig" 441 442source "arch/arm/mach-dove/Kconfig" 443 444source "arch/arm/mach-ep93xx/Kconfig" 445 446source "arch/arm/mach-exynos/Kconfig" 447 448source "arch/arm/mach-footbridge/Kconfig" 449 450source "arch/arm/mach-gemini/Kconfig" 451 452source "arch/arm/mach-highbank/Kconfig" 453 454source "arch/arm/mach-hisi/Kconfig" 455 456source "arch/arm/mach-hpe/Kconfig" 457 458source "arch/arm/mach-imx/Kconfig" 459 460source "arch/arm/mach-iop32x/Kconfig" 461 462source "arch/arm/mach-ixp4xx/Kconfig" 463 464source "arch/arm/mach-keystone/Kconfig" 465 466source "arch/arm/mach-lpc32xx/Kconfig" 467 468source "arch/arm/mach-mediatek/Kconfig" 469 470source "arch/arm/mach-meson/Kconfig" 471 472source "arch/arm/mach-milbeaut/Kconfig" 473 474source "arch/arm/mach-mmp/Kconfig" 475 476source "arch/arm/mach-moxart/Kconfig" 477 478source "arch/arm/mach-mstar/Kconfig" 479 480source "arch/arm/mach-mv78xx0/Kconfig" 481 482source "arch/arm/mach-mvebu/Kconfig" 483 484source "arch/arm/mach-mxs/Kconfig" 485 486source "arch/arm/mach-nomadik/Kconfig" 487 488source "arch/arm/mach-npcm/Kconfig" 489 490source "arch/arm/mach-nspire/Kconfig" 491 492source "arch/arm/mach-omap1/Kconfig" 493 494source "arch/arm/mach-omap2/Kconfig" 495 496source "arch/arm/mach-orion5x/Kconfig" 497 498source "arch/arm/mach-oxnas/Kconfig" 499 500source "arch/arm/mach-pxa/Kconfig" 501 502source "arch/arm/mach-qcom/Kconfig" 503 504source "arch/arm/mach-rda/Kconfig" 505 506source "arch/arm/mach-realtek/Kconfig" 507 508source "arch/arm/mach-rpc/Kconfig" 509 510source "arch/arm/mach-rockchip/Kconfig" 511 512source "arch/arm/mach-s3c/Kconfig" 513 514source "arch/arm/mach-s5pv210/Kconfig" 515 516source "arch/arm/mach-sa1100/Kconfig" 517 518source "arch/arm/mach-shmobile/Kconfig" 519 520source "arch/arm/mach-socfpga/Kconfig" 521 522source "arch/arm/mach-spear/Kconfig" 523 524source "arch/arm/mach-sti/Kconfig" 525 526source "arch/arm/mach-stm32/Kconfig" 527 528source "arch/arm/mach-sunplus/Kconfig" 529 530source "arch/arm/mach-sunxi/Kconfig" 531 532source "arch/arm/mach-tegra/Kconfig" 533 534source "arch/arm/mach-uniphier/Kconfig" 535 536source "arch/arm/mach-ux500/Kconfig" 537 538source "arch/arm/mach-versatile/Kconfig" 539 540source "arch/arm/mach-vt8500/Kconfig" 541 542source "arch/arm/mach-zynq/Kconfig" 543 544# ARMv7-M architecture 545config ARCH_LPC18XX 546 bool "NXP LPC18xx/LPC43xx" 547 depends on ARM_SINGLE_ARMV7M 548 select ARCH_HAS_RESET_CONTROLLER 549 select ARM_AMBA 550 select CLKSRC_LPC32XX 551 select PINCTRL 552 help 553 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 554 high performance microcontrollers. 555 556config ARCH_MPS2 557 bool "ARM MPS2 platform" 558 depends on ARM_SINGLE_ARMV7M 559 select ARM_AMBA 560 select CLKSRC_MPS2 561 help 562 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 563 with a range of available cores like Cortex-M3/M4/M7. 564 565 Please, note that depends which Application Note is used memory map 566 for the platform may vary, so adjustment of RAM base might be needed. 567 568# Definitions to make life easier 569config ARCH_ACORN 570 bool 571 572config PLAT_ORION 573 bool 574 select CLKSRC_MMIO 575 select GENERIC_IRQ_CHIP 576 select IRQ_DOMAIN 577 578config PLAT_ORION_LEGACY 579 bool 580 select PLAT_ORION 581 582config PLAT_VERSATILE 583 bool 584 585source "arch/arm/mm/Kconfig" 586 587config IWMMXT 588 bool "Enable iWMMXt support" 589 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 590 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 591 help 592 Enable support for iWMMXt context switching at run time if 593 running on a CPU that supports it. 594 595if !MMU 596source "arch/arm/Kconfig-nommu" 597endif 598 599config PJ4B_ERRATA_4742 600 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 601 depends on CPU_PJ4B && MACH_ARMADA_370 602 default y 603 help 604 When coming out of either a Wait for Interrupt (WFI) or a Wait for 605 Event (WFE) IDLE states, a specific timing sensitivity exists between 606 the retiring WFI/WFE instructions and the newly issued subsequent 607 instructions. This sensitivity can result in a CPU hang scenario. 608 Workaround: 609 The software must insert either a Data Synchronization Barrier (DSB) 610 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 611 instruction 612 613config ARM_ERRATA_326103 614 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 615 depends on CPU_V6 616 help 617 Executing a SWP instruction to read-only memory does not set bit 11 618 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 619 treat the access as a read, preventing a COW from occurring and 620 causing the faulting task to livelock. 621 622config ARM_ERRATA_411920 623 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 624 depends on CPU_V6 || CPU_V6K 625 help 626 Invalidation of the Instruction Cache operation can 627 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 628 It does not affect the MPCore. This option enables the ARM Ltd. 629 recommended workaround. 630 631config ARM_ERRATA_430973 632 bool "ARM errata: Stale prediction on replaced interworking branch" 633 depends on CPU_V7 634 help 635 This option enables the workaround for the 430973 Cortex-A8 636 r1p* erratum. If a code sequence containing an ARM/Thumb 637 interworking branch is replaced with another code sequence at the 638 same virtual address, whether due to self-modifying code or virtual 639 to physical address re-mapping, Cortex-A8 does not recover from the 640 stale interworking branch prediction. This results in Cortex-A8 641 executing the new code sequence in the incorrect ARM or Thumb state. 642 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 643 and also flushes the branch target cache at every context switch. 644 Note that setting specific bits in the ACTLR register may not be 645 available in non-secure mode. 646 647config ARM_ERRATA_458693 648 bool "ARM errata: Processor deadlock when a false hazard is created" 649 depends on CPU_V7 650 depends on !ARCH_MULTIPLATFORM 651 help 652 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 653 erratum. For very specific sequences of memory operations, it is 654 possible for a hazard condition intended for a cache line to instead 655 be incorrectly associated with a different cache line. This false 656 hazard might then cause a processor deadlock. The workaround enables 657 the L1 caching of the NEON accesses and disables the PLD instruction 658 in the ACTLR register. Note that setting specific bits in the ACTLR 659 register may not be available in non-secure mode. 660 661config ARM_ERRATA_460075 662 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 663 depends on CPU_V7 664 depends on !ARCH_MULTIPLATFORM 665 help 666 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 667 erratum. Any asynchronous access to the L2 cache may encounter a 668 situation in which recent store transactions to the L2 cache are lost 669 and overwritten with stale memory contents from external memory. The 670 workaround disables the write-allocate mode for the L2 cache via the 671 ACTLR register. Note that setting specific bits in the ACTLR register 672 may not be available in non-secure mode. 673 674config ARM_ERRATA_742230 675 bool "ARM errata: DMB operation may be faulty" 676 depends on CPU_V7 && SMP 677 depends on !ARCH_MULTIPLATFORM 678 help 679 This option enables the workaround for the 742230 Cortex-A9 680 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 681 between two write operations may not ensure the correct visibility 682 ordering of the two writes. This workaround sets a specific bit in 683 the diagnostic register of the Cortex-A9 which causes the DMB 684 instruction to behave as a DSB, ensuring the correct behaviour of 685 the two writes. 686 687config ARM_ERRATA_742231 688 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 689 depends on CPU_V7 && SMP 690 depends on !ARCH_MULTIPLATFORM 691 help 692 This option enables the workaround for the 742231 Cortex-A9 693 (r2p0..r2p2) erratum. Under certain conditions, specific to the 694 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 695 accessing some data located in the same cache line, may get corrupted 696 data due to bad handling of the address hazard when the line gets 697 replaced from one of the CPUs at the same time as another CPU is 698 accessing it. This workaround sets specific bits in the diagnostic 699 register of the Cortex-A9 which reduces the linefill issuing 700 capabilities of the processor. 701 702config ARM_ERRATA_643719 703 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 704 depends on CPU_V7 && SMP 705 default y 706 help 707 This option enables the workaround for the 643719 Cortex-A9 (prior to 708 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 709 register returns zero when it should return one. The workaround 710 corrects this value, ensuring cache maintenance operations which use 711 it behave as intended and avoiding data corruption. 712 713config ARM_ERRATA_720789 714 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 715 depends on CPU_V7 716 help 717 This option enables the workaround for the 720789 Cortex-A9 (prior to 718 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 719 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 720 As a consequence of this erratum, some TLB entries which should be 721 invalidated are not, resulting in an incoherency in the system page 722 tables. The workaround changes the TLB flushing routines to invalidate 723 entries regardless of the ASID. 724 725config ARM_ERRATA_743622 726 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 727 depends on CPU_V7 728 depends on !ARCH_MULTIPLATFORM 729 help 730 This option enables the workaround for the 743622 Cortex-A9 731 (r2p*) erratum. Under very rare conditions, a faulty 732 optimisation in the Cortex-A9 Store Buffer may lead to data 733 corruption. This workaround sets a specific bit in the diagnostic 734 register of the Cortex-A9 which disables the Store Buffer 735 optimisation, preventing the defect from occurring. This has no 736 visible impact on the overall performance or power consumption of the 737 processor. 738 739config ARM_ERRATA_751472 740 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 741 depends on CPU_V7 742 depends on !ARCH_MULTIPLATFORM 743 help 744 This option enables the workaround for the 751472 Cortex-A9 (prior 745 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 746 completion of a following broadcasted operation if the second 747 operation is received by a CPU before the ICIALLUIS has completed, 748 potentially leading to corrupted entries in the cache or TLB. 749 750config ARM_ERRATA_754322 751 bool "ARM errata: possible faulty MMU translations following an ASID switch" 752 depends on CPU_V7 753 help 754 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 755 r3p*) erratum. A speculative memory access may cause a page table walk 756 which starts prior to an ASID switch but completes afterwards. This 757 can populate the micro-TLB with a stale entry which may be hit with 758 the new ASID. This workaround places two dsb instructions in the mm 759 switching code so that no page table walks can cross the ASID switch. 760 761config ARM_ERRATA_754327 762 bool "ARM errata: no automatic Store Buffer drain" 763 depends on CPU_V7 && SMP 764 help 765 This option enables the workaround for the 754327 Cortex-A9 (prior to 766 r2p0) erratum. The Store Buffer does not have any automatic draining 767 mechanism and therefore a livelock may occur if an external agent 768 continuously polls a memory location waiting to observe an update. 769 This workaround defines cpu_relax() as smp_mb(), preventing correctly 770 written polling loops from denying visibility of updates to memory. 771 772config ARM_ERRATA_364296 773 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 774 depends on CPU_V6 775 help 776 This options enables the workaround for the 364296 ARM1136 777 r0p2 erratum (possible cache data corruption with 778 hit-under-miss enabled). It sets the undocumented bit 31 in 779 the auxiliary control register and the FI bit in the control 780 register, thus disabling hit-under-miss without putting the 781 processor into full low interrupt latency mode. ARM11MPCore 782 is not affected. 783 784config ARM_ERRATA_764369 785 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 786 depends on CPU_V7 && SMP 787 help 788 This option enables the workaround for erratum 764369 789 affecting Cortex-A9 MPCore with two or more processors (all 790 current revisions). Under certain timing circumstances, a data 791 cache line maintenance operation by MVA targeting an Inner 792 Shareable memory region may fail to proceed up to either the 793 Point of Coherency or to the Point of Unification of the 794 system. This workaround adds a DSB instruction before the 795 relevant cache maintenance functions and sets a specific bit 796 in the diagnostic control register of the SCU. 797 798config ARM_ERRATA_764319 799 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 800 depends on CPU_V7 801 help 802 This option enables the workaround for the 764319 Cortex A-9 erratum. 803 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 804 unexpected Undefined Instruction exception when the DBGSWENABLE 805 external pin is set to 0, even when the CP14 accesses are performed 806 from a privileged mode. This work around catches the exception in a 807 way the kernel does not stop execution. 808 809config ARM_ERRATA_775420 810 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 811 depends on CPU_V7 812 help 813 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 814 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 815 operation aborts with MMU exception, it might cause the processor 816 to deadlock. This workaround puts DSB before executing ISB if 817 an abort may occur on cache maintenance. 818 819config ARM_ERRATA_798181 820 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 821 depends on CPU_V7 && SMP 822 help 823 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 824 adequately shooting down all use of the old entries. This 825 option enables the Linux kernel workaround for this erratum 826 which sends an IPI to the CPUs that are running the same ASID 827 as the one being invalidated. 828 829config ARM_ERRATA_773022 830 bool "ARM errata: incorrect instructions may be executed from loop buffer" 831 depends on CPU_V7 832 help 833 This option enables the workaround for the 773022 Cortex-A15 834 (up to r0p4) erratum. In certain rare sequences of code, the 835 loop buffer may deliver incorrect instructions. This 836 workaround disables the loop buffer to avoid the erratum. 837 838config ARM_ERRATA_818325_852422 839 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 840 depends on CPU_V7 841 help 842 This option enables the workaround for: 843 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 844 instruction might deadlock. Fixed in r0p1. 845 - Cortex-A12 852422: Execution of a sequence of instructions might 846 lead to either a data corruption or a CPU deadlock. Not fixed in 847 any Cortex-A12 cores yet. 848 This workaround for all both errata involves setting bit[12] of the 849 Feature Register. This bit disables an optimisation applied to a 850 sequence of 2 instructions that use opposing condition codes. 851 852config ARM_ERRATA_821420 853 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 854 depends on CPU_V7 855 help 856 This option enables the workaround for the 821420 Cortex-A12 857 (all revs) erratum. In very rare timing conditions, a sequence 858 of VMOV to Core registers instructions, for which the second 859 one is in the shadow of a branch or abort, can lead to a 860 deadlock when the VMOV instructions are issued out-of-order. 861 862config ARM_ERRATA_825619 863 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 864 depends on CPU_V7 865 help 866 This option enables the workaround for the 825619 Cortex-A12 867 (all revs) erratum. Within rare timing constraints, executing a 868 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 869 and Device/Strongly-Ordered loads and stores might cause deadlock 870 871config ARM_ERRATA_857271 872 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 873 depends on CPU_V7 874 help 875 This option enables the workaround for the 857271 Cortex-A12 876 (all revs) erratum. Under very rare timing conditions, the CPU might 877 hang. The workaround is expected to have a < 1% performance impact. 878 879config ARM_ERRATA_852421 880 bool "ARM errata: A17: DMB ST might fail to create order between stores" 881 depends on CPU_V7 882 help 883 This option enables the workaround for the 852421 Cortex-A17 884 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 885 execution of a DMB ST instruction might fail to properly order 886 stores from GroupA and stores from GroupB. 887 888config ARM_ERRATA_852423 889 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 890 depends on CPU_V7 891 help 892 This option enables the workaround for: 893 - Cortex-A17 852423: Execution of a sequence of instructions might 894 lead to either a data corruption or a CPU deadlock. Not fixed in 895 any Cortex-A17 cores yet. 896 This is identical to Cortex-A12 erratum 852422. It is a separate 897 config option from the A12 erratum due to the way errata are checked 898 for and handled. 899 900config ARM_ERRATA_857272 901 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 902 depends on CPU_V7 903 help 904 This option enables the workaround for the 857272 Cortex-A17 erratum. 905 This erratum is not known to be fixed in any A17 revision. 906 This is identical to Cortex-A12 erratum 857271. It is a separate 907 config option from the A12 erratum due to the way errata are checked 908 for and handled. 909 910endmenu 911 912source "arch/arm/common/Kconfig" 913 914menu "Bus support" 915 916config ISA 917 bool 918 help 919 Find out whether you have ISA slots on your motherboard. ISA is the 920 name of a bus system, i.e. the way the CPU talks to the other stuff 921 inside your box. Other bus systems are PCI, EISA, MicroChannel 922 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 923 newer boards don't support it. If you have ISA, say Y, otherwise N. 924 925# Select ISA DMA interface 926config ISA_DMA_API 927 bool 928 929config PCI_NANOENGINE 930 bool "BSE nanoEngine PCI support" 931 depends on SA1100_NANOENGINE 932 help 933 Enable PCI on the BSE nanoEngine board. 934 935config ARM_ERRATA_814220 936 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 937 depends on CPU_V7 938 help 939 The v7 ARM states that all cache and branch predictor maintenance 940 operations that do not specify an address execute, relative to 941 each other, in program order. 942 However, because of this erratum, an L2 set/way cache maintenance 943 operation can overtake an L1 set/way cache maintenance operation. 944 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 945 r0p4, r0p5. 946 947endmenu 948 949menu "Kernel Features" 950 951config HAVE_SMP 952 bool 953 help 954 This option should be selected by machines which have an SMP- 955 capable CPU. 956 957 The only effect of this option is to make the SMP-related 958 options available to the user for configuration. 959 960config SMP 961 bool "Symmetric Multi-Processing" 962 depends on CPU_V6K || CPU_V7 963 depends on HAVE_SMP 964 depends on MMU || ARM_MPU 965 select IRQ_WORK 966 help 967 This enables support for systems with more than one CPU. If you have 968 a system with only one CPU, say N. If you have a system with more 969 than one CPU, say Y. 970 971 If you say N here, the kernel will run on uni- and multiprocessor 972 machines, but will use only one CPU of a multiprocessor machine. If 973 you say Y here, the kernel will run on many, but not all, 974 uniprocessor machines. On a uniprocessor machine, the kernel 975 will run faster if you say N here. 976 977 See also <file:Documentation/x86/i386/IO-APIC.rst>, 978 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 979 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 980 981 If you don't know what to do here, say N. 982 983config SMP_ON_UP 984 bool "Allow booting SMP kernel on uniprocessor systems" 985 depends on SMP && MMU 986 default y 987 help 988 SMP kernels contain instructions which fail on non-SMP processors. 989 Enabling this option allows the kernel to modify itself to make 990 these instructions safe. Disabling it allows about 1K of space 991 savings. 992 993 If you don't know what to do here, say Y. 994 995 996config CURRENT_POINTER_IN_TPIDRURO 997 def_bool y 998 depends on CPU_32v6K && !CPU_V6 999 1000config IRQSTACKS 1001 def_bool y 1002 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1003 select HAVE_SOFTIRQ_ON_OWN_STACK 1004 1005config ARM_CPU_TOPOLOGY 1006 bool "Support cpu topology definition" 1007 depends on SMP && CPU_V7 1008 default y 1009 help 1010 Support ARM cpu topology definition. The MPIDR register defines 1011 affinity between processors which is then used to describe the cpu 1012 topology of an ARM System. 1013 1014config SCHED_MC 1015 bool "Multi-core scheduler support" 1016 depends on ARM_CPU_TOPOLOGY 1017 help 1018 Multi-core scheduler support improves the CPU scheduler's decision 1019 making when dealing with multi-core CPU chips at a cost of slightly 1020 increased overhead in some places. If unsure say N here. 1021 1022config SCHED_SMT 1023 bool "SMT scheduler support" 1024 depends on ARM_CPU_TOPOLOGY 1025 help 1026 Improves the CPU scheduler's decision making when dealing with 1027 MultiThreading at a cost of slightly increased overhead in some 1028 places. If unsure say N here. 1029 1030config HAVE_ARM_SCU 1031 bool 1032 help 1033 This option enables support for the ARM snoop control unit 1034 1035config HAVE_ARM_ARCH_TIMER 1036 bool "Architected timer support" 1037 depends on CPU_V7 1038 select ARM_ARCH_TIMER 1039 help 1040 This option enables support for the ARM architected timer 1041 1042config HAVE_ARM_TWD 1043 bool 1044 help 1045 This options enables support for the ARM timer and watchdog unit 1046 1047config MCPM 1048 bool "Multi-Cluster Power Management" 1049 depends on CPU_V7 && SMP 1050 help 1051 This option provides the common power management infrastructure 1052 for (multi-)cluster based systems, such as big.LITTLE based 1053 systems. 1054 1055config MCPM_QUAD_CLUSTER 1056 bool 1057 depends on MCPM 1058 help 1059 To avoid wasting resources unnecessarily, MCPM only supports up 1060 to 2 clusters by default. 1061 Platforms with 3 or 4 clusters that use MCPM must select this 1062 option to allow the additional clusters to be managed. 1063 1064config BIG_LITTLE 1065 bool "big.LITTLE support (Experimental)" 1066 depends on CPU_V7 && SMP 1067 select MCPM 1068 help 1069 This option enables support selections for the big.LITTLE 1070 system architecture. 1071 1072config BL_SWITCHER 1073 bool "big.LITTLE switcher support" 1074 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1075 select CPU_PM 1076 help 1077 The big.LITTLE "switcher" provides the core functionality to 1078 transparently handle transition between a cluster of A15's 1079 and a cluster of A7's in a big.LITTLE system. 1080 1081config BL_SWITCHER_DUMMY_IF 1082 tristate "Simple big.LITTLE switcher user interface" 1083 depends on BL_SWITCHER && DEBUG_KERNEL 1084 help 1085 This is a simple and dummy char dev interface to control 1086 the big.LITTLE switcher core code. It is meant for 1087 debugging purposes only. 1088 1089choice 1090 prompt "Memory split" 1091 depends on MMU 1092 default VMSPLIT_3G 1093 help 1094 Select the desired split between kernel and user memory. 1095 1096 If you are not absolutely sure what you are doing, leave this 1097 option alone! 1098 1099 config VMSPLIT_3G 1100 bool "3G/1G user/kernel split" 1101 config VMSPLIT_3G_OPT 1102 depends on !ARM_LPAE 1103 bool "3G/1G user/kernel split (for full 1G low memory)" 1104 config VMSPLIT_2G 1105 bool "2G/2G user/kernel split" 1106 config VMSPLIT_1G 1107 bool "1G/3G user/kernel split" 1108endchoice 1109 1110config PAGE_OFFSET 1111 hex 1112 default PHYS_OFFSET if !MMU 1113 default 0x40000000 if VMSPLIT_1G 1114 default 0x80000000 if VMSPLIT_2G 1115 default 0xB0000000 if VMSPLIT_3G_OPT 1116 default 0xC0000000 1117 1118config KASAN_SHADOW_OFFSET 1119 hex 1120 depends on KASAN 1121 default 0x1f000000 if PAGE_OFFSET=0x40000000 1122 default 0x5f000000 if PAGE_OFFSET=0x80000000 1123 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1124 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1125 default 0xffffffff 1126 1127config NR_CPUS 1128 int "Maximum number of CPUs (2-32)" 1129 range 2 16 if DEBUG_KMAP_LOCAL 1130 range 2 32 if !DEBUG_KMAP_LOCAL 1131 depends on SMP 1132 default "4" 1133 help 1134 The maximum number of CPUs that the kernel can support. 1135 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1136 debugging is enabled, which uses half of the per-CPU fixmap 1137 slots as guard regions. 1138 1139config HOTPLUG_CPU 1140 bool "Support for hot-pluggable CPUs" 1141 depends on SMP 1142 select GENERIC_IRQ_MIGRATION 1143 help 1144 Say Y here to experiment with turning CPUs off and on. CPUs 1145 can be controlled through /sys/devices/system/cpu. 1146 1147config ARM_PSCI 1148 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1149 depends on HAVE_ARM_SMCCC 1150 select ARM_PSCI_FW 1151 help 1152 Say Y here if you want Linux to communicate with system firmware 1153 implementing the PSCI specification for CPU-centric power 1154 management operations described in ARM document number ARM DEN 1155 0022A ("Power State Coordination Interface System Software on 1156 ARM processors"). 1157 1158# The GPIO number here must be sorted by descending number. In case of 1159# a multiplatform kernel, we just want the highest value required by the 1160# selected platforms. 1161config ARCH_NR_GPIO 1162 int 1163 default 2048 if ARCH_INTEL_SOCFPGA 1164 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1165 ARCH_ZYNQ || ARCH_ASPEED 1166 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1167 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1168 default 416 if ARCH_SUNXI 1169 default 392 if ARCH_U8500 1170 default 352 if ARCH_VT8500 1171 default 288 if ARCH_ROCKCHIP 1172 default 264 if MACH_H4700 1173 default 0 1174 help 1175 Maximum number of GPIOs in the system. 1176 1177 If unsure, leave the default value. 1178 1179config HZ_FIXED 1180 int 1181 default 128 if SOC_AT91RM9200 1182 default 0 1183 1184choice 1185 depends on HZ_FIXED = 0 1186 prompt "Timer frequency" 1187 1188config HZ_100 1189 bool "100 Hz" 1190 1191config HZ_200 1192 bool "200 Hz" 1193 1194config HZ_250 1195 bool "250 Hz" 1196 1197config HZ_300 1198 bool "300 Hz" 1199 1200config HZ_500 1201 bool "500 Hz" 1202 1203config HZ_1000 1204 bool "1000 Hz" 1205 1206endchoice 1207 1208config HZ 1209 int 1210 default HZ_FIXED if HZ_FIXED != 0 1211 default 100 if HZ_100 1212 default 200 if HZ_200 1213 default 250 if HZ_250 1214 default 300 if HZ_300 1215 default 500 if HZ_500 1216 default 1000 1217 1218config SCHED_HRTICK 1219 def_bool HIGH_RES_TIMERS 1220 1221config THUMB2_KERNEL 1222 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1223 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1224 default y if CPU_THUMBONLY 1225 select ARM_UNWIND 1226 help 1227 By enabling this option, the kernel will be compiled in 1228 Thumb-2 mode. 1229 1230 If unsure, say N. 1231 1232config ARM_PATCH_IDIV 1233 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1234 depends on CPU_32v7 1235 default y 1236 help 1237 The ARM compiler inserts calls to __aeabi_idiv() and 1238 __aeabi_uidiv() when it needs to perform division on signed 1239 and unsigned integers. Some v7 CPUs have support for the sdiv 1240 and udiv instructions that can be used to implement those 1241 functions. 1242 1243 Enabling this option allows the kernel to modify itself to 1244 replace the first two instructions of these library functions 1245 with the sdiv or udiv plus "bx lr" instructions when the CPU 1246 it is running on supports them. Typically this will be faster 1247 and less power intensive than running the original library 1248 code to do integer division. 1249 1250config AEABI 1251 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1252 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1253 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1254 help 1255 This option allows for the kernel to be compiled using the latest 1256 ARM ABI (aka EABI). This is only useful if you are using a user 1257 space environment that is also compiled with EABI. 1258 1259 Since there are major incompatibilities between the legacy ABI and 1260 EABI, especially with regard to structure member alignment, this 1261 option also changes the kernel syscall calling convention to 1262 disambiguate both ABIs and allow for backward compatibility support 1263 (selected with CONFIG_OABI_COMPAT). 1264 1265 To use this you need GCC version 4.0.0 or later. 1266 1267config OABI_COMPAT 1268 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1269 depends on AEABI && !THUMB2_KERNEL 1270 help 1271 This option preserves the old syscall interface along with the 1272 new (ARM EABI) one. It also provides a compatibility layer to 1273 intercept syscalls that have structure arguments which layout 1274 in memory differs between the legacy ABI and the new ARM EABI 1275 (only for non "thumb" binaries). This option adds a tiny 1276 overhead to all syscalls and produces a slightly larger kernel. 1277 1278 The seccomp filter system will not be available when this is 1279 selected, since there is no way yet to sensibly distinguish 1280 between calling conventions during filtering. 1281 1282 If you know you'll be using only pure EABI user space then you 1283 can say N here. If this option is not selected and you attempt 1284 to execute a legacy ABI binary then the result will be 1285 UNPREDICTABLE (in fact it can be predicted that it won't work 1286 at all). If in doubt say N. 1287 1288config ARCH_SELECT_MEMORY_MODEL 1289 def_bool y 1290 1291config ARCH_FLATMEM_ENABLE 1292 def_bool !(ARCH_RPC || ARCH_SA1100) 1293 1294config ARCH_SPARSEMEM_ENABLE 1295 def_bool !ARCH_FOOTBRIDGE 1296 select SPARSEMEM_STATIC if SPARSEMEM 1297 1298config HIGHMEM 1299 bool "High Memory Support" 1300 depends on MMU 1301 select KMAP_LOCAL 1302 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1303 help 1304 The address space of ARM processors is only 4 Gigabytes large 1305 and it has to accommodate user address space, kernel address 1306 space as well as some memory mapped IO. That means that, if you 1307 have a large amount of physical memory and/or IO, not all of the 1308 memory can be "permanently mapped" by the kernel. The physical 1309 memory that is not permanently mapped is called "high memory". 1310 1311 Depending on the selected kernel/user memory split, minimum 1312 vmalloc space and actual amount of RAM, you may not need this 1313 option which should result in a slightly faster kernel. 1314 1315 If unsure, say n. 1316 1317config HIGHPTE 1318 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1319 depends on HIGHMEM 1320 default y 1321 help 1322 The VM uses one page of physical memory for each page table. 1323 For systems with a lot of processes, this can use a lot of 1324 precious low memory, eventually leading to low memory being 1325 consumed by page tables. Setting this option will allow 1326 user-space 2nd level page tables to reside in high memory. 1327 1328config CPU_SW_DOMAIN_PAN 1329 bool "Enable use of CPU domains to implement privileged no-access" 1330 depends on MMU && !ARM_LPAE 1331 default y 1332 help 1333 Increase kernel security by ensuring that normal kernel accesses 1334 are unable to access userspace addresses. This can help prevent 1335 use-after-free bugs becoming an exploitable privilege escalation 1336 by ensuring that magic values (such as LIST_POISON) will always 1337 fault when dereferenced. 1338 1339 CPUs with low-vector mappings use a best-efforts implementation. 1340 Their lower 1MB needs to remain accessible for the vectors, but 1341 the remainder of userspace will become appropriately inaccessible. 1342 1343config HW_PERF_EVENTS 1344 def_bool y 1345 depends on ARM_PMU 1346 1347config ARM_MODULE_PLTS 1348 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1349 depends on MODULES 1350 select KASAN_VMALLOC if KASAN 1351 default y 1352 help 1353 Allocate PLTs when loading modules so that jumps and calls whose 1354 targets are too far away for their relative offsets to be encoded 1355 in the instructions themselves can be bounced via veneers in the 1356 module's PLT. This allows modules to be allocated in the generic 1357 vmalloc area after the dedicated module memory area has been 1358 exhausted. The modules will use slightly more memory, but after 1359 rounding up to page size, the actual memory footprint is usually 1360 the same. 1361 1362 Disabling this is usually safe for small single-platform 1363 configurations. If unsure, say y. 1364 1365config ARCH_FORCE_MAX_ORDER 1366 int "Maximum zone order" 1367 default "12" if SOC_AM33XX 1368 default "9" if SA1111 1369 default "11" 1370 help 1371 The kernel memory allocator divides physically contiguous memory 1372 blocks into "zones", where each zone is a power of two number of 1373 pages. This option selects the largest power of two that the kernel 1374 keeps in the memory allocator. If you need to allocate very large 1375 blocks of physically contiguous memory, then you may need to 1376 increase this value. 1377 1378 This config option is actually maximum order plus one. For example, 1379 a value of 11 means that the largest free memory block is 2^10 pages. 1380 1381config ALIGNMENT_TRAP 1382 def_bool CPU_CP15_MMU 1383 select HAVE_PROC_CPU if PROC_FS 1384 help 1385 ARM processors cannot fetch/store information which is not 1386 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1387 address divisible by 4. On 32-bit ARM processors, these non-aligned 1388 fetch/store instructions will be emulated in software if you say 1389 here, which has a severe performance impact. This is necessary for 1390 correct operation of some network protocols. With an IP-only 1391 configuration it is safe to say N, otherwise say Y. 1392 1393config UACCESS_WITH_MEMCPY 1394 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1395 depends on MMU 1396 default y if CPU_FEROCEON 1397 help 1398 Implement faster copy_to_user and clear_user methods for CPU 1399 cores where a 8-word STM instruction give significantly higher 1400 memory write throughput than a sequence of individual 32bit stores. 1401 1402 A possible side effect is a slight increase in scheduling latency 1403 between threads sharing the same address space if they invoke 1404 such copy operations with large buffers. 1405 1406 However, if the CPU data cache is using a write-allocate mode, 1407 this option is unlikely to provide any performance gain. 1408 1409config PARAVIRT 1410 bool "Enable paravirtualization code" 1411 help 1412 This changes the kernel so it can modify itself when it is run 1413 under a hypervisor, potentially improving performance significantly 1414 over full virtualization. 1415 1416config PARAVIRT_TIME_ACCOUNTING 1417 bool "Paravirtual steal time accounting" 1418 select PARAVIRT 1419 help 1420 Select this option to enable fine granularity task steal time 1421 accounting. Time spent executing other tasks in parallel with 1422 the current vCPU is discounted from the vCPU power. To account for 1423 that, there can be a small performance impact. 1424 1425 If in doubt, say N here. 1426 1427config XEN_DOM0 1428 def_bool y 1429 depends on XEN 1430 1431config XEN 1432 bool "Xen guest support on ARM" 1433 depends on ARM && AEABI && OF 1434 depends on CPU_V7 && !CPU_V6 1435 depends on !GENERIC_ATOMIC64 1436 depends on MMU 1437 select ARCH_DMA_ADDR_T_64BIT 1438 select ARM_PSCI 1439 select SWIOTLB 1440 select SWIOTLB_XEN 1441 select PARAVIRT 1442 help 1443 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1444 1445config CC_HAVE_STACKPROTECTOR_TLS 1446 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1447 1448config STACKPROTECTOR_PER_TASK 1449 bool "Use a unique stack canary value for each task" 1450 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1451 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1452 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1453 default y 1454 help 1455 Due to the fact that GCC uses an ordinary symbol reference from 1456 which to load the value of the stack canary, this value can only 1457 change at reboot time on SMP systems, and all tasks running in the 1458 kernel's address space are forced to use the same canary value for 1459 the entire duration that the system is up. 1460 1461 Enable this option to switch to a different method that uses a 1462 different canary value for each task. 1463 1464endmenu 1465 1466menu "Boot options" 1467 1468config USE_OF 1469 bool "Flattened Device Tree support" 1470 select IRQ_DOMAIN 1471 select OF 1472 help 1473 Include support for flattened device tree machine descriptions. 1474 1475config ATAGS 1476 bool "Support for the traditional ATAGS boot data passing" 1477 default y 1478 help 1479 This is the traditional way of passing data to the kernel at boot 1480 time. If you are solely relying on the flattened device tree (or 1481 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1482 to remove ATAGS support from your kernel binary. 1483 1484config UNUSED_BOARD_FILES 1485 bool "Board support for machines without known users" 1486 depends on ATAGS 1487 help 1488 Most ATAGS based board files are completely unused and are 1489 scheduled for removal in early 2023, and left out of kernels 1490 by default now. If you are using a board file that is marked 1491 as unused, turn on this option to build support into the kernel. 1492 1493 To keep support for your individual board from being removed, 1494 send a reply to the email discussion at 1495 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/ 1496 1497config DEPRECATED_PARAM_STRUCT 1498 bool "Provide old way to pass kernel parameters" 1499 depends on ATAGS 1500 help 1501 This was deprecated in 2001 and announced to live on for 5 years. 1502 Some old boot loaders still use this way. 1503 1504# Compressed boot loader in ROM. Yes, we really want to ask about 1505# TEXT and BSS so we preserve their values in the config files. 1506config ZBOOT_ROM_TEXT 1507 hex "Compressed ROM boot loader base address" 1508 default 0x0 1509 help 1510 The physical address at which the ROM-able zImage is to be 1511 placed in the target. Platforms which normally make use of 1512 ROM-able zImage formats normally set this to a suitable 1513 value in their defconfig file. 1514 1515 If ZBOOT_ROM is not enabled, this has no effect. 1516 1517config ZBOOT_ROM_BSS 1518 hex "Compressed ROM boot loader BSS address" 1519 default 0x0 1520 help 1521 The base address of an area of read/write memory in the target 1522 for the ROM-able zImage which must be available while the 1523 decompressor is running. It must be large enough to hold the 1524 entire decompressed kernel plus an additional 128 KiB. 1525 Platforms which normally make use of ROM-able zImage formats 1526 normally set this to a suitable value in their defconfig file. 1527 1528 If ZBOOT_ROM is not enabled, this has no effect. 1529 1530config ZBOOT_ROM 1531 bool "Compressed boot loader in ROM/flash" 1532 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1533 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1534 help 1535 Say Y here if you intend to execute your compressed kernel image 1536 (zImage) directly from ROM or flash. If unsure, say N. 1537 1538config ARM_APPENDED_DTB 1539 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1540 depends on OF 1541 help 1542 With this option, the boot code will look for a device tree binary 1543 (DTB) appended to zImage 1544 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1545 1546 This is meant as a backward compatibility convenience for those 1547 systems with a bootloader that can't be upgraded to accommodate 1548 the documented boot protocol using a device tree. 1549 1550 Beware that there is very little in terms of protection against 1551 this option being confused by leftover garbage in memory that might 1552 look like a DTB header after a reboot if no actual DTB is appended 1553 to zImage. Do not leave this option active in a production kernel 1554 if you don't intend to always append a DTB. Proper passing of the 1555 location into r2 of a bootloader provided DTB is always preferable 1556 to this option. 1557 1558config ARM_ATAG_DTB_COMPAT 1559 bool "Supplement the appended DTB with traditional ATAG information" 1560 depends on ARM_APPENDED_DTB 1561 help 1562 Some old bootloaders can't be updated to a DTB capable one, yet 1563 they provide ATAGs with memory configuration, the ramdisk address, 1564 the kernel cmdline string, etc. Such information is dynamically 1565 provided by the bootloader and can't always be stored in a static 1566 DTB. To allow a device tree enabled kernel to be used with such 1567 bootloaders, this option allows zImage to extract the information 1568 from the ATAG list and store it at run time into the appended DTB. 1569 1570choice 1571 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1572 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1573 1574config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1575 bool "Use bootloader kernel arguments if available" 1576 help 1577 Uses the command-line options passed by the boot loader instead of 1578 the device tree bootargs property. If the boot loader doesn't provide 1579 any, the device tree bootargs property will be used. 1580 1581config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1582 bool "Extend with bootloader kernel arguments" 1583 help 1584 The command-line arguments provided by the boot loader will be 1585 appended to the the device tree bootargs property. 1586 1587endchoice 1588 1589config CMDLINE 1590 string "Default kernel command string" 1591 default "" 1592 help 1593 On some architectures (e.g. CATS), there is currently no way 1594 for the boot loader to pass arguments to the kernel. For these 1595 architectures, you should supply some command-line options at build 1596 time by entering them here. As a minimum, you should specify the 1597 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1598 1599choice 1600 prompt "Kernel command line type" if CMDLINE != "" 1601 default CMDLINE_FROM_BOOTLOADER 1602 1603config CMDLINE_FROM_BOOTLOADER 1604 bool "Use bootloader kernel arguments if available" 1605 help 1606 Uses the command-line options passed by the boot loader. If 1607 the boot loader doesn't provide any, the default kernel command 1608 string provided in CMDLINE will be used. 1609 1610config CMDLINE_EXTEND 1611 bool "Extend bootloader kernel arguments" 1612 help 1613 The command-line arguments provided by the boot loader will be 1614 appended to the default kernel command string. 1615 1616config CMDLINE_FORCE 1617 bool "Always use the default kernel command string" 1618 help 1619 Always use the default kernel command string, even if the boot 1620 loader passes other arguments to the kernel. 1621 This is useful if you cannot or don't want to change the 1622 command-line options your boot loader passes to the kernel. 1623endchoice 1624 1625config XIP_KERNEL 1626 bool "Kernel Execute-In-Place from ROM" 1627 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1628 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1629 help 1630 Execute-In-Place allows the kernel to run from non-volatile storage 1631 directly addressable by the CPU, such as NOR flash. This saves RAM 1632 space since the text section of the kernel is not loaded from flash 1633 to RAM. Read-write sections, such as the data section and stack, 1634 are still copied to RAM. The XIP kernel is not compressed since 1635 it has to run directly from flash, so it will take more space to 1636 store it. The flash address used to link the kernel object files, 1637 and for storing it, is configuration dependent. Therefore, if you 1638 say Y here, you must know the proper physical address where to 1639 store the kernel image depending on your own flash memory usage. 1640 1641 Also note that the make target becomes "make xipImage" rather than 1642 "make zImage" or "make Image". The final kernel binary to put in 1643 ROM memory will be arch/arm/boot/xipImage. 1644 1645 If unsure, say N. 1646 1647config XIP_PHYS_ADDR 1648 hex "XIP Kernel Physical Location" 1649 depends on XIP_KERNEL 1650 default "0x00080000" 1651 help 1652 This is the physical address in your flash memory the kernel will 1653 be linked for and stored to. This address is dependent on your 1654 own flash usage. 1655 1656config XIP_DEFLATED_DATA 1657 bool "Store kernel .data section compressed in ROM" 1658 depends on XIP_KERNEL 1659 select ZLIB_INFLATE 1660 help 1661 Before the kernel is actually executed, its .data section has to be 1662 copied to RAM from ROM. This option allows for storing that data 1663 in compressed form and decompressed to RAM rather than merely being 1664 copied, saving some precious ROM space. A possible drawback is a 1665 slightly longer boot delay. 1666 1667config KEXEC 1668 bool "Kexec system call (EXPERIMENTAL)" 1669 depends on (!SMP || PM_SLEEP_SMP) 1670 depends on MMU 1671 select KEXEC_CORE 1672 help 1673 kexec is a system call that implements the ability to shutdown your 1674 current kernel, and to start another kernel. It is like a reboot 1675 but it is independent of the system firmware. And like a reboot 1676 you can start any kernel with it, not just Linux. 1677 1678 It is an ongoing process to be certain the hardware in a machine 1679 is properly shutdown, so do not be surprised if this code does not 1680 initially work for you. 1681 1682config ATAGS_PROC 1683 bool "Export atags in procfs" 1684 depends on ATAGS && KEXEC 1685 default y 1686 help 1687 Should the atags used to boot the kernel be exported in an "atags" 1688 file in procfs. Useful with kexec. 1689 1690config CRASH_DUMP 1691 bool "Build kdump crash kernel (EXPERIMENTAL)" 1692 help 1693 Generate crash dump after being started by kexec. This should 1694 be normally only set in special crash dump kernels which are 1695 loaded in the main kernel with kexec-tools into a specially 1696 reserved region and then later executed after a crash by 1697 kdump/kexec. The crash dump kernel must be compiled to a 1698 memory address not used by the main kernel 1699 1700 For more details see Documentation/admin-guide/kdump/kdump.rst 1701 1702config AUTO_ZRELADDR 1703 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1704 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1705 help 1706 ZRELADDR is the physical address where the decompressed kernel 1707 image will be placed. If AUTO_ZRELADDR is selected, the address 1708 will be determined at run-time, either by masking the current IP 1709 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1710 This assumes the zImage being placed in the first 128MB from 1711 start of memory. 1712 1713config EFI_STUB 1714 bool 1715 1716config EFI 1717 bool "UEFI runtime support" 1718 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1719 select UCS2_STRING 1720 select EFI_PARAMS_FROM_FDT 1721 select EFI_STUB 1722 select EFI_GENERIC_STUB 1723 select EFI_RUNTIME_WRAPPERS 1724 help 1725 This option provides support for runtime services provided 1726 by UEFI firmware (such as non-volatile variables, realtime 1727 clock, and platform reset). A UEFI stub is also provided to 1728 allow the kernel to be booted as an EFI application. This 1729 is only useful for kernels that may run on systems that have 1730 UEFI firmware. 1731 1732config DMI 1733 bool "Enable support for SMBIOS (DMI) tables" 1734 depends on EFI 1735 default y 1736 help 1737 This enables SMBIOS/DMI feature for systems. 1738 1739 This option is only useful on systems that have UEFI firmware. 1740 However, even with this option, the resultant kernel should 1741 continue to boot on existing non-UEFI platforms. 1742 1743 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1744 i.e., the the practice of identifying the platform via DMI to 1745 decide whether certain workarounds for buggy hardware and/or 1746 firmware need to be enabled. This would require the DMI subsystem 1747 to be enabled much earlier than we do on ARM, which is non-trivial. 1748 1749endmenu 1750 1751menu "CPU Power Management" 1752 1753source "drivers/cpufreq/Kconfig" 1754 1755source "drivers/cpuidle/Kconfig" 1756 1757endmenu 1758 1759menu "Floating point emulation" 1760 1761comment "At least one emulation must be selected" 1762 1763config FPE_NWFPE 1764 bool "NWFPE math emulation" 1765 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1766 help 1767 Say Y to include the NWFPE floating point emulator in the kernel. 1768 This is necessary to run most binaries. Linux does not currently 1769 support floating point hardware so you need to say Y here even if 1770 your machine has an FPA or floating point co-processor podule. 1771 1772 You may say N here if you are going to load the Acorn FPEmulator 1773 early in the bootup. 1774 1775config FPE_NWFPE_XP 1776 bool "Support extended precision" 1777 depends on FPE_NWFPE 1778 help 1779 Say Y to include 80-bit support in the kernel floating-point 1780 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1781 Note that gcc does not generate 80-bit operations by default, 1782 so in most cases this option only enlarges the size of the 1783 floating point emulator without any good reason. 1784 1785 You almost surely want to say N here. 1786 1787config FPE_FASTFPE 1788 bool "FastFPE math emulation (EXPERIMENTAL)" 1789 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1790 help 1791 Say Y here to include the FAST floating point emulator in the kernel. 1792 This is an experimental much faster emulator which now also has full 1793 precision for the mantissa. It does not support any exceptions. 1794 It is very simple, and approximately 3-6 times faster than NWFPE. 1795 1796 It should be sufficient for most programs. It may be not suitable 1797 for scientific calculations, but you have to check this for yourself. 1798 If you do not feel you need a faster FP emulation you should better 1799 choose NWFPE. 1800 1801config VFP 1802 bool "VFP-format floating point maths" 1803 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1804 help 1805 Say Y to include VFP support code in the kernel. This is needed 1806 if your hardware includes a VFP unit. 1807 1808 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1809 release notes and additional status information. 1810 1811 Say N if your target does not have VFP hardware. 1812 1813config VFPv3 1814 bool 1815 depends on VFP 1816 default y if CPU_V7 1817 1818config NEON 1819 bool "Advanced SIMD (NEON) Extension support" 1820 depends on VFPv3 && CPU_V7 1821 help 1822 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1823 Extension. 1824 1825config KERNEL_MODE_NEON 1826 bool "Support for NEON in kernel mode" 1827 depends on NEON && AEABI 1828 help 1829 Say Y to include support for NEON in kernel mode. 1830 1831endmenu 1832 1833menu "Power management options" 1834 1835source "kernel/power/Kconfig" 1836 1837config ARCH_SUSPEND_POSSIBLE 1838 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1839 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1840 def_bool y 1841 1842config ARM_CPU_SUSPEND 1843 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1844 depends on ARCH_SUSPEND_POSSIBLE 1845 1846config ARCH_HIBERNATION_POSSIBLE 1847 bool 1848 depends on MMU 1849 default y if ARCH_SUSPEND_POSSIBLE 1850 1851endmenu 1852 1853source "arch/arm/Kconfig.assembler" 1854