1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_EXTRA_PHDRS 14 select ARCH_BINFMT_ELF_STATE 15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 17 select ARCH_ENABLE_MEMORY_HOTPLUG 18 select ARCH_ENABLE_MEMORY_HOTREMOVE 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CURRENT_STACK_POINTER 23 select ARCH_HAS_DEBUG_VIRTUAL 24 select ARCH_HAS_DEBUG_VM_PGTABLE 25 select ARCH_HAS_DMA_PREP_COHERENT 26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 27 select ARCH_HAS_FAST_MULTIPLIER 28 select ARCH_HAS_FORTIFY_SOURCE 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_HAS_GIGANTIC_PAGE 31 select ARCH_HAS_KCOV 32 select ARCH_HAS_KEEPINITRD 33 select ARCH_HAS_MEMBARRIER_SYNC_CORE 34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 35 select ARCH_HAS_PTE_DEVMAP 36 select ARCH_HAS_PTE_SPECIAL 37 select ARCH_HAS_SETUP_DMA_OPS 38 select ARCH_HAS_SET_DIRECT_MAP 39 select ARCH_HAS_SET_MEMORY 40 select ARCH_STACKWALK 41 select ARCH_HAS_STRICT_KERNEL_RWX 42 select ARCH_HAS_STRICT_MODULE_RWX 43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 44 select ARCH_HAS_SYNC_DMA_FOR_CPU 45 select ARCH_HAS_SYSCALL_WRAPPER 46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 48 select ARCH_HAS_ZONE_DMA_SET if EXPERT 49 select ARCH_HAVE_ELF_PROT 50 select ARCH_HAVE_NMI_SAFE_CMPXCHG 51 select ARCH_HAVE_TRACE_MMIO_ACCESS 52 select ARCH_INLINE_READ_LOCK if !PREEMPTION 53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 78 select ARCH_KEEP_MEMBLOCK 79 select ARCH_USE_CMPXCHG_LOCKREF 80 select ARCH_USE_GNU_PROPERTY 81 select ARCH_USE_MEMTEST 82 select ARCH_USE_QUEUED_RWLOCKS 83 select ARCH_USE_QUEUED_SPINLOCKS 84 select ARCH_USE_SYM_ANNOTATIONS 85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 86 select ARCH_SUPPORTS_HUGETLBFS 87 select ARCH_SUPPORTS_MEMORY_FAILURE 88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 90 select ARCH_SUPPORTS_LTO_CLANG_THIN 91 select ARCH_SUPPORTS_CFI_CLANG 92 select ARCH_SUPPORTS_ATOMIC_RMW 93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 94 select ARCH_SUPPORTS_NUMA_BALANCING 95 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 96 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 97 select ARCH_WANT_DEFAULT_BPF_JIT 98 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 99 select ARCH_WANT_FRAME_POINTERS 100 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 101 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP 102 select ARCH_WANT_LD_ORPHAN_WARN 103 select ARCH_WANTS_NO_INSTR 104 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 105 select ARCH_HAS_UBSAN_SANITIZE_ALL 106 select ARM_AMBA 107 select ARM_ARCH_TIMER 108 select ARM_GIC 109 select AUDIT_ARCH_COMPAT_GENERIC 110 select ARM_GIC_V2M if PCI 111 select ARM_GIC_V3 112 select ARM_GIC_V3_ITS if PCI 113 select ARM_PSCI_FW 114 select BUILDTIME_TABLE_SORT 115 select CLONE_BACKWARDS 116 select COMMON_CLK 117 select CPU_PM if (SUSPEND || CPU_IDLE) 118 select CRC32 119 select DCACHE_WORD_ACCESS 120 select DMA_DIRECT_REMAP 121 select EDAC_SUPPORT 122 select FRAME_POINTER 123 select GENERIC_ALLOCATOR 124 select GENERIC_ARCH_TOPOLOGY 125 select GENERIC_CLOCKEVENTS_BROADCAST 126 select GENERIC_CPU_AUTOPROBE 127 select GENERIC_CPU_VULNERABILITIES 128 select GENERIC_EARLY_IOREMAP 129 select GENERIC_IDLE_POLL_SETUP 130 select GENERIC_IOREMAP 131 select GENERIC_IRQ_IPI 132 select GENERIC_IRQ_PROBE 133 select GENERIC_IRQ_SHOW 134 select GENERIC_IRQ_SHOW_LEVEL 135 select GENERIC_LIB_DEVMEM_IS_ALLOWED 136 select GENERIC_PCI_IOMAP 137 select GENERIC_PTDUMP 138 select GENERIC_SCHED_CLOCK 139 select GENERIC_SMP_IDLE_THREAD 140 select GENERIC_TIME_VSYSCALL 141 select GENERIC_GETTIMEOFDAY 142 select GENERIC_VDSO_TIME_NS 143 select HARDIRQS_SW_RESEND 144 select HAVE_MOVE_PMD 145 select HAVE_MOVE_PUD 146 select HAVE_PCI 147 select HAVE_ACPI_APEI if (ACPI && EFI) 148 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 149 select HAVE_ARCH_AUDITSYSCALL 150 select HAVE_ARCH_BITREVERSE 151 select HAVE_ARCH_COMPILER_H 152 select HAVE_ARCH_HUGE_VMALLOC 153 select HAVE_ARCH_HUGE_VMAP 154 select HAVE_ARCH_JUMP_LABEL 155 select HAVE_ARCH_JUMP_LABEL_RELATIVE 156 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 157 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 158 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 159 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 160 # Some instrumentation may be unsound, hence EXPERT 161 select HAVE_ARCH_KCSAN if EXPERT 162 select HAVE_ARCH_KFENCE 163 select HAVE_ARCH_KGDB 164 select HAVE_ARCH_MMAP_RND_BITS 165 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 166 select HAVE_ARCH_PREL32_RELOCATIONS 167 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 168 select HAVE_ARCH_SECCOMP_FILTER 169 select HAVE_ARCH_STACKLEAK 170 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 171 select HAVE_ARCH_TRACEHOOK 172 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 173 select HAVE_ARCH_VMAP_STACK 174 select HAVE_ARM_SMCCC 175 select HAVE_ASM_MODVERSIONS 176 select HAVE_EBPF_JIT 177 select HAVE_C_RECORDMCOUNT 178 select HAVE_CMPXCHG_DOUBLE 179 select HAVE_CMPXCHG_LOCAL 180 select HAVE_CONTEXT_TRACKING_USER 181 select HAVE_DEBUG_KMEMLEAK 182 select HAVE_DMA_CONTIGUOUS 183 select HAVE_DYNAMIC_FTRACE 184 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 185 if DYNAMIC_FTRACE_WITH_REGS 186 select HAVE_EFFICIENT_UNALIGNED_ACCESS 187 select HAVE_FAST_GUP 188 select HAVE_FTRACE_MCOUNT_RECORD 189 select HAVE_FUNCTION_TRACER 190 select HAVE_FUNCTION_ERROR_INJECTION 191 select HAVE_FUNCTION_GRAPH_TRACER 192 select HAVE_GCC_PLUGINS 193 select HAVE_HW_BREAKPOINT if PERF_EVENTS 194 select HAVE_IOREMAP_PROT 195 select HAVE_IRQ_TIME_ACCOUNTING 196 select HAVE_KVM 197 select HAVE_NMI 198 select HAVE_PERF_EVENTS 199 select HAVE_PERF_REGS 200 select HAVE_PERF_USER_STACK_DUMP 201 select HAVE_PREEMPT_DYNAMIC_KEY 202 select HAVE_REGS_AND_STACK_ACCESS_API 203 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 204 select HAVE_FUNCTION_ARG_ACCESS_API 205 select MMU_GATHER_RCU_TABLE_FREE 206 select HAVE_RSEQ 207 select HAVE_STACKPROTECTOR 208 select HAVE_SYSCALL_TRACEPOINTS 209 select HAVE_KPROBES 210 select HAVE_KRETPROBES 211 select HAVE_GENERIC_VDSO 212 select IRQ_DOMAIN 213 select IRQ_FORCED_THREADING 214 select KASAN_VMALLOC if KASAN 215 select MODULES_USE_ELF_RELA 216 select NEED_DMA_MAP_STATE 217 select NEED_SG_DMA_LENGTH 218 select OF 219 select OF_EARLY_FLATTREE 220 select PCI_DOMAINS_GENERIC if PCI 221 select PCI_ECAM if (ACPI && PCI) 222 select PCI_SYSCALL if PCI 223 select POWER_RESET 224 select POWER_SUPPLY 225 select SPARSE_IRQ 226 select SWIOTLB 227 select SYSCTL_EXCEPTION_TRACE 228 select THREAD_INFO_IN_TASK 229 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 230 select TRACE_IRQFLAGS_SUPPORT 231 select TRACE_IRQFLAGS_NMI_SUPPORT 232 select HAVE_SOFTIRQ_ON_OWN_STACK 233 help 234 ARM 64-bit (AArch64) Linux support. 235 236config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 237 def_bool CC_IS_CLANG 238 # https://github.com/ClangBuiltLinux/linux/issues/1507 239 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 240 select HAVE_DYNAMIC_FTRACE_WITH_REGS 241 242config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 243 def_bool CC_IS_GCC 244 depends on $(cc-option,-fpatchable-function-entry=2) 245 select HAVE_DYNAMIC_FTRACE_WITH_REGS 246 247config 64BIT 248 def_bool y 249 250config MMU 251 def_bool y 252 253config ARM64_PAGE_SHIFT 254 int 255 default 16 if ARM64_64K_PAGES 256 default 14 if ARM64_16K_PAGES 257 default 12 258 259config ARM64_CONT_PTE_SHIFT 260 int 261 default 5 if ARM64_64K_PAGES 262 default 7 if ARM64_16K_PAGES 263 default 4 264 265config ARM64_CONT_PMD_SHIFT 266 int 267 default 5 if ARM64_64K_PAGES 268 default 5 if ARM64_16K_PAGES 269 default 4 270 271config ARCH_MMAP_RND_BITS_MIN 272 default 14 if ARM64_64K_PAGES 273 default 16 if ARM64_16K_PAGES 274 default 18 275 276# max bits determined by the following formula: 277# VA_BITS - PAGE_SHIFT - 3 278config ARCH_MMAP_RND_BITS_MAX 279 default 19 if ARM64_VA_BITS=36 280 default 24 if ARM64_VA_BITS=39 281 default 27 if ARM64_VA_BITS=42 282 default 30 if ARM64_VA_BITS=47 283 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 284 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 285 default 33 if ARM64_VA_BITS=48 286 default 14 if ARM64_64K_PAGES 287 default 16 if ARM64_16K_PAGES 288 default 18 289 290config ARCH_MMAP_RND_COMPAT_BITS_MIN 291 default 7 if ARM64_64K_PAGES 292 default 9 if ARM64_16K_PAGES 293 default 11 294 295config ARCH_MMAP_RND_COMPAT_BITS_MAX 296 default 16 297 298config NO_IOPORT_MAP 299 def_bool y if !PCI 300 301config STACKTRACE_SUPPORT 302 def_bool y 303 304config ILLEGAL_POINTER_VALUE 305 hex 306 default 0xdead000000000000 307 308config LOCKDEP_SUPPORT 309 def_bool y 310 311config GENERIC_BUG 312 def_bool y 313 depends on BUG 314 315config GENERIC_BUG_RELATIVE_POINTERS 316 def_bool y 317 depends on GENERIC_BUG 318 319config GENERIC_HWEIGHT 320 def_bool y 321 322config GENERIC_CSUM 323 def_bool y 324 325config GENERIC_CALIBRATE_DELAY 326 def_bool y 327 328config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 329 def_bool y 330 331config SMP 332 def_bool y 333 334config KERNEL_MODE_NEON 335 def_bool y 336 337config FIX_EARLYCON_MEM 338 def_bool y 339 340config PGTABLE_LEVELS 341 int 342 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 343 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 344 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 345 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 346 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 347 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 348 349config ARCH_SUPPORTS_UPROBES 350 def_bool y 351 352config ARCH_PROC_KCORE_TEXT 353 def_bool y 354 355config BROKEN_GAS_INST 356 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 357 358config KASAN_SHADOW_OFFSET 359 hex 360 depends on KASAN_GENERIC || KASAN_SW_TAGS 361 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 362 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 363 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 364 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 365 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 366 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 367 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 368 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 369 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 370 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 371 default 0xffffffffffffffff 372 373source "arch/arm64/Kconfig.platforms" 374 375menu "Kernel Features" 376 377menu "ARM errata workarounds via the alternatives framework" 378 379config ARM64_WORKAROUND_CLEAN_CACHE 380 bool 381 382config ARM64_ERRATUM_826319 383 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 384 default y 385 select ARM64_WORKAROUND_CLEAN_CACHE 386 help 387 This option adds an alternative code sequence to work around ARM 388 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 389 AXI master interface and an L2 cache. 390 391 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 392 and is unable to accept a certain write via this interface, it will 393 not progress on read data presented on the read data channel and the 394 system can deadlock. 395 396 The workaround promotes data cache clean instructions to 397 data cache clean-and-invalidate. 398 Please note that this does not necessarily enable the workaround, 399 as it depends on the alternative framework, which will only patch 400 the kernel if an affected CPU is detected. 401 402 If unsure, say Y. 403 404config ARM64_ERRATUM_827319 405 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 406 default y 407 select ARM64_WORKAROUND_CLEAN_CACHE 408 help 409 This option adds an alternative code sequence to work around ARM 410 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 411 master interface and an L2 cache. 412 413 Under certain conditions this erratum can cause a clean line eviction 414 to occur at the same time as another transaction to the same address 415 on the AMBA 5 CHI interface, which can cause data corruption if the 416 interconnect reorders the two transactions. 417 418 The workaround promotes data cache clean instructions to 419 data cache clean-and-invalidate. 420 Please note that this does not necessarily enable the workaround, 421 as it depends on the alternative framework, which will only patch 422 the kernel if an affected CPU is detected. 423 424 If unsure, say Y. 425 426config ARM64_ERRATUM_824069 427 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 428 default y 429 select ARM64_WORKAROUND_CLEAN_CACHE 430 help 431 This option adds an alternative code sequence to work around ARM 432 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 433 to a coherent interconnect. 434 435 If a Cortex-A53 processor is executing a store or prefetch for 436 write instruction at the same time as a processor in another 437 cluster is executing a cache maintenance operation to the same 438 address, then this erratum might cause a clean cache line to be 439 incorrectly marked as dirty. 440 441 The workaround promotes data cache clean instructions to 442 data cache clean-and-invalidate. 443 Please note that this option does not necessarily enable the 444 workaround, as it depends on the alternative framework, which will 445 only patch the kernel if an affected CPU is detected. 446 447 If unsure, say Y. 448 449config ARM64_ERRATUM_819472 450 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 451 default y 452 select ARM64_WORKAROUND_CLEAN_CACHE 453 help 454 This option adds an alternative code sequence to work around ARM 455 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 456 present when it is connected to a coherent interconnect. 457 458 If the processor is executing a load and store exclusive sequence at 459 the same time as a processor in another cluster is executing a cache 460 maintenance operation to the same address, then this erratum might 461 cause data corruption. 462 463 The workaround promotes data cache clean instructions to 464 data cache clean-and-invalidate. 465 Please note that this does not necessarily enable the workaround, 466 as it depends on the alternative framework, which will only patch 467 the kernel if an affected CPU is detected. 468 469 If unsure, say Y. 470 471config ARM64_ERRATUM_832075 472 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 473 default y 474 help 475 This option adds an alternative code sequence to work around ARM 476 erratum 832075 on Cortex-A57 parts up to r1p2. 477 478 Affected Cortex-A57 parts might deadlock when exclusive load/store 479 instructions to Write-Back memory are mixed with Device loads. 480 481 The workaround is to promote device loads to use Load-Acquire 482 semantics. 483 Please note that this does not necessarily enable the workaround, 484 as it depends on the alternative framework, which will only patch 485 the kernel if an affected CPU is detected. 486 487 If unsure, say Y. 488 489config ARM64_ERRATUM_834220 490 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 491 depends on KVM 492 default y 493 help 494 This option adds an alternative code sequence to work around ARM 495 erratum 834220 on Cortex-A57 parts up to r1p2. 496 497 Affected Cortex-A57 parts might report a Stage 2 translation 498 fault as the result of a Stage 1 fault for load crossing a 499 page boundary when there is a permission or device memory 500 alignment fault at Stage 1 and a translation fault at Stage 2. 501 502 The workaround is to verify that the Stage 1 translation 503 doesn't generate a fault before handling the Stage 2 fault. 504 Please note that this does not necessarily enable the workaround, 505 as it depends on the alternative framework, which will only patch 506 the kernel if an affected CPU is detected. 507 508 If unsure, say Y. 509 510config ARM64_ERRATUM_1742098 511 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 512 depends on COMPAT 513 default y 514 help 515 This option removes the AES hwcap for aarch32 user-space to 516 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 517 518 Affected parts may corrupt the AES state if an interrupt is 519 taken between a pair of AES instructions. These instructions 520 are only present if the cryptography extensions are present. 521 All software should have a fallback implementation for CPUs 522 that don't implement the cryptography extensions. 523 524 If unsure, say Y. 525 526config ARM64_ERRATUM_845719 527 bool "Cortex-A53: 845719: a load might read incorrect data" 528 depends on COMPAT 529 default y 530 help 531 This option adds an alternative code sequence to work around ARM 532 erratum 845719 on Cortex-A53 parts up to r0p4. 533 534 When running a compat (AArch32) userspace on an affected Cortex-A53 535 part, a load at EL0 from a virtual address that matches the bottom 32 536 bits of the virtual address used by a recent load at (AArch64) EL1 537 might return incorrect data. 538 539 The workaround is to write the contextidr_el1 register on exception 540 return to a 32-bit task. 541 Please note that this does not necessarily enable the workaround, 542 as it depends on the alternative framework, which will only patch 543 the kernel if an affected CPU is detected. 544 545 If unsure, say Y. 546 547config ARM64_ERRATUM_843419 548 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 549 default y 550 select ARM64_MODULE_PLTS if MODULES 551 help 552 This option links the kernel with '--fix-cortex-a53-843419' and 553 enables PLT support to replace certain ADRP instructions, which can 554 cause subsequent memory accesses to use an incorrect address on 555 Cortex-A53 parts up to r0p4. 556 557 If unsure, say Y. 558 559config ARM64_LD_HAS_FIX_ERRATUM_843419 560 def_bool $(ld-option,--fix-cortex-a53-843419) 561 562config ARM64_ERRATUM_1024718 563 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 564 default y 565 help 566 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 567 568 Affected Cortex-A55 cores (all revisions) could cause incorrect 569 update of the hardware dirty bit when the DBM/AP bits are updated 570 without a break-before-make. The workaround is to disable the usage 571 of hardware DBM locally on the affected cores. CPUs not affected by 572 this erratum will continue to use the feature. 573 574 If unsure, say Y. 575 576config ARM64_ERRATUM_1418040 577 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 578 default y 579 depends on COMPAT 580 help 581 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 582 errata 1188873 and 1418040. 583 584 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 585 cause register corruption when accessing the timer registers 586 from AArch32 userspace. 587 588 If unsure, say Y. 589 590config ARM64_WORKAROUND_SPECULATIVE_AT 591 bool 592 593config ARM64_ERRATUM_1165522 594 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 595 default y 596 select ARM64_WORKAROUND_SPECULATIVE_AT 597 help 598 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 599 600 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 601 corrupted TLBs by speculating an AT instruction during a guest 602 context switch. 603 604 If unsure, say Y. 605 606config ARM64_ERRATUM_1319367 607 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 608 default y 609 select ARM64_WORKAROUND_SPECULATIVE_AT 610 help 611 This option adds work arounds for ARM Cortex-A57 erratum 1319537 612 and A72 erratum 1319367 613 614 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 615 speculating an AT instruction during a guest context switch. 616 617 If unsure, say Y. 618 619config ARM64_ERRATUM_1530923 620 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 621 default y 622 select ARM64_WORKAROUND_SPECULATIVE_AT 623 help 624 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 625 626 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 627 corrupted TLBs by speculating an AT instruction during a guest 628 context switch. 629 630 If unsure, say Y. 631 632config ARM64_WORKAROUND_REPEAT_TLBI 633 bool 634 635config ARM64_ERRATUM_2441007 636 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 637 default y 638 select ARM64_WORKAROUND_REPEAT_TLBI 639 help 640 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 641 642 Under very rare circumstances, affected Cortex-A55 CPUs 643 may not handle a race between a break-before-make sequence on one 644 CPU, and another CPU accessing the same page. This could allow a 645 store to a page that has been unmapped. 646 647 Work around this by adding the affected CPUs to the list that needs 648 TLB sequences to be done twice. 649 650 If unsure, say Y. 651 652config ARM64_ERRATUM_1286807 653 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 654 default y 655 select ARM64_WORKAROUND_REPEAT_TLBI 656 help 657 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 658 659 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 660 address for a cacheable mapping of a location is being 661 accessed by a core while another core is remapping the virtual 662 address to a new physical page using the recommended 663 break-before-make sequence, then under very rare circumstances 664 TLBI+DSB completes before a read using the translation being 665 invalidated has been observed by other observers. The 666 workaround repeats the TLBI+DSB operation. 667 668config ARM64_ERRATUM_1463225 669 bool "Cortex-A76: Software Step might prevent interrupt recognition" 670 default y 671 help 672 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 673 674 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 675 of a system call instruction (SVC) can prevent recognition of 676 subsequent interrupts when software stepping is disabled in the 677 exception handler of the system call and either kernel debugging 678 is enabled or VHE is in use. 679 680 Work around the erratum by triggering a dummy step exception 681 when handling a system call from a task that is being stepped 682 in a VHE configuration of the kernel. 683 684 If unsure, say Y. 685 686config ARM64_ERRATUM_1542419 687 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 688 default y 689 help 690 This option adds a workaround for ARM Neoverse-N1 erratum 691 1542419. 692 693 Affected Neoverse-N1 cores could execute a stale instruction when 694 modified by another CPU. The workaround depends on a firmware 695 counterpart. 696 697 Workaround the issue by hiding the DIC feature from EL0. This 698 forces user-space to perform cache maintenance. 699 700 If unsure, say Y. 701 702config ARM64_ERRATUM_1508412 703 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 704 default y 705 help 706 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 707 708 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 709 of a store-exclusive or read of PAR_EL1 and a load with device or 710 non-cacheable memory attributes. The workaround depends on a firmware 711 counterpart. 712 713 KVM guests must also have the workaround implemented or they can 714 deadlock the system. 715 716 Work around the issue by inserting DMB SY barriers around PAR_EL1 717 register reads and warning KVM users. The DMB barrier is sufficient 718 to prevent a speculative PAR_EL1 read. 719 720 If unsure, say Y. 721 722config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 723 bool 724 725config ARM64_ERRATUM_2051678 726 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 727 default y 728 help 729 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 730 Affected Cortex-A510 might not respect the ordering rules for 731 hardware update of the page table's dirty bit. The workaround 732 is to not enable the feature on affected CPUs. 733 734 If unsure, say Y. 735 736config ARM64_ERRATUM_2077057 737 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 738 default y 739 help 740 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 741 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 742 expected, but a Pointer Authentication trap is taken instead. The 743 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 744 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 745 746 This can only happen when EL2 is stepping EL1. 747 748 When these conditions occur, the SPSR_EL2 value is unchanged from the 749 previous guest entry, and can be restored from the in-memory copy. 750 751 If unsure, say Y. 752 753config ARM64_ERRATUM_2658417 754 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 755 default y 756 help 757 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 758 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 759 BFMMLA or VMMLA instructions in rare circumstances when a pair of 760 A510 CPUs are using shared neon hardware. As the sharing is not 761 discoverable by the kernel, hide the BF16 HWCAP to indicate that 762 user-space should not be using these instructions. 763 764 If unsure, say Y. 765 766config ARM64_ERRATUM_2119858 767 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 768 default y 769 depends on CORESIGHT_TRBE 770 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 771 help 772 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 773 774 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 775 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 776 the event of a WRAP event. 777 778 Work around the issue by always making sure we move the TRBPTR_EL1 by 779 256 bytes before enabling the buffer and filling the first 256 bytes of 780 the buffer with ETM ignore packets upon disabling. 781 782 If unsure, say Y. 783 784config ARM64_ERRATUM_2139208 785 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 786 default y 787 depends on CORESIGHT_TRBE 788 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 789 help 790 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 791 792 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 793 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 794 the event of a WRAP event. 795 796 Work around the issue by always making sure we move the TRBPTR_EL1 by 797 256 bytes before enabling the buffer and filling the first 256 bytes of 798 the buffer with ETM ignore packets upon disabling. 799 800 If unsure, say Y. 801 802config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 803 bool 804 805config ARM64_ERRATUM_2054223 806 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 807 default y 808 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 809 help 810 Enable workaround for ARM Cortex-A710 erratum 2054223 811 812 Affected cores may fail to flush the trace data on a TSB instruction, when 813 the PE is in trace prohibited state. This will cause losing a few bytes 814 of the trace cached. 815 816 Workaround is to issue two TSB consecutively on affected cores. 817 818 If unsure, say Y. 819 820config ARM64_ERRATUM_2067961 821 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 822 default y 823 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 824 help 825 Enable workaround for ARM Neoverse-N2 erratum 2067961 826 827 Affected cores may fail to flush the trace data on a TSB instruction, when 828 the PE is in trace prohibited state. This will cause losing a few bytes 829 of the trace cached. 830 831 Workaround is to issue two TSB consecutively on affected cores. 832 833 If unsure, say Y. 834 835config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 836 bool 837 838config ARM64_ERRATUM_2253138 839 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 840 depends on CORESIGHT_TRBE 841 default y 842 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 843 help 844 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 845 846 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 847 for TRBE. Under some conditions, the TRBE might generate a write to the next 848 virtually addressed page following the last page of the TRBE address space 849 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 850 851 Work around this in the driver by always making sure that there is a 852 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 853 854 If unsure, say Y. 855 856config ARM64_ERRATUM_2224489 857 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 858 depends on CORESIGHT_TRBE 859 default y 860 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 861 help 862 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 863 864 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 865 for TRBE. Under some conditions, the TRBE might generate a write to the next 866 virtually addressed page following the last page of the TRBE address space 867 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 868 869 Work around this in the driver by always making sure that there is a 870 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 871 872 If unsure, say Y. 873 874config ARM64_ERRATUM_2441009 875 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 876 default y 877 select ARM64_WORKAROUND_REPEAT_TLBI 878 help 879 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 880 881 Under very rare circumstances, affected Cortex-A510 CPUs 882 may not handle a race between a break-before-make sequence on one 883 CPU, and another CPU accessing the same page. This could allow a 884 store to a page that has been unmapped. 885 886 Work around this by adding the affected CPUs to the list that needs 887 TLB sequences to be done twice. 888 889 If unsure, say Y. 890 891config ARM64_ERRATUM_2064142 892 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 893 depends on CORESIGHT_TRBE 894 default y 895 help 896 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 897 898 Affected Cortex-A510 core might fail to write into system registers after the 899 TRBE has been disabled. Under some conditions after the TRBE has been disabled 900 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 901 and TRBTRG_EL1 will be ignored and will not be effected. 902 903 Work around this in the driver by executing TSB CSYNC and DSB after collection 904 is stopped and before performing a system register write to one of the affected 905 registers. 906 907 If unsure, say Y. 908 909config ARM64_ERRATUM_2038923 910 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 911 depends on CORESIGHT_TRBE 912 default y 913 help 914 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 915 916 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 917 prohibited within the CPU. As a result, the trace buffer or trace buffer state 918 might be corrupted. This happens after TRBE buffer has been enabled by setting 919 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 920 execution changes from a context, in which trace is prohibited to one where it 921 isn't, or vice versa. In these mentioned conditions, the view of whether trace 922 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 923 the trace buffer state might be corrupted. 924 925 Work around this in the driver by preventing an inconsistent view of whether the 926 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 927 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 928 two ISB instructions if no ERET is to take place. 929 930 If unsure, say Y. 931 932config ARM64_ERRATUM_1902691 933 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 934 depends on CORESIGHT_TRBE 935 default y 936 help 937 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 938 939 Affected Cortex-A510 core might cause trace data corruption, when being written 940 into the memory. Effectively TRBE is broken and hence cannot be used to capture 941 trace data. 942 943 Work around this problem in the driver by just preventing TRBE initialization on 944 affected cpus. The firmware must have disabled the access to TRBE for the kernel 945 on such implementations. This will cover the kernel for any firmware that doesn't 946 do this already. 947 948 If unsure, say Y. 949 950config ARM64_ERRATUM_2457168 951 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 952 depends on ARM64_AMU_EXTN 953 default y 954 help 955 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 956 957 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 958 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 959 incorrectly giving a significantly higher output value. 960 961 Work around this problem by returning 0 when reading the affected counter in 962 key locations that results in disabling all users of this counter. This effect 963 is the same to firmware disabling affected counters. 964 965 If unsure, say Y. 966 967config CAVIUM_ERRATUM_22375 968 bool "Cavium erratum 22375, 24313" 969 default y 970 help 971 Enable workaround for errata 22375 and 24313. 972 973 This implements two gicv3-its errata workarounds for ThunderX. Both 974 with a small impact affecting only ITS table allocation. 975 976 erratum 22375: only alloc 8MB table size 977 erratum 24313: ignore memory access type 978 979 The fixes are in ITS initialization and basically ignore memory access 980 type and table size provided by the TYPER and BASER registers. 981 982 If unsure, say Y. 983 984config CAVIUM_ERRATUM_23144 985 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 986 depends on NUMA 987 default y 988 help 989 ITS SYNC command hang for cross node io and collections/cpu mapping. 990 991 If unsure, say Y. 992 993config CAVIUM_ERRATUM_23154 994 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 995 default y 996 help 997 The ThunderX GICv3 implementation requires a modified version for 998 reading the IAR status to ensure data synchronization 999 (access to icc_iar1_el1 is not sync'ed before and after). 1000 1001 It also suffers from erratum 38545 (also present on Marvell's 1002 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1003 spuriously presented to the CPU interface. 1004 1005 If unsure, say Y. 1006 1007config CAVIUM_ERRATUM_27456 1008 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1009 default y 1010 help 1011 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1012 instructions may cause the icache to become corrupted if it 1013 contains data for a non-current ASID. The fix is to 1014 invalidate the icache when changing the mm context. 1015 1016 If unsure, say Y. 1017 1018config CAVIUM_ERRATUM_30115 1019 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1020 default y 1021 help 1022 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1023 1.2, and T83 Pass 1.0, KVM guest execution may disable 1024 interrupts in host. Trapping both GICv3 group-0 and group-1 1025 accesses sidesteps the issue. 1026 1027 If unsure, say Y. 1028 1029config CAVIUM_TX2_ERRATUM_219 1030 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1031 default y 1032 help 1033 On Cavium ThunderX2, a load, store or prefetch instruction between a 1034 TTBR update and the corresponding context synchronizing operation can 1035 cause a spurious Data Abort to be delivered to any hardware thread in 1036 the CPU core. 1037 1038 Work around the issue by avoiding the problematic code sequence and 1039 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1040 trap handler performs the corresponding register access, skips the 1041 instruction and ensures context synchronization by virtue of the 1042 exception return. 1043 1044 If unsure, say Y. 1045 1046config FUJITSU_ERRATUM_010001 1047 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1048 default y 1049 help 1050 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1051 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1052 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1053 This fault occurs under a specific hardware condition when a 1054 load/store instruction performs an address translation using: 1055 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1056 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1057 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1058 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1059 1060 The workaround is to ensure these bits are clear in TCR_ELx. 1061 The workaround only affects the Fujitsu-A64FX. 1062 1063 If unsure, say Y. 1064 1065config HISILICON_ERRATUM_161600802 1066 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1067 default y 1068 help 1069 The HiSilicon Hip07 SoC uses the wrong redistributor base 1070 when issued ITS commands such as VMOVP and VMAPP, and requires 1071 a 128kB offset to be applied to the target address in this commands. 1072 1073 If unsure, say Y. 1074 1075config QCOM_FALKOR_ERRATUM_1003 1076 bool "Falkor E1003: Incorrect translation due to ASID change" 1077 default y 1078 help 1079 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1080 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1081 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1082 then only for entries in the walk cache, since the leaf translation 1083 is unchanged. Work around the erratum by invalidating the walk cache 1084 entries for the trampoline before entering the kernel proper. 1085 1086config QCOM_FALKOR_ERRATUM_1009 1087 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1088 default y 1089 select ARM64_WORKAROUND_REPEAT_TLBI 1090 help 1091 On Falkor v1, the CPU may prematurely complete a DSB following a 1092 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1093 one more time to fix the issue. 1094 1095 If unsure, say Y. 1096 1097config QCOM_QDF2400_ERRATUM_0065 1098 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1099 default y 1100 help 1101 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1102 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1103 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1104 1105 If unsure, say Y. 1106 1107config QCOM_FALKOR_ERRATUM_E1041 1108 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1109 default y 1110 help 1111 Falkor CPU may speculatively fetch instructions from an improper 1112 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1113 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1114 1115 If unsure, say Y. 1116 1117config NVIDIA_CARMEL_CNP_ERRATUM 1118 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1119 default y 1120 help 1121 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1122 invalidate shared TLB entries installed by a different core, as it would 1123 on standard ARM cores. 1124 1125 If unsure, say Y. 1126 1127config SOCIONEXT_SYNQUACER_PREITS 1128 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1129 default y 1130 help 1131 Socionext Synquacer SoCs implement a separate h/w block to generate 1132 MSI doorbell writes with non-zero values for the device ID. 1133 1134 If unsure, say Y. 1135 1136endmenu # "ARM errata workarounds via the alternatives framework" 1137 1138choice 1139 prompt "Page size" 1140 default ARM64_4K_PAGES 1141 help 1142 Page size (translation granule) configuration. 1143 1144config ARM64_4K_PAGES 1145 bool "4KB" 1146 help 1147 This feature enables 4KB pages support. 1148 1149config ARM64_16K_PAGES 1150 bool "16KB" 1151 help 1152 The system will use 16KB pages support. AArch32 emulation 1153 requires applications compiled with 16K (or a multiple of 16K) 1154 aligned segments. 1155 1156config ARM64_64K_PAGES 1157 bool "64KB" 1158 help 1159 This feature enables 64KB pages support (4KB by default) 1160 allowing only two levels of page tables and faster TLB 1161 look-up. AArch32 emulation requires applications compiled 1162 with 64K aligned segments. 1163 1164endchoice 1165 1166choice 1167 prompt "Virtual address space size" 1168 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1169 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1170 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1171 help 1172 Allows choosing one of multiple possible virtual address 1173 space sizes. The level of translation table is determined by 1174 a combination of page size and virtual address space size. 1175 1176config ARM64_VA_BITS_36 1177 bool "36-bit" if EXPERT 1178 depends on ARM64_16K_PAGES 1179 1180config ARM64_VA_BITS_39 1181 bool "39-bit" 1182 depends on ARM64_4K_PAGES 1183 1184config ARM64_VA_BITS_42 1185 bool "42-bit" 1186 depends on ARM64_64K_PAGES 1187 1188config ARM64_VA_BITS_47 1189 bool "47-bit" 1190 depends on ARM64_16K_PAGES 1191 1192config ARM64_VA_BITS_48 1193 bool "48-bit" 1194 1195config ARM64_VA_BITS_52 1196 bool "52-bit" 1197 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1198 help 1199 Enable 52-bit virtual addressing for userspace when explicitly 1200 requested via a hint to mmap(). The kernel will also use 52-bit 1201 virtual addresses for its own mappings (provided HW support for 1202 this feature is available, otherwise it reverts to 48-bit). 1203 1204 NOTE: Enabling 52-bit virtual addressing in conjunction with 1205 ARMv8.3 Pointer Authentication will result in the PAC being 1206 reduced from 7 bits to 3 bits, which may have a significant 1207 impact on its susceptibility to brute-force attacks. 1208 1209 If unsure, select 48-bit virtual addressing instead. 1210 1211endchoice 1212 1213config ARM64_FORCE_52BIT 1214 bool "Force 52-bit virtual addresses for userspace" 1215 depends on ARM64_VA_BITS_52 && EXPERT 1216 help 1217 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1218 to maintain compatibility with older software by providing 48-bit VAs 1219 unless a hint is supplied to mmap. 1220 1221 This configuration option disables the 48-bit compatibility logic, and 1222 forces all userspace addresses to be 52-bit on HW that supports it. One 1223 should only enable this configuration option for stress testing userspace 1224 memory management code. If unsure say N here. 1225 1226config ARM64_VA_BITS 1227 int 1228 default 36 if ARM64_VA_BITS_36 1229 default 39 if ARM64_VA_BITS_39 1230 default 42 if ARM64_VA_BITS_42 1231 default 47 if ARM64_VA_BITS_47 1232 default 48 if ARM64_VA_BITS_48 1233 default 52 if ARM64_VA_BITS_52 1234 1235choice 1236 prompt "Physical address space size" 1237 default ARM64_PA_BITS_48 1238 help 1239 Choose the maximum physical address range that the kernel will 1240 support. 1241 1242config ARM64_PA_BITS_48 1243 bool "48-bit" 1244 1245config ARM64_PA_BITS_52 1246 bool "52-bit (ARMv8.2)" 1247 depends on ARM64_64K_PAGES 1248 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1249 help 1250 Enable support for a 52-bit physical address space, introduced as 1251 part of the ARMv8.2-LPA extension. 1252 1253 With this enabled, the kernel will also continue to work on CPUs that 1254 do not support ARMv8.2-LPA, but with some added memory overhead (and 1255 minor performance overhead). 1256 1257endchoice 1258 1259config ARM64_PA_BITS 1260 int 1261 default 48 if ARM64_PA_BITS_48 1262 default 52 if ARM64_PA_BITS_52 1263 1264choice 1265 prompt "Endianness" 1266 default CPU_LITTLE_ENDIAN 1267 help 1268 Select the endianness of data accesses performed by the CPU. Userspace 1269 applications will need to be compiled and linked for the endianness 1270 that is selected here. 1271 1272config CPU_BIG_ENDIAN 1273 bool "Build big-endian kernel" 1274 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1275 help 1276 Say Y if you plan on running a kernel with a big-endian userspace. 1277 1278config CPU_LITTLE_ENDIAN 1279 bool "Build little-endian kernel" 1280 help 1281 Say Y if you plan on running a kernel with a little-endian userspace. 1282 This is usually the case for distributions targeting arm64. 1283 1284endchoice 1285 1286config SCHED_MC 1287 bool "Multi-core scheduler support" 1288 help 1289 Multi-core scheduler support improves the CPU scheduler's decision 1290 making when dealing with multi-core CPU chips at a cost of slightly 1291 increased overhead in some places. If unsure say N here. 1292 1293config SCHED_CLUSTER 1294 bool "Cluster scheduler support" 1295 help 1296 Cluster scheduler support improves the CPU scheduler's decision 1297 making when dealing with machines that have clusters of CPUs. 1298 Cluster usually means a couple of CPUs which are placed closely 1299 by sharing mid-level caches, last-level cache tags or internal 1300 busses. 1301 1302config SCHED_SMT 1303 bool "SMT scheduler support" 1304 help 1305 Improves the CPU scheduler's decision making when dealing with 1306 MultiThreading at a cost of slightly increased overhead in some 1307 places. If unsure say N here. 1308 1309config NR_CPUS 1310 int "Maximum number of CPUs (2-4096)" 1311 range 2 4096 1312 default "256" 1313 1314config HOTPLUG_CPU 1315 bool "Support for hot-pluggable CPUs" 1316 select GENERIC_IRQ_MIGRATION 1317 help 1318 Say Y here to experiment with turning CPUs off and on. CPUs 1319 can be controlled through /sys/devices/system/cpu. 1320 1321# Common NUMA Features 1322config NUMA 1323 bool "NUMA Memory Allocation and Scheduler Support" 1324 select GENERIC_ARCH_NUMA 1325 select ACPI_NUMA if ACPI 1326 select OF_NUMA 1327 select HAVE_SETUP_PER_CPU_AREA 1328 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1329 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1330 select USE_PERCPU_NUMA_NODE_ID 1331 help 1332 Enable NUMA (Non-Uniform Memory Access) support. 1333 1334 The kernel will try to allocate memory used by a CPU on the 1335 local memory of the CPU and add some more 1336 NUMA awareness to the kernel. 1337 1338config NODES_SHIFT 1339 int "Maximum NUMA Nodes (as a power of 2)" 1340 range 1 10 1341 default "4" 1342 depends on NUMA 1343 help 1344 Specify the maximum number of NUMA Nodes available on the target 1345 system. Increases memory reserved to accommodate various tables. 1346 1347source "kernel/Kconfig.hz" 1348 1349config ARCH_SPARSEMEM_ENABLE 1350 def_bool y 1351 select SPARSEMEM_VMEMMAP_ENABLE 1352 select SPARSEMEM_VMEMMAP 1353 1354config HW_PERF_EVENTS 1355 def_bool y 1356 depends on ARM_PMU 1357 1358# Supported by clang >= 7.0 or GCC >= 12.0.0 1359config CC_HAVE_SHADOW_CALL_STACK 1360 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1361 1362config PARAVIRT 1363 bool "Enable paravirtualization code" 1364 help 1365 This changes the kernel so it can modify itself when it is run 1366 under a hypervisor, potentially improving performance significantly 1367 over full virtualization. 1368 1369config PARAVIRT_TIME_ACCOUNTING 1370 bool "Paravirtual steal time accounting" 1371 select PARAVIRT 1372 help 1373 Select this option to enable fine granularity task steal time 1374 accounting. Time spent executing other tasks in parallel with 1375 the current vCPU is discounted from the vCPU power. To account for 1376 that, there can be a small performance impact. 1377 1378 If in doubt, say N here. 1379 1380config KEXEC 1381 depends on PM_SLEEP_SMP 1382 select KEXEC_CORE 1383 bool "kexec system call" 1384 help 1385 kexec is a system call that implements the ability to shutdown your 1386 current kernel, and to start another kernel. It is like a reboot 1387 but it is independent of the system firmware. And like a reboot 1388 you can start any kernel with it, not just Linux. 1389 1390config KEXEC_FILE 1391 bool "kexec file based system call" 1392 select KEXEC_CORE 1393 select HAVE_IMA_KEXEC if IMA 1394 help 1395 This is new version of kexec system call. This system call is 1396 file based and takes file descriptors as system call argument 1397 for kernel and initramfs as opposed to list of segments as 1398 accepted by previous system call. 1399 1400config KEXEC_SIG 1401 bool "Verify kernel signature during kexec_file_load() syscall" 1402 depends on KEXEC_FILE 1403 help 1404 Select this option to verify a signature with loaded kernel 1405 image. If configured, any attempt of loading a image without 1406 valid signature will fail. 1407 1408 In addition to that option, you need to enable signature 1409 verification for the corresponding kernel image type being 1410 loaded in order for this to work. 1411 1412config KEXEC_IMAGE_VERIFY_SIG 1413 bool "Enable Image signature verification support" 1414 default y 1415 depends on KEXEC_SIG 1416 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1417 help 1418 Enable Image signature verification support. 1419 1420comment "Support for PE file signature verification disabled" 1421 depends on KEXEC_SIG 1422 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1423 1424config CRASH_DUMP 1425 bool "Build kdump crash kernel" 1426 help 1427 Generate crash dump after being started by kexec. This should 1428 be normally only set in special crash dump kernels which are 1429 loaded in the main kernel with kexec-tools into a specially 1430 reserved region and then later executed after a crash by 1431 kdump/kexec. 1432 1433 For more details see Documentation/admin-guide/kdump/kdump.rst 1434 1435config TRANS_TABLE 1436 def_bool y 1437 depends on HIBERNATION || KEXEC_CORE 1438 1439config XEN_DOM0 1440 def_bool y 1441 depends on XEN 1442 1443config XEN 1444 bool "Xen guest support on ARM64" 1445 depends on ARM64 && OF 1446 select SWIOTLB_XEN 1447 select PARAVIRT 1448 help 1449 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1450 1451config ARCH_FORCE_MAX_ORDER 1452 int 1453 default "14" if ARM64_64K_PAGES 1454 default "12" if ARM64_16K_PAGES 1455 default "11" 1456 help 1457 The kernel memory allocator divides physically contiguous memory 1458 blocks into "zones", where each zone is a power of two number of 1459 pages. This option selects the largest power of two that the kernel 1460 keeps in the memory allocator. If you need to allocate very large 1461 blocks of physically contiguous memory, then you may need to 1462 increase this value. 1463 1464 This config option is actually maximum order plus one. For example, 1465 a value of 11 means that the largest free memory block is 2^10 pages. 1466 1467 We make sure that we can allocate upto a HugePage size for each configuration. 1468 Hence we have : 1469 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1470 1471 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1472 4M allocations matching the default size used by generic code. 1473 1474config UNMAP_KERNEL_AT_EL0 1475 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1476 default y 1477 help 1478 Speculation attacks against some high-performance processors can 1479 be used to bypass MMU permission checks and leak kernel data to 1480 userspace. This can be defended against by unmapping the kernel 1481 when running in userspace, mapping it back in on exception entry 1482 via a trampoline page in the vector table. 1483 1484 If unsure, say Y. 1485 1486config MITIGATE_SPECTRE_BRANCH_HISTORY 1487 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1488 default y 1489 help 1490 Speculation attacks against some high-performance processors can 1491 make use of branch history to influence future speculation. 1492 When taking an exception from user-space, a sequence of branches 1493 or a firmware call overwrites the branch history. 1494 1495config RODATA_FULL_DEFAULT_ENABLED 1496 bool "Apply r/o permissions of VM areas also to their linear aliases" 1497 default y 1498 help 1499 Apply read-only attributes of VM areas to the linear alias of 1500 the backing pages as well. This prevents code or read-only data 1501 from being modified (inadvertently or intentionally) via another 1502 mapping of the same memory page. This additional enhancement can 1503 be turned off at runtime by passing rodata=[off|on] (and turned on 1504 with rodata=full if this option is set to 'n') 1505 1506 This requires the linear region to be mapped down to pages, 1507 which may adversely affect performance in some cases. 1508 1509config ARM64_SW_TTBR0_PAN 1510 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1511 help 1512 Enabling this option prevents the kernel from accessing 1513 user-space memory directly by pointing TTBR0_EL1 to a reserved 1514 zeroed area and reserved ASID. The user access routines 1515 restore the valid TTBR0_EL1 temporarily. 1516 1517config ARM64_TAGGED_ADDR_ABI 1518 bool "Enable the tagged user addresses syscall ABI" 1519 default y 1520 help 1521 When this option is enabled, user applications can opt in to a 1522 relaxed ABI via prctl() allowing tagged addresses to be passed 1523 to system calls as pointer arguments. For details, see 1524 Documentation/arm64/tagged-address-abi.rst. 1525 1526menuconfig COMPAT 1527 bool "Kernel support for 32-bit EL0" 1528 depends on ARM64_4K_PAGES || EXPERT 1529 select HAVE_UID16 1530 select OLD_SIGSUSPEND3 1531 select COMPAT_OLD_SIGACTION 1532 help 1533 This option enables support for a 32-bit EL0 running under a 64-bit 1534 kernel at EL1. AArch32-specific components such as system calls, 1535 the user helper functions, VFP support and the ptrace interface are 1536 handled appropriately by the kernel. 1537 1538 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1539 that you will only be able to execute AArch32 binaries that were compiled 1540 with page size aligned segments. 1541 1542 If you want to execute 32-bit userspace applications, say Y. 1543 1544if COMPAT 1545 1546config KUSER_HELPERS 1547 bool "Enable kuser helpers page for 32-bit applications" 1548 default y 1549 help 1550 Warning: disabling this option may break 32-bit user programs. 1551 1552 Provide kuser helpers to compat tasks. The kernel provides 1553 helper code to userspace in read only form at a fixed location 1554 to allow userspace to be independent of the CPU type fitted to 1555 the system. This permits binaries to be run on ARMv4 through 1556 to ARMv8 without modification. 1557 1558 See Documentation/arm/kernel_user_helpers.rst for details. 1559 1560 However, the fixed address nature of these helpers can be used 1561 by ROP (return orientated programming) authors when creating 1562 exploits. 1563 1564 If all of the binaries and libraries which run on your platform 1565 are built specifically for your platform, and make no use of 1566 these helpers, then you can turn this option off to hinder 1567 such exploits. However, in that case, if a binary or library 1568 relying on those helpers is run, it will not function correctly. 1569 1570 Say N here only if you are absolutely certain that you do not 1571 need these helpers; otherwise, the safe option is to say Y. 1572 1573config COMPAT_VDSO 1574 bool "Enable vDSO for 32-bit applications" 1575 depends on !CPU_BIG_ENDIAN 1576 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1577 select GENERIC_COMPAT_VDSO 1578 default y 1579 help 1580 Place in the process address space of 32-bit applications an 1581 ELF shared object providing fast implementations of gettimeofday 1582 and clock_gettime. 1583 1584 You must have a 32-bit build of glibc 2.22 or later for programs 1585 to seamlessly take advantage of this. 1586 1587config THUMB2_COMPAT_VDSO 1588 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1589 depends on COMPAT_VDSO 1590 default y 1591 help 1592 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1593 otherwise with '-marm'. 1594 1595config COMPAT_ALIGNMENT_FIXUPS 1596 bool "Fix up misaligned multi-word loads and stores in user space" 1597 1598menuconfig ARMV8_DEPRECATED 1599 bool "Emulate deprecated/obsolete ARMv8 instructions" 1600 depends on SYSCTL 1601 help 1602 Legacy software support may require certain instructions 1603 that have been deprecated or obsoleted in the architecture. 1604 1605 Enable this config to enable selective emulation of these 1606 features. 1607 1608 If unsure, say Y 1609 1610if ARMV8_DEPRECATED 1611 1612config SWP_EMULATION 1613 bool "Emulate SWP/SWPB instructions" 1614 help 1615 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1616 they are always undefined. Say Y here to enable software 1617 emulation of these instructions for userspace using LDXR/STXR. 1618 This feature can be controlled at runtime with the abi.swp 1619 sysctl which is disabled by default. 1620 1621 In some older versions of glibc [<=2.8] SWP is used during futex 1622 trylock() operations with the assumption that the code will not 1623 be preempted. This invalid assumption may be more likely to fail 1624 with SWP emulation enabled, leading to deadlock of the user 1625 application. 1626 1627 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1628 on an external transaction monitoring block called a global 1629 monitor to maintain update atomicity. If your system does not 1630 implement a global monitor, this option can cause programs that 1631 perform SWP operations to uncached memory to deadlock. 1632 1633 If unsure, say Y 1634 1635config CP15_BARRIER_EMULATION 1636 bool "Emulate CP15 Barrier instructions" 1637 help 1638 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1639 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1640 strongly recommended to use the ISB, DSB, and DMB 1641 instructions instead. 1642 1643 Say Y here to enable software emulation of these 1644 instructions for AArch32 userspace code. When this option is 1645 enabled, CP15 barrier usage is traced which can help 1646 identify software that needs updating. This feature can be 1647 controlled at runtime with the abi.cp15_barrier sysctl. 1648 1649 If unsure, say Y 1650 1651config SETEND_EMULATION 1652 bool "Emulate SETEND instruction" 1653 help 1654 The SETEND instruction alters the data-endianness of the 1655 AArch32 EL0, and is deprecated in ARMv8. 1656 1657 Say Y here to enable software emulation of the instruction 1658 for AArch32 userspace code. This feature can be controlled 1659 at runtime with the abi.setend sysctl. 1660 1661 Note: All the cpus on the system must have mixed endian support at EL0 1662 for this feature to be enabled. If a new CPU - which doesn't support mixed 1663 endian - is hotplugged in after this feature has been enabled, there could 1664 be unexpected results in the applications. 1665 1666 If unsure, say Y 1667endif # ARMV8_DEPRECATED 1668 1669endif # COMPAT 1670 1671menu "ARMv8.1 architectural features" 1672 1673config ARM64_HW_AFDBM 1674 bool "Support for hardware updates of the Access and Dirty page flags" 1675 default y 1676 help 1677 The ARMv8.1 architecture extensions introduce support for 1678 hardware updates of the access and dirty information in page 1679 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1680 capable processors, accesses to pages with PTE_AF cleared will 1681 set this bit instead of raising an access flag fault. 1682 Similarly, writes to read-only pages with the DBM bit set will 1683 clear the read-only bit (AP[2]) instead of raising a 1684 permission fault. 1685 1686 Kernels built with this configuration option enabled continue 1687 to work on pre-ARMv8.1 hardware and the performance impact is 1688 minimal. If unsure, say Y. 1689 1690config ARM64_PAN 1691 bool "Enable support for Privileged Access Never (PAN)" 1692 default y 1693 help 1694 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1695 prevents the kernel or hypervisor from accessing user-space (EL0) 1696 memory directly. 1697 1698 Choosing this option will cause any unprotected (not using 1699 copy_to_user et al) memory access to fail with a permission fault. 1700 1701 The feature is detected at runtime, and will remain as a 'nop' 1702 instruction if the cpu does not implement the feature. 1703 1704config AS_HAS_LDAPR 1705 def_bool $(as-instr,.arch_extension rcpc) 1706 1707config AS_HAS_LSE_ATOMICS 1708 def_bool $(as-instr,.arch_extension lse) 1709 1710config ARM64_LSE_ATOMICS 1711 bool 1712 default ARM64_USE_LSE_ATOMICS 1713 depends on AS_HAS_LSE_ATOMICS 1714 1715config ARM64_USE_LSE_ATOMICS 1716 bool "Atomic instructions" 1717 depends on JUMP_LABEL 1718 default y 1719 help 1720 As part of the Large System Extensions, ARMv8.1 introduces new 1721 atomic instructions that are designed specifically to scale in 1722 very large systems. 1723 1724 Say Y here to make use of these instructions for the in-kernel 1725 atomic routines. This incurs a small overhead on CPUs that do 1726 not support these instructions and requires the kernel to be 1727 built with binutils >= 2.25 in order for the new instructions 1728 to be used. 1729 1730endmenu # "ARMv8.1 architectural features" 1731 1732menu "ARMv8.2 architectural features" 1733 1734config AS_HAS_ARMV8_2 1735 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1736 1737config AS_HAS_SHA3 1738 def_bool $(as-instr,.arch armv8.2-a+sha3) 1739 1740config ARM64_PMEM 1741 bool "Enable support for persistent memory" 1742 select ARCH_HAS_PMEM_API 1743 select ARCH_HAS_UACCESS_FLUSHCACHE 1744 help 1745 Say Y to enable support for the persistent memory API based on the 1746 ARMv8.2 DCPoP feature. 1747 1748 The feature is detected at runtime, and the kernel will use DC CVAC 1749 operations if DC CVAP is not supported (following the behaviour of 1750 DC CVAP itself if the system does not define a point of persistence). 1751 1752config ARM64_RAS_EXTN 1753 bool "Enable support for RAS CPU Extensions" 1754 default y 1755 help 1756 CPUs that support the Reliability, Availability and Serviceability 1757 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1758 errors, classify them and report them to software. 1759 1760 On CPUs with these extensions system software can use additional 1761 barriers to determine if faults are pending and read the 1762 classification from a new set of registers. 1763 1764 Selecting this feature will allow the kernel to use these barriers 1765 and access the new registers if the system supports the extension. 1766 Platform RAS features may additionally depend on firmware support. 1767 1768config ARM64_CNP 1769 bool "Enable support for Common Not Private (CNP) translations" 1770 default y 1771 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1772 help 1773 Common Not Private (CNP) allows translation table entries to 1774 be shared between different PEs in the same inner shareable 1775 domain, so the hardware can use this fact to optimise the 1776 caching of such entries in the TLB. 1777 1778 Selecting this option allows the CNP feature to be detected 1779 at runtime, and does not affect PEs that do not implement 1780 this feature. 1781 1782endmenu # "ARMv8.2 architectural features" 1783 1784menu "ARMv8.3 architectural features" 1785 1786config ARM64_PTR_AUTH 1787 bool "Enable support for pointer authentication" 1788 default y 1789 help 1790 Pointer authentication (part of the ARMv8.3 Extensions) provides 1791 instructions for signing and authenticating pointers against secret 1792 keys, which can be used to mitigate Return Oriented Programming (ROP) 1793 and other attacks. 1794 1795 This option enables these instructions at EL0 (i.e. for userspace). 1796 Choosing this option will cause the kernel to initialise secret keys 1797 for each process at exec() time, with these keys being 1798 context-switched along with the process. 1799 1800 The feature is detected at runtime. If the feature is not present in 1801 hardware it will not be advertised to userspace/KVM guest nor will it 1802 be enabled. 1803 1804 If the feature is present on the boot CPU but not on a late CPU, then 1805 the late CPU will be parked. Also, if the boot CPU does not have 1806 address auth and the late CPU has then the late CPU will still boot 1807 but with the feature disabled. On such a system, this option should 1808 not be selected. 1809 1810config ARM64_PTR_AUTH_KERNEL 1811 bool "Use pointer authentication for kernel" 1812 default y 1813 depends on ARM64_PTR_AUTH 1814 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1815 # Modern compilers insert a .note.gnu.property section note for PAC 1816 # which is only understood by binutils starting with version 2.33.1. 1817 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1818 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1819 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1820 help 1821 If the compiler supports the -mbranch-protection or 1822 -msign-return-address flag (e.g. GCC 7 or later), then this option 1823 will cause the kernel itself to be compiled with return address 1824 protection. In this case, and if the target hardware is known to 1825 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1826 disabled with minimal loss of protection. 1827 1828 This feature works with FUNCTION_GRAPH_TRACER option only if 1829 DYNAMIC_FTRACE_WITH_REGS is enabled. 1830 1831config CC_HAS_BRANCH_PROT_PAC_RET 1832 # GCC 9 or later, clang 8 or later 1833 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1834 1835config CC_HAS_SIGN_RETURN_ADDRESS 1836 # GCC 7, 8 1837 def_bool $(cc-option,-msign-return-address=all) 1838 1839config AS_HAS_PAC 1840 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1841 1842config AS_HAS_CFI_NEGATE_RA_STATE 1843 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1844 1845endmenu # "ARMv8.3 architectural features" 1846 1847menu "ARMv8.4 architectural features" 1848 1849config ARM64_AMU_EXTN 1850 bool "Enable support for the Activity Monitors Unit CPU extension" 1851 default y 1852 help 1853 The activity monitors extension is an optional extension introduced 1854 by the ARMv8.4 CPU architecture. This enables support for version 1 1855 of the activity monitors architecture, AMUv1. 1856 1857 To enable the use of this extension on CPUs that implement it, say Y. 1858 1859 Note that for architectural reasons, firmware _must_ implement AMU 1860 support when running on CPUs that present the activity monitors 1861 extension. The required support is present in: 1862 * Version 1.5 and later of the ARM Trusted Firmware 1863 1864 For kernels that have this configuration enabled but boot with broken 1865 firmware, you may need to say N here until the firmware is fixed. 1866 Otherwise you may experience firmware panics or lockups when 1867 accessing the counter registers. Even if you are not observing these 1868 symptoms, the values returned by the register reads might not 1869 correctly reflect reality. Most commonly, the value read will be 0, 1870 indicating that the counter is not enabled. 1871 1872config AS_HAS_ARMV8_4 1873 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1874 1875config ARM64_TLB_RANGE 1876 bool "Enable support for tlbi range feature" 1877 default y 1878 depends on AS_HAS_ARMV8_4 1879 help 1880 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1881 range of input addresses. 1882 1883 The feature introduces new assembly instructions, and they were 1884 support when binutils >= 2.30. 1885 1886endmenu # "ARMv8.4 architectural features" 1887 1888menu "ARMv8.5 architectural features" 1889 1890config AS_HAS_ARMV8_5 1891 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1892 1893config ARM64_BTI 1894 bool "Branch Target Identification support" 1895 default y 1896 help 1897 Branch Target Identification (part of the ARMv8.5 Extensions) 1898 provides a mechanism to limit the set of locations to which computed 1899 branch instructions such as BR or BLR can jump. 1900 1901 To make use of BTI on CPUs that support it, say Y. 1902 1903 BTI is intended to provide complementary protection to other control 1904 flow integrity protection mechanisms, such as the Pointer 1905 authentication mechanism provided as part of the ARMv8.3 Extensions. 1906 For this reason, it does not make sense to enable this option without 1907 also enabling support for pointer authentication. Thus, when 1908 enabling this option you should also select ARM64_PTR_AUTH=y. 1909 1910 Userspace binaries must also be specifically compiled to make use of 1911 this mechanism. If you say N here or the hardware does not support 1912 BTI, such binaries can still run, but you get no additional 1913 enforcement of branch destinations. 1914 1915config ARM64_BTI_KERNEL 1916 bool "Use Branch Target Identification for kernel" 1917 default y 1918 depends on ARM64_BTI 1919 depends on ARM64_PTR_AUTH_KERNEL 1920 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1921 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1922 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1923 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 1924 depends on !CC_IS_GCC 1925 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1926 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1927 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1928 help 1929 Build the kernel with Branch Target Identification annotations 1930 and enable enforcement of this for kernel code. When this option 1931 is enabled and the system supports BTI all kernel code including 1932 modular code must have BTI enabled. 1933 1934config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1935 # GCC 9 or later, clang 8 or later 1936 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1937 1938config ARM64_E0PD 1939 bool "Enable support for E0PD" 1940 default y 1941 help 1942 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1943 that EL0 accesses made via TTBR1 always fault in constant time, 1944 providing similar benefits to KASLR as those provided by KPTI, but 1945 with lower overhead and without disrupting legitimate access to 1946 kernel memory such as SPE. 1947 1948 This option enables E0PD for TTBR1 where available. 1949 1950config ARM64_AS_HAS_MTE 1951 # Initial support for MTE went in binutils 2.32.0, checked with 1952 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1953 # as a late addition to the final architecture spec (LDGM/STGM) 1954 # is only supported in the newer 2.32.x and 2.33 binutils 1955 # versions, hence the extra "stgm" instruction check below. 1956 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1957 1958config ARM64_MTE 1959 bool "Memory Tagging Extension support" 1960 default y 1961 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1962 depends on AS_HAS_ARMV8_5 1963 depends on AS_HAS_LSE_ATOMICS 1964 # Required for tag checking in the uaccess routines 1965 depends on ARM64_PAN 1966 select ARCH_HAS_SUBPAGE_FAULTS 1967 select ARCH_USES_HIGH_VMA_FLAGS 1968 help 1969 Memory Tagging (part of the ARMv8.5 Extensions) provides 1970 architectural support for run-time, always-on detection of 1971 various classes of memory error to aid with software debugging 1972 to eliminate vulnerabilities arising from memory-unsafe 1973 languages. 1974 1975 This option enables the support for the Memory Tagging 1976 Extension at EL0 (i.e. for userspace). 1977 1978 Selecting this option allows the feature to be detected at 1979 runtime. Any secondary CPU not implementing this feature will 1980 not be allowed a late bring-up. 1981 1982 Userspace binaries that want to use this feature must 1983 explicitly opt in. The mechanism for the userspace is 1984 described in: 1985 1986 Documentation/arm64/memory-tagging-extension.rst. 1987 1988endmenu # "ARMv8.5 architectural features" 1989 1990menu "ARMv8.7 architectural features" 1991 1992config ARM64_EPAN 1993 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1994 default y 1995 depends on ARM64_PAN 1996 help 1997 Enhanced Privileged Access Never (EPAN) allows Privileged 1998 Access Never to be used with Execute-only mappings. 1999 2000 The feature is detected at runtime, and will remain disabled 2001 if the cpu does not implement the feature. 2002endmenu # "ARMv8.7 architectural features" 2003 2004config ARM64_SVE 2005 bool "ARM Scalable Vector Extension support" 2006 default y 2007 help 2008 The Scalable Vector Extension (SVE) is an extension to the AArch64 2009 execution state which complements and extends the SIMD functionality 2010 of the base architecture to support much larger vectors and to enable 2011 additional vectorisation opportunities. 2012 2013 To enable use of this extension on CPUs that implement it, say Y. 2014 2015 On CPUs that support the SVE2 extensions, this option will enable 2016 those too. 2017 2018 Note that for architectural reasons, firmware _must_ implement SVE 2019 support when running on SVE capable hardware. The required support 2020 is present in: 2021 2022 * version 1.5 and later of the ARM Trusted Firmware 2023 * the AArch64 boot wrapper since commit 5e1261e08abf 2024 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2025 2026 For other firmware implementations, consult the firmware documentation 2027 or vendor. 2028 2029 If you need the kernel to boot on SVE-capable hardware with broken 2030 firmware, you may need to say N here until you get your firmware 2031 fixed. Otherwise, you may experience firmware panics or lockups when 2032 booting the kernel. If unsure and you are not observing these 2033 symptoms, you should assume that it is safe to say Y. 2034 2035config ARM64_SME 2036 bool "ARM Scalable Matrix Extension support" 2037 default y 2038 depends on ARM64_SVE 2039 help 2040 The Scalable Matrix Extension (SME) is an extension to the AArch64 2041 execution state which utilises a substantial subset of the SVE 2042 instruction set, together with the addition of new architectural 2043 register state capable of holding two dimensional matrix tiles to 2044 enable various matrix operations. 2045 2046config ARM64_MODULE_PLTS 2047 bool "Use PLTs to allow module memory to spill over into vmalloc area" 2048 depends on MODULES 2049 select HAVE_MOD_ARCH_SPECIFIC 2050 help 2051 Allocate PLTs when loading modules so that jumps and calls whose 2052 targets are too far away for their relative offsets to be encoded 2053 in the instructions themselves can be bounced via veneers in the 2054 module's PLT. This allows modules to be allocated in the generic 2055 vmalloc area after the dedicated module memory area has been 2056 exhausted. 2057 2058 When running with address space randomization (KASLR), the module 2059 region itself may be too far away for ordinary relative jumps and 2060 calls, and so in that case, module PLTs are required and cannot be 2061 disabled. 2062 2063 Specific errata workaround(s) might also force module PLTs to be 2064 enabled (ARM64_ERRATUM_843419). 2065 2066config ARM64_PSEUDO_NMI 2067 bool "Support for NMI-like interrupts" 2068 select ARM_GIC_V3 2069 help 2070 Adds support for mimicking Non-Maskable Interrupts through the use of 2071 GIC interrupt priority. This support requires version 3 or later of 2072 ARM GIC. 2073 2074 This high priority configuration for interrupts needs to be 2075 explicitly enabled by setting the kernel parameter 2076 "irqchip.gicv3_pseudo_nmi" to 1. 2077 2078 If unsure, say N 2079 2080if ARM64_PSEUDO_NMI 2081config ARM64_DEBUG_PRIORITY_MASKING 2082 bool "Debug interrupt priority masking" 2083 help 2084 This adds runtime checks to functions enabling/disabling 2085 interrupts when using priority masking. The additional checks verify 2086 the validity of ICC_PMR_EL1 when calling concerned functions. 2087 2088 If unsure, say N 2089endif # ARM64_PSEUDO_NMI 2090 2091config RELOCATABLE 2092 bool "Build a relocatable kernel image" if EXPERT 2093 select ARCH_HAS_RELR 2094 default y 2095 help 2096 This builds the kernel as a Position Independent Executable (PIE), 2097 which retains all relocation metadata required to relocate the 2098 kernel binary at runtime to a different virtual address than the 2099 address it was linked at. 2100 Since AArch64 uses the RELA relocation format, this requires a 2101 relocation pass at runtime even if the kernel is loaded at the 2102 same address it was linked at. 2103 2104config RANDOMIZE_BASE 2105 bool "Randomize the address of the kernel image" 2106 select ARM64_MODULE_PLTS if MODULES 2107 select RELOCATABLE 2108 help 2109 Randomizes the virtual address at which the kernel image is 2110 loaded, as a security feature that deters exploit attempts 2111 relying on knowledge of the location of kernel internals. 2112 2113 It is the bootloader's job to provide entropy, by passing a 2114 random u64 value in /chosen/kaslr-seed at kernel entry. 2115 2116 When booting via the UEFI stub, it will invoke the firmware's 2117 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2118 to the kernel proper. In addition, it will randomise the physical 2119 location of the kernel Image as well. 2120 2121 If unsure, say N. 2122 2123config RANDOMIZE_MODULE_REGION_FULL 2124 bool "Randomize the module region over a 2 GB range" 2125 depends on RANDOMIZE_BASE 2126 default y 2127 help 2128 Randomizes the location of the module region inside a 2 GB window 2129 covering the core kernel. This way, it is less likely for modules 2130 to leak information about the location of core kernel data structures 2131 but it does imply that function calls between modules and the core 2132 kernel will need to be resolved via veneers in the module PLT. 2133 2134 When this option is not set, the module region will be randomized over 2135 a limited range that contains the [_stext, _etext] interval of the 2136 core kernel, so branch relocations are almost always in range unless 2137 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2138 particular case of region exhaustion, modules might be able to fall 2139 back to a larger 2GB area. 2140 2141config CC_HAVE_STACKPROTECTOR_SYSREG 2142 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2143 2144config STACKPROTECTOR_PER_TASK 2145 def_bool y 2146 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2147 2148# The GPIO number here must be sorted by descending number. In case of 2149# a multiplatform kernel, we just want the highest value required by the 2150# selected platforms. 2151config ARCH_NR_GPIO 2152 int 2153 default 2048 if ARCH_APPLE 2154 default 0 2155 help 2156 Maximum number of GPIOs in the system. 2157 2158 If unsure, leave the default value. 2159 2160endmenu # "Kernel Features" 2161 2162menu "Boot options" 2163 2164config ARM64_ACPI_PARKING_PROTOCOL 2165 bool "Enable support for the ARM64 ACPI parking protocol" 2166 depends on ACPI 2167 help 2168 Enable support for the ARM64 ACPI parking protocol. If disabled 2169 the kernel will not allow booting through the ARM64 ACPI parking 2170 protocol even if the corresponding data is present in the ACPI 2171 MADT table. 2172 2173config CMDLINE 2174 string "Default kernel command string" 2175 default "" 2176 help 2177 Provide a set of default command-line options at build time by 2178 entering them here. As a minimum, you should specify the the 2179 root device (e.g. root=/dev/nfs). 2180 2181choice 2182 prompt "Kernel command line type" if CMDLINE != "" 2183 default CMDLINE_FROM_BOOTLOADER 2184 help 2185 Choose how the kernel will handle the provided default kernel 2186 command line string. 2187 2188config CMDLINE_FROM_BOOTLOADER 2189 bool "Use bootloader kernel arguments if available" 2190 help 2191 Uses the command-line options passed by the boot loader. If 2192 the boot loader doesn't provide any, the default kernel command 2193 string provided in CMDLINE will be used. 2194 2195config CMDLINE_FORCE 2196 bool "Always use the default kernel command string" 2197 help 2198 Always use the default kernel command string, even if the boot 2199 loader passes other arguments to the kernel. 2200 This is useful if you cannot or don't want to change the 2201 command-line options your boot loader passes to the kernel. 2202 2203endchoice 2204 2205config EFI_STUB 2206 bool 2207 2208config EFI 2209 bool "UEFI runtime support" 2210 depends on OF && !CPU_BIG_ENDIAN 2211 depends on KERNEL_MODE_NEON 2212 select ARCH_SUPPORTS_ACPI 2213 select LIBFDT 2214 select UCS2_STRING 2215 select EFI_PARAMS_FROM_FDT 2216 select EFI_RUNTIME_WRAPPERS 2217 select EFI_STUB 2218 select EFI_GENERIC_STUB 2219 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2220 default y 2221 help 2222 This option provides support for runtime services provided 2223 by UEFI firmware (such as non-volatile variables, realtime 2224 clock, and platform reset). A UEFI stub is also provided to 2225 allow the kernel to be booted as an EFI application. This 2226 is only useful on systems that have UEFI firmware. 2227 2228config DMI 2229 bool "Enable support for SMBIOS (DMI) tables" 2230 depends on EFI 2231 default y 2232 help 2233 This enables SMBIOS/DMI feature for systems. 2234 2235 This option is only useful on systems that have UEFI firmware. 2236 However, even with this option, the resultant kernel should 2237 continue to boot on existing non-UEFI platforms. 2238 2239endmenu # "Boot options" 2240 2241menu "Power management options" 2242 2243source "kernel/power/Kconfig" 2244 2245config ARCH_HIBERNATION_POSSIBLE 2246 def_bool y 2247 depends on CPU_PM 2248 2249config ARCH_HIBERNATION_HEADER 2250 def_bool y 2251 depends on HIBERNATION 2252 2253config ARCH_SUSPEND_POSSIBLE 2254 def_bool y 2255 2256endmenu # "Power management options" 2257 2258menu "CPU Power Management" 2259 2260source "drivers/cpuidle/Kconfig" 2261 2262source "drivers/cpufreq/Kconfig" 2263 2264endmenu # "CPU Power Management" 2265 2266source "drivers/acpi/Kconfig" 2267 2268source "arch/arm64/kvm/Kconfig" 2269 2270