1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3	def_bool y
4	select ACPI_APMT if ACPI
5	select ACPI_CCA_REQUIRED if ACPI
6	select ACPI_GENERIC_GSI if ACPI
7	select ACPI_GTDT if ACPI
8	select ACPI_IORT if ACPI
9	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10	select ACPI_MCFG if (ACPI && PCI)
11	select ACPI_SPCR_TABLE if ACPI
12	select ACPI_PPTT if ACPI
13	select ARCH_HAS_DEBUG_WX
14	select ARCH_BINFMT_ELF_EXTRA_PHDRS
15	select ARCH_BINFMT_ELF_STATE
16	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18	select ARCH_ENABLE_MEMORY_HOTPLUG
19	select ARCH_ENABLE_MEMORY_HOTREMOVE
20	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21	select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22	select ARCH_HAS_CACHE_LINE_SIZE
23	select ARCH_HAS_CURRENT_STACK_POINTER
24	select ARCH_HAS_DEBUG_VIRTUAL
25	select ARCH_HAS_DEBUG_VM_PGTABLE
26	select ARCH_HAS_DMA_PREP_COHERENT
27	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28	select ARCH_HAS_FAST_MULTIPLIER
29	select ARCH_HAS_FORTIFY_SOURCE
30	select ARCH_HAS_GCOV_PROFILE_ALL
31	select ARCH_HAS_GIGANTIC_PAGE
32	select ARCH_HAS_KCOV
33	select ARCH_HAS_KEEPINITRD
34	select ARCH_HAS_MEMBARRIER_SYNC_CORE
35	select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37	select ARCH_HAS_PTE_DEVMAP
38	select ARCH_HAS_PTE_SPECIAL
39	select ARCH_HAS_SETUP_DMA_OPS
40	select ARCH_HAS_SET_DIRECT_MAP
41	select ARCH_HAS_SET_MEMORY
42	select ARCH_STACKWALK
43	select ARCH_HAS_STRICT_KERNEL_RWX
44	select ARCH_HAS_STRICT_MODULE_RWX
45	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
46	select ARCH_HAS_SYNC_DMA_FOR_CPU
47	select ARCH_HAS_SYSCALL_WRAPPER
48	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
49	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
50	select ARCH_HAS_ZONE_DMA_SET if EXPERT
51	select ARCH_HAVE_ELF_PROT
52	select ARCH_HAVE_NMI_SAFE_CMPXCHG
53	select ARCH_HAVE_TRACE_MMIO_ACCESS
54	select ARCH_INLINE_READ_LOCK if !PREEMPTION
55	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
56	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
57	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
58	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
59	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
60	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
61	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
62	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
63	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
64	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
65	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
66	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
67	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
68	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
69	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
70	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
71	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
72	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
73	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
74	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
75	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
76	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
77	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
78	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
79	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
80	select ARCH_KEEP_MEMBLOCK
81	select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
82	select ARCH_USE_CMPXCHG_LOCKREF
83	select ARCH_USE_GNU_PROPERTY
84	select ARCH_USE_MEMTEST
85	select ARCH_USE_QUEUED_RWLOCKS
86	select ARCH_USE_QUEUED_SPINLOCKS
87	select ARCH_USE_SYM_ANNOTATIONS
88	select ARCH_SUPPORTS_DEBUG_PAGEALLOC
89	select ARCH_SUPPORTS_HUGETLBFS
90	select ARCH_SUPPORTS_MEMORY_FAILURE
91	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
92	select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
93	select ARCH_SUPPORTS_LTO_CLANG_THIN
94	select ARCH_SUPPORTS_CFI_CLANG
95	select ARCH_SUPPORTS_ATOMIC_RMW
96	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
97	select ARCH_SUPPORTS_NUMA_BALANCING
98	select ARCH_SUPPORTS_PAGE_TABLE_CHECK
99	select ARCH_SUPPORTS_PER_VMA_LOCK
100	select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH
101	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
102	select ARCH_WANT_DEFAULT_BPF_JIT
103	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
104	select ARCH_WANT_FRAME_POINTERS
105	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
106	select ARCH_WANT_LD_ORPHAN_WARN
107	select ARCH_WANTS_NO_INSTR
108	select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
109	select ARCH_HAS_UBSAN_SANITIZE_ALL
110	select ARM_AMBA
111	select ARM_ARCH_TIMER
112	select ARM_GIC
113	select AUDIT_ARCH_COMPAT_GENERIC
114	select ARM_GIC_V2M if PCI
115	select ARM_GIC_V3
116	select ARM_GIC_V3_ITS if PCI
117	select ARM_PSCI_FW
118	select BUILDTIME_TABLE_SORT
119	select CLONE_BACKWARDS
120	select COMMON_CLK
121	select CPU_PM if (SUSPEND || CPU_IDLE)
122	select CRC32
123	select DCACHE_WORD_ACCESS
124	select DYNAMIC_FTRACE if FUNCTION_TRACER
125	select DMA_BOUNCE_UNALIGNED_KMALLOC
126	select DMA_DIRECT_REMAP
127	select EDAC_SUPPORT
128	select FRAME_POINTER
129	select FUNCTION_ALIGNMENT_4B
130	select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
131	select GENERIC_ALLOCATOR
132	select GENERIC_ARCH_TOPOLOGY
133	select GENERIC_CLOCKEVENTS_BROADCAST
134	select GENERIC_CPU_AUTOPROBE
135	select GENERIC_CPU_VULNERABILITIES
136	select GENERIC_EARLY_IOREMAP
137	select GENERIC_IDLE_POLL_SETUP
138	select GENERIC_IOREMAP
139	select GENERIC_IRQ_IPI
140	select GENERIC_IRQ_PROBE
141	select GENERIC_IRQ_SHOW
142	select GENERIC_IRQ_SHOW_LEVEL
143	select GENERIC_LIB_DEVMEM_IS_ALLOWED
144	select GENERIC_PCI_IOMAP
145	select GENERIC_PTDUMP
146	select GENERIC_SCHED_CLOCK
147	select GENERIC_SMP_IDLE_THREAD
148	select GENERIC_TIME_VSYSCALL
149	select GENERIC_GETTIMEOFDAY
150	select GENERIC_VDSO_TIME_NS
151	select HARDIRQS_SW_RESEND
152	select HAS_IOPORT
153	select HAVE_MOVE_PMD
154	select HAVE_MOVE_PUD
155	select HAVE_PCI
156	select HAVE_ACPI_APEI if (ACPI && EFI)
157	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
158	select HAVE_ARCH_AUDITSYSCALL
159	select HAVE_ARCH_BITREVERSE
160	select HAVE_ARCH_COMPILER_H
161	select HAVE_ARCH_HUGE_VMALLOC
162	select HAVE_ARCH_HUGE_VMAP
163	select HAVE_ARCH_JUMP_LABEL
164	select HAVE_ARCH_JUMP_LABEL_RELATIVE
165	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
166	select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
167	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
168	select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
169	# Some instrumentation may be unsound, hence EXPERT
170	select HAVE_ARCH_KCSAN if EXPERT
171	select HAVE_ARCH_KFENCE
172	select HAVE_ARCH_KGDB
173	select HAVE_ARCH_MMAP_RND_BITS
174	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
175	select HAVE_ARCH_PREL32_RELOCATIONS
176	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
177	select HAVE_ARCH_SECCOMP_FILTER
178	select HAVE_ARCH_STACKLEAK
179	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
180	select HAVE_ARCH_TRACEHOOK
181	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
182	select HAVE_ARCH_VMAP_STACK
183	select HAVE_ARM_SMCCC
184	select HAVE_ASM_MODVERSIONS
185	select HAVE_EBPF_JIT
186	select HAVE_C_RECORDMCOUNT
187	select HAVE_CMPXCHG_DOUBLE
188	select HAVE_CMPXCHG_LOCAL
189	select HAVE_CONTEXT_TRACKING_USER
190	select HAVE_DEBUG_KMEMLEAK
191	select HAVE_DMA_CONTIGUOUS
192	select HAVE_DYNAMIC_FTRACE
193	select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
194		if $(cc-option,-fpatchable-function-entry=2)
195	select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
196		if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
197	select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
198		if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
199		    !CC_OPTIMIZE_FOR_SIZE)
200	select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
201		if DYNAMIC_FTRACE_WITH_ARGS
202	select HAVE_SAMPLE_FTRACE_DIRECT
203	select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
204	select HAVE_EFFICIENT_UNALIGNED_ACCESS
205	select HAVE_FAST_GUP
206	select HAVE_FTRACE_MCOUNT_RECORD
207	select HAVE_FUNCTION_TRACER
208	select HAVE_FUNCTION_ERROR_INJECTION
209	select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER
210	select HAVE_FUNCTION_GRAPH_TRACER
211	select HAVE_GCC_PLUGINS
212	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \
213		HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI
214	select HAVE_HW_BREAKPOINT if PERF_EVENTS
215	select HAVE_IOREMAP_PROT
216	select HAVE_IRQ_TIME_ACCOUNTING
217	select HAVE_KVM
218	select HAVE_MOD_ARCH_SPECIFIC
219	select HAVE_NMI
220	select HAVE_PERF_EVENTS
221	select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI
222	select HAVE_PERF_REGS
223	select HAVE_PERF_USER_STACK_DUMP
224	select HAVE_PREEMPT_DYNAMIC_KEY
225	select HAVE_REGS_AND_STACK_ACCESS_API
226	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
227	select HAVE_FUNCTION_ARG_ACCESS_API
228	select MMU_GATHER_RCU_TABLE_FREE
229	select HAVE_RSEQ
230	select HAVE_STACKPROTECTOR
231	select HAVE_SYSCALL_TRACEPOINTS
232	select HAVE_KPROBES
233	select HAVE_KRETPROBES
234	select HAVE_GENERIC_VDSO
235	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
236	select IRQ_DOMAIN
237	select IRQ_FORCED_THREADING
238	select KASAN_VMALLOC if KASAN
239	select LOCK_MM_AND_FIND_VMA
240	select MODULES_USE_ELF_RELA
241	select NEED_DMA_MAP_STATE
242	select NEED_SG_DMA_LENGTH
243	select OF
244	select OF_EARLY_FLATTREE
245	select PCI_DOMAINS_GENERIC if PCI
246	select PCI_ECAM if (ACPI && PCI)
247	select PCI_SYSCALL if PCI
248	select POWER_RESET
249	select POWER_SUPPLY
250	select SPARSE_IRQ
251	select SWIOTLB
252	select SYSCTL_EXCEPTION_TRACE
253	select THREAD_INFO_IN_TASK
254	select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
255	select TRACE_IRQFLAGS_SUPPORT
256	select TRACE_IRQFLAGS_NMI_SUPPORT
257	select HAVE_SOFTIRQ_ON_OWN_STACK
258	help
259	  ARM 64-bit (AArch64) Linux support.
260
261config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
262	def_bool CC_IS_CLANG
263	# https://github.com/ClangBuiltLinux/linux/issues/1507
264	depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
265	select HAVE_DYNAMIC_FTRACE_WITH_ARGS
266
267config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
268	def_bool CC_IS_GCC
269	depends on $(cc-option,-fpatchable-function-entry=2)
270	select HAVE_DYNAMIC_FTRACE_WITH_ARGS
271
272config 64BIT
273	def_bool y
274
275config MMU
276	def_bool y
277
278config ARM64_PAGE_SHIFT
279	int
280	default 16 if ARM64_64K_PAGES
281	default 14 if ARM64_16K_PAGES
282	default 12
283
284config ARM64_CONT_PTE_SHIFT
285	int
286	default 5 if ARM64_64K_PAGES
287	default 7 if ARM64_16K_PAGES
288	default 4
289
290config ARM64_CONT_PMD_SHIFT
291	int
292	default 5 if ARM64_64K_PAGES
293	default 5 if ARM64_16K_PAGES
294	default 4
295
296config ARCH_MMAP_RND_BITS_MIN
297	default 14 if ARM64_64K_PAGES
298	default 16 if ARM64_16K_PAGES
299	default 18
300
301# max bits determined by the following formula:
302#  VA_BITS - PAGE_SHIFT - 3
303config ARCH_MMAP_RND_BITS_MAX
304	default 19 if ARM64_VA_BITS=36
305	default 24 if ARM64_VA_BITS=39
306	default 27 if ARM64_VA_BITS=42
307	default 30 if ARM64_VA_BITS=47
308	default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
309	default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
310	default 33 if ARM64_VA_BITS=48
311	default 14 if ARM64_64K_PAGES
312	default 16 if ARM64_16K_PAGES
313	default 18
314
315config ARCH_MMAP_RND_COMPAT_BITS_MIN
316	default 7 if ARM64_64K_PAGES
317	default 9 if ARM64_16K_PAGES
318	default 11
319
320config ARCH_MMAP_RND_COMPAT_BITS_MAX
321	default 16
322
323config NO_IOPORT_MAP
324	def_bool y if !PCI
325
326config STACKTRACE_SUPPORT
327	def_bool y
328
329config ILLEGAL_POINTER_VALUE
330	hex
331	default 0xdead000000000000
332
333config LOCKDEP_SUPPORT
334	def_bool y
335
336config GENERIC_BUG
337	def_bool y
338	depends on BUG
339
340config GENERIC_BUG_RELATIVE_POINTERS
341	def_bool y
342	depends on GENERIC_BUG
343
344config GENERIC_HWEIGHT
345	def_bool y
346
347config GENERIC_CSUM
348	def_bool y
349
350config GENERIC_CALIBRATE_DELAY
351	def_bool y
352
353config SMP
354	def_bool y
355
356config KERNEL_MODE_NEON
357	def_bool y
358
359config FIX_EARLYCON_MEM
360	def_bool y
361
362config PGTABLE_LEVELS
363	int
364	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
365	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
366	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
367	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
368	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
369	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
370
371config ARCH_SUPPORTS_UPROBES
372	def_bool y
373
374config ARCH_PROC_KCORE_TEXT
375	def_bool y
376
377config BROKEN_GAS_INST
378	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
379
380config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
381	bool
382	# Clang's __builtin_return_adddress() strips the PAC since 12.0.0
383	# https://reviews.llvm.org/D75044
384	default y if CC_IS_CLANG && (CLANG_VERSION >= 120000)
385	# GCC's __builtin_return_address() strips the PAC since 11.1.0,
386	# and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
387	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
388	default y if CC_IS_GCC && (GCC_VERSION >= 110100)
389	default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
390	default y if CC_IS_GCC && (GCC_VERSION >=  90400) && (GCC_VERSION < 100000)
391	default y if CC_IS_GCC && (GCC_VERSION >=  80500) && (GCC_VERSION <  90000)
392	default n
393
394config KASAN_SHADOW_OFFSET
395	hex
396	depends on KASAN_GENERIC || KASAN_SW_TAGS
397	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
398	default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
399	default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
400	default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
401	default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
402	default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
403	default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
404	default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
405	default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
406	default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
407	default 0xffffffffffffffff
408
409config UNWIND_TABLES
410	bool
411
412source "arch/arm64/Kconfig.platforms"
413
414menu "Kernel Features"
415
416menu "ARM errata workarounds via the alternatives framework"
417
418config AMPERE_ERRATUM_AC03_CPU_38
419        bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
420	default y
421	help
422	  This option adds an alternative code sequence to work around Ampere
423	  erratum AC03_CPU_38 on AmpereOne.
424
425	  The affected design reports FEAT_HAFDBS as not implemented in
426	  ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
427	  as required by the architecture. The unadvertised HAFDBS
428	  implementation suffers from an additional erratum where hardware
429	  A/D updates can occur after a PTE has been marked invalid.
430
431	  The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
432	  which avoids enabling unadvertised hardware Access Flag management
433	  at stage-2.
434
435	  If unsure, say Y.
436
437config ARM64_WORKAROUND_CLEAN_CACHE
438	bool
439
440config ARM64_ERRATUM_826319
441	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
442	default y
443	select ARM64_WORKAROUND_CLEAN_CACHE
444	help
445	  This option adds an alternative code sequence to work around ARM
446	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
447	  AXI master interface and an L2 cache.
448
449	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
450	  and is unable to accept a certain write via this interface, it will
451	  not progress on read data presented on the read data channel and the
452	  system can deadlock.
453
454	  The workaround promotes data cache clean instructions to
455	  data cache clean-and-invalidate.
456	  Please note that this does not necessarily enable the workaround,
457	  as it depends on the alternative framework, which will only patch
458	  the kernel if an affected CPU is detected.
459
460	  If unsure, say Y.
461
462config ARM64_ERRATUM_827319
463	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
464	default y
465	select ARM64_WORKAROUND_CLEAN_CACHE
466	help
467	  This option adds an alternative code sequence to work around ARM
468	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
469	  master interface and an L2 cache.
470
471	  Under certain conditions this erratum can cause a clean line eviction
472	  to occur at the same time as another transaction to the same address
473	  on the AMBA 5 CHI interface, which can cause data corruption if the
474	  interconnect reorders the two transactions.
475
476	  The workaround promotes data cache clean instructions to
477	  data cache clean-and-invalidate.
478	  Please note that this does not necessarily enable the workaround,
479	  as it depends on the alternative framework, which will only patch
480	  the kernel if an affected CPU is detected.
481
482	  If unsure, say Y.
483
484config ARM64_ERRATUM_824069
485	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
486	default y
487	select ARM64_WORKAROUND_CLEAN_CACHE
488	help
489	  This option adds an alternative code sequence to work around ARM
490	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
491	  to a coherent interconnect.
492
493	  If a Cortex-A53 processor is executing a store or prefetch for
494	  write instruction at the same time as a processor in another
495	  cluster is executing a cache maintenance operation to the same
496	  address, then this erratum might cause a clean cache line to be
497	  incorrectly marked as dirty.
498
499	  The workaround promotes data cache clean instructions to
500	  data cache clean-and-invalidate.
501	  Please note that this option does not necessarily enable the
502	  workaround, as it depends on the alternative framework, which will
503	  only patch the kernel if an affected CPU is detected.
504
505	  If unsure, say Y.
506
507config ARM64_ERRATUM_819472
508	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
509	default y
510	select ARM64_WORKAROUND_CLEAN_CACHE
511	help
512	  This option adds an alternative code sequence to work around ARM
513	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
514	  present when it is connected to a coherent interconnect.
515
516	  If the processor is executing a load and store exclusive sequence at
517	  the same time as a processor in another cluster is executing a cache
518	  maintenance operation to the same address, then this erratum might
519	  cause data corruption.
520
521	  The workaround promotes data cache clean instructions to
522	  data cache clean-and-invalidate.
523	  Please note that this does not necessarily enable the workaround,
524	  as it depends on the alternative framework, which will only patch
525	  the kernel if an affected CPU is detected.
526
527	  If unsure, say Y.
528
529config ARM64_ERRATUM_832075
530	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
531	default y
532	help
533	  This option adds an alternative code sequence to work around ARM
534	  erratum 832075 on Cortex-A57 parts up to r1p2.
535
536	  Affected Cortex-A57 parts might deadlock when exclusive load/store
537	  instructions to Write-Back memory are mixed with Device loads.
538
539	  The workaround is to promote device loads to use Load-Acquire
540	  semantics.
541	  Please note that this does not necessarily enable the workaround,
542	  as it depends on the alternative framework, which will only patch
543	  the kernel if an affected CPU is detected.
544
545	  If unsure, say Y.
546
547config ARM64_ERRATUM_834220
548	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
549	depends on KVM
550	default y
551	help
552	  This option adds an alternative code sequence to work around ARM
553	  erratum 834220 on Cortex-A57 parts up to r1p2.
554
555	  Affected Cortex-A57 parts might report a Stage 2 translation
556	  fault as the result of a Stage 1 fault for load crossing a
557	  page boundary when there is a permission or device memory
558	  alignment fault at Stage 1 and a translation fault at Stage 2.
559
560	  The workaround is to verify that the Stage 1 translation
561	  doesn't generate a fault before handling the Stage 2 fault.
562	  Please note that this does not necessarily enable the workaround,
563	  as it depends on the alternative framework, which will only patch
564	  the kernel if an affected CPU is detected.
565
566	  If unsure, say Y.
567
568config ARM64_ERRATUM_1742098
569	bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
570	depends on COMPAT
571	default y
572	help
573	  This option removes the AES hwcap for aarch32 user-space to
574	  workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
575
576	  Affected parts may corrupt the AES state if an interrupt is
577	  taken between a pair of AES instructions. These instructions
578	  are only present if the cryptography extensions are present.
579	  All software should have a fallback implementation for CPUs
580	  that don't implement the cryptography extensions.
581
582	  If unsure, say Y.
583
584config ARM64_ERRATUM_845719
585	bool "Cortex-A53: 845719: a load might read incorrect data"
586	depends on COMPAT
587	default y
588	help
589	  This option adds an alternative code sequence to work around ARM
590	  erratum 845719 on Cortex-A53 parts up to r0p4.
591
592	  When running a compat (AArch32) userspace on an affected Cortex-A53
593	  part, a load at EL0 from a virtual address that matches the bottom 32
594	  bits of the virtual address used by a recent load at (AArch64) EL1
595	  might return incorrect data.
596
597	  The workaround is to write the contextidr_el1 register on exception
598	  return to a 32-bit task.
599	  Please note that this does not necessarily enable the workaround,
600	  as it depends on the alternative framework, which will only patch
601	  the kernel if an affected CPU is detected.
602
603	  If unsure, say Y.
604
605config ARM64_ERRATUM_843419
606	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
607	default y
608	help
609	  This option links the kernel with '--fix-cortex-a53-843419' and
610	  enables PLT support to replace certain ADRP instructions, which can
611	  cause subsequent memory accesses to use an incorrect address on
612	  Cortex-A53 parts up to r0p4.
613
614	  If unsure, say Y.
615
616config ARM64_LD_HAS_FIX_ERRATUM_843419
617	def_bool $(ld-option,--fix-cortex-a53-843419)
618
619config ARM64_ERRATUM_1024718
620	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
621	default y
622	help
623	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
624
625	  Affected Cortex-A55 cores (all revisions) could cause incorrect
626	  update of the hardware dirty bit when the DBM/AP bits are updated
627	  without a break-before-make. The workaround is to disable the usage
628	  of hardware DBM locally on the affected cores. CPUs not affected by
629	  this erratum will continue to use the feature.
630
631	  If unsure, say Y.
632
633config ARM64_ERRATUM_1418040
634	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
635	default y
636	depends on COMPAT
637	help
638	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
639	  errata 1188873 and 1418040.
640
641	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
642	  cause register corruption when accessing the timer registers
643	  from AArch32 userspace.
644
645	  If unsure, say Y.
646
647config ARM64_WORKAROUND_SPECULATIVE_AT
648	bool
649
650config ARM64_ERRATUM_1165522
651	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
652	default y
653	select ARM64_WORKAROUND_SPECULATIVE_AT
654	help
655	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
656
657	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
658	  corrupted TLBs by speculating an AT instruction during a guest
659	  context switch.
660
661	  If unsure, say Y.
662
663config ARM64_ERRATUM_1319367
664	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
665	default y
666	select ARM64_WORKAROUND_SPECULATIVE_AT
667	help
668	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
669	  and A72 erratum 1319367
670
671	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
672	  speculating an AT instruction during a guest context switch.
673
674	  If unsure, say Y.
675
676config ARM64_ERRATUM_1530923
677	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
678	default y
679	select ARM64_WORKAROUND_SPECULATIVE_AT
680	help
681	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
682
683	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
684	  corrupted TLBs by speculating an AT instruction during a guest
685	  context switch.
686
687	  If unsure, say Y.
688
689config ARM64_WORKAROUND_REPEAT_TLBI
690	bool
691
692config ARM64_ERRATUM_2441007
693	bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
694	default y
695	select ARM64_WORKAROUND_REPEAT_TLBI
696	help
697	  This option adds a workaround for ARM Cortex-A55 erratum #2441007.
698
699	  Under very rare circumstances, affected Cortex-A55 CPUs
700	  may not handle a race between a break-before-make sequence on one
701	  CPU, and another CPU accessing the same page. This could allow a
702	  store to a page that has been unmapped.
703
704	  Work around this by adding the affected CPUs to the list that needs
705	  TLB sequences to be done twice.
706
707	  If unsure, say Y.
708
709config ARM64_ERRATUM_1286807
710	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
711	default y
712	select ARM64_WORKAROUND_REPEAT_TLBI
713	help
714	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
715
716	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
717	  address for a cacheable mapping of a location is being
718	  accessed by a core while another core is remapping the virtual
719	  address to a new physical page using the recommended
720	  break-before-make sequence, then under very rare circumstances
721	  TLBI+DSB completes before a read using the translation being
722	  invalidated has been observed by other observers. The
723	  workaround repeats the TLBI+DSB operation.
724
725config ARM64_ERRATUM_1463225
726	bool "Cortex-A76: Software Step might prevent interrupt recognition"
727	default y
728	help
729	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
730
731	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
732	  of a system call instruction (SVC) can prevent recognition of
733	  subsequent interrupts when software stepping is disabled in the
734	  exception handler of the system call and either kernel debugging
735	  is enabled or VHE is in use.
736
737	  Work around the erratum by triggering a dummy step exception
738	  when handling a system call from a task that is being stepped
739	  in a VHE configuration of the kernel.
740
741	  If unsure, say Y.
742
743config ARM64_ERRATUM_1542419
744	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
745	default y
746	help
747	  This option adds a workaround for ARM Neoverse-N1 erratum
748	  1542419.
749
750	  Affected Neoverse-N1 cores could execute a stale instruction when
751	  modified by another CPU. The workaround depends on a firmware
752	  counterpart.
753
754	  Workaround the issue by hiding the DIC feature from EL0. This
755	  forces user-space to perform cache maintenance.
756
757	  If unsure, say Y.
758
759config ARM64_ERRATUM_1508412
760	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
761	default y
762	help
763	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
764
765	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
766	  of a store-exclusive or read of PAR_EL1 and a load with device or
767	  non-cacheable memory attributes. The workaround depends on a firmware
768	  counterpart.
769
770	  KVM guests must also have the workaround implemented or they can
771	  deadlock the system.
772
773	  Work around the issue by inserting DMB SY barriers around PAR_EL1
774	  register reads and warning KVM users. The DMB barrier is sufficient
775	  to prevent a speculative PAR_EL1 read.
776
777	  If unsure, say Y.
778
779config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
780	bool
781
782config ARM64_ERRATUM_2051678
783	bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
784	default y
785	help
786	  This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
787	  Affected Cortex-A510 might not respect the ordering rules for
788	  hardware update of the page table's dirty bit. The workaround
789	  is to not enable the feature on affected CPUs.
790
791	  If unsure, say Y.
792
793config ARM64_ERRATUM_2077057
794	bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
795	default y
796	help
797	  This option adds the workaround for ARM Cortex-A510 erratum 2077057.
798	  Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
799	  expected, but a Pointer Authentication trap is taken instead. The
800	  erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
801	  EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
802
803	  This can only happen when EL2 is stepping EL1.
804
805	  When these conditions occur, the SPSR_EL2 value is unchanged from the
806	  previous guest entry, and can be restored from the in-memory copy.
807
808	  If unsure, say Y.
809
810config ARM64_ERRATUM_2658417
811	bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
812	default y
813	help
814	  This option adds the workaround for ARM Cortex-A510 erratum 2658417.
815	  Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
816	  BFMMLA or VMMLA instructions in rare circumstances when a pair of
817	  A510 CPUs are using shared neon hardware. As the sharing is not
818	  discoverable by the kernel, hide the BF16 HWCAP to indicate that
819	  user-space should not be using these instructions.
820
821	  If unsure, say Y.
822
823config ARM64_ERRATUM_2119858
824	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
825	default y
826	depends on CORESIGHT_TRBE
827	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
828	help
829	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
830
831	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
832	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
833	  the event of a WRAP event.
834
835	  Work around the issue by always making sure we move the TRBPTR_EL1 by
836	  256 bytes before enabling the buffer and filling the first 256 bytes of
837	  the buffer with ETM ignore packets upon disabling.
838
839	  If unsure, say Y.
840
841config ARM64_ERRATUM_2139208
842	bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
843	default y
844	depends on CORESIGHT_TRBE
845	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
846	help
847	  This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
848
849	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
850	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
851	  the event of a WRAP event.
852
853	  Work around the issue by always making sure we move the TRBPTR_EL1 by
854	  256 bytes before enabling the buffer and filling the first 256 bytes of
855	  the buffer with ETM ignore packets upon disabling.
856
857	  If unsure, say Y.
858
859config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
860	bool
861
862config ARM64_ERRATUM_2054223
863	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
864	default y
865	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
866	help
867	  Enable workaround for ARM Cortex-A710 erratum 2054223
868
869	  Affected cores may fail to flush the trace data on a TSB instruction, when
870	  the PE is in trace prohibited state. This will cause losing a few bytes
871	  of the trace cached.
872
873	  Workaround is to issue two TSB consecutively on affected cores.
874
875	  If unsure, say Y.
876
877config ARM64_ERRATUM_2067961
878	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
879	default y
880	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
881	help
882	  Enable workaround for ARM Neoverse-N2 erratum 2067961
883
884	  Affected cores may fail to flush the trace data on a TSB instruction, when
885	  the PE is in trace prohibited state. This will cause losing a few bytes
886	  of the trace cached.
887
888	  Workaround is to issue two TSB consecutively on affected cores.
889
890	  If unsure, say Y.
891
892config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
893	bool
894
895config ARM64_ERRATUM_2253138
896	bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
897	depends on CORESIGHT_TRBE
898	default y
899	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
900	help
901	  This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
902
903	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
904	  for TRBE. Under some conditions, the TRBE might generate a write to the next
905	  virtually addressed page following the last page of the TRBE address space
906	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
907
908	  Work around this in the driver by always making sure that there is a
909	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
910
911	  If unsure, say Y.
912
913config ARM64_ERRATUM_2224489
914	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
915	depends on CORESIGHT_TRBE
916	default y
917	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
918	help
919	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
920
921	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
922	  for TRBE. Under some conditions, the TRBE might generate a write to the next
923	  virtually addressed page following the last page of the TRBE address space
924	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
925
926	  Work around this in the driver by always making sure that there is a
927	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
928
929	  If unsure, say Y.
930
931config ARM64_ERRATUM_2441009
932	bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
933	default y
934	select ARM64_WORKAROUND_REPEAT_TLBI
935	help
936	  This option adds a workaround for ARM Cortex-A510 erratum #2441009.
937
938	  Under very rare circumstances, affected Cortex-A510 CPUs
939	  may not handle a race between a break-before-make sequence on one
940	  CPU, and another CPU accessing the same page. This could allow a
941	  store to a page that has been unmapped.
942
943	  Work around this by adding the affected CPUs to the list that needs
944	  TLB sequences to be done twice.
945
946	  If unsure, say Y.
947
948config ARM64_ERRATUM_2064142
949	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
950	depends on CORESIGHT_TRBE
951	default y
952	help
953	  This option adds the workaround for ARM Cortex-A510 erratum 2064142.
954
955	  Affected Cortex-A510 core might fail to write into system registers after the
956	  TRBE has been disabled. Under some conditions after the TRBE has been disabled
957	  writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
958	  and TRBTRG_EL1 will be ignored and will not be effected.
959
960	  Work around this in the driver by executing TSB CSYNC and DSB after collection
961	  is stopped and before performing a system register write to one of the affected
962	  registers.
963
964	  If unsure, say Y.
965
966config ARM64_ERRATUM_2038923
967	bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
968	depends on CORESIGHT_TRBE
969	default y
970	help
971	  This option adds the workaround for ARM Cortex-A510 erratum 2038923.
972
973	  Affected Cortex-A510 core might cause an inconsistent view on whether trace is
974	  prohibited within the CPU. As a result, the trace buffer or trace buffer state
975	  might be corrupted. This happens after TRBE buffer has been enabled by setting
976	  TRBLIMITR_EL1.E, followed by just a single context synchronization event before
977	  execution changes from a context, in which trace is prohibited to one where it
978	  isn't, or vice versa. In these mentioned conditions, the view of whether trace
979	  is prohibited is inconsistent between parts of the CPU, and the trace buffer or
980	  the trace buffer state might be corrupted.
981
982	  Work around this in the driver by preventing an inconsistent view of whether the
983	  trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
984	  change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
985	  two ISB instructions if no ERET is to take place.
986
987	  If unsure, say Y.
988
989config ARM64_ERRATUM_1902691
990	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
991	depends on CORESIGHT_TRBE
992	default y
993	help
994	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.
995
996	  Affected Cortex-A510 core might cause trace data corruption, when being written
997	  into the memory. Effectively TRBE is broken and hence cannot be used to capture
998	  trace data.
999
1000	  Work around this problem in the driver by just preventing TRBE initialization on
1001	  affected cpus. The firmware must have disabled the access to TRBE for the kernel
1002	  on such implementations. This will cover the kernel for any firmware that doesn't
1003	  do this already.
1004
1005	  If unsure, say Y.
1006
1007config ARM64_ERRATUM_2457168
1008	bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1009	depends on ARM64_AMU_EXTN
1010	default y
1011	help
1012	  This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1013
1014	  The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
1015	  as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1016	  incorrectly giving a significantly higher output value.
1017
1018	  Work around this problem by returning 0 when reading the affected counter in
1019	  key locations that results in disabling all users of this counter. This effect
1020	  is the same to firmware disabling affected counters.
1021
1022	  If unsure, say Y.
1023
1024config ARM64_ERRATUM_2645198
1025	bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1026	default y
1027	help
1028	  This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1029
1030	  If a Cortex-A715 cpu sees a page mapping permissions change from executable
1031	  to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1032	  next instruction abort caused by permission fault.
1033
1034	  Only user-space does executable to non-executable permission transition via
1035	  mprotect() system call. Workaround the problem by doing a break-before-make
1036	  TLB invalidation, for all changes to executable user space mappings.
1037
1038	  If unsure, say Y.
1039
1040config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1041	bool
1042
1043config ARM64_ERRATUM_2966298
1044	bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1045	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1046	default y
1047	help
1048	  This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1049
1050	  On an affected Cortex-A520 core, a speculatively executed unprivileged
1051	  load might leak data from a privileged level via a cache side channel.
1052
1053	  Work around this problem by executing a TLBI before returning to EL0.
1054
1055	  If unsure, say Y.
1056
1057config ARM64_ERRATUM_3117295
1058	bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1059	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1060	default y
1061	help
1062	  This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1063
1064	  On an affected Cortex-A510 core, a speculatively executed unprivileged
1065	  load might leak data from a privileged level via a cache side channel.
1066
1067	  Work around this problem by executing a TLBI before returning to EL0.
1068
1069	  If unsure, say Y.
1070
1071config CAVIUM_ERRATUM_22375
1072	bool "Cavium erratum 22375, 24313"
1073	default y
1074	help
1075	  Enable workaround for errata 22375 and 24313.
1076
1077	  This implements two gicv3-its errata workarounds for ThunderX. Both
1078	  with a small impact affecting only ITS table allocation.
1079
1080	    erratum 22375: only alloc 8MB table size
1081	    erratum 24313: ignore memory access type
1082
1083	  The fixes are in ITS initialization and basically ignore memory access
1084	  type and table size provided by the TYPER and BASER registers.
1085
1086	  If unsure, say Y.
1087
1088config CAVIUM_ERRATUM_23144
1089	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1090	depends on NUMA
1091	default y
1092	help
1093	  ITS SYNC command hang for cross node io and collections/cpu mapping.
1094
1095	  If unsure, say Y.
1096
1097config CAVIUM_ERRATUM_23154
1098	bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1099	default y
1100	help
1101	  The ThunderX GICv3 implementation requires a modified version for
1102	  reading the IAR status to ensure data synchronization
1103	  (access to icc_iar1_el1 is not sync'ed before and after).
1104
1105	  It also suffers from erratum 38545 (also present on Marvell's
1106	  OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1107	  spuriously presented to the CPU interface.
1108
1109	  If unsure, say Y.
1110
1111config CAVIUM_ERRATUM_27456
1112	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1113	default y
1114	help
1115	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1116	  instructions may cause the icache to become corrupted if it
1117	  contains data for a non-current ASID.  The fix is to
1118	  invalidate the icache when changing the mm context.
1119
1120	  If unsure, say Y.
1121
1122config CAVIUM_ERRATUM_30115
1123	bool "Cavium erratum 30115: Guest may disable interrupts in host"
1124	default y
1125	help
1126	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1127	  1.2, and T83 Pass 1.0, KVM guest execution may disable
1128	  interrupts in host. Trapping both GICv3 group-0 and group-1
1129	  accesses sidesteps the issue.
1130
1131	  If unsure, say Y.
1132
1133config CAVIUM_TX2_ERRATUM_219
1134	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1135	default y
1136	help
1137	  On Cavium ThunderX2, a load, store or prefetch instruction between a
1138	  TTBR update and the corresponding context synchronizing operation can
1139	  cause a spurious Data Abort to be delivered to any hardware thread in
1140	  the CPU core.
1141
1142	  Work around the issue by avoiding the problematic code sequence and
1143	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1144	  trap handler performs the corresponding register access, skips the
1145	  instruction and ensures context synchronization by virtue of the
1146	  exception return.
1147
1148	  If unsure, say Y.
1149
1150config FUJITSU_ERRATUM_010001
1151	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1152	default y
1153	help
1154	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1155	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1156	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
1157	  This fault occurs under a specific hardware condition when a
1158	  load/store instruction performs an address translation using:
1159	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1160	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1161	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1162	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1163
1164	  The workaround is to ensure these bits are clear in TCR_ELx.
1165	  The workaround only affects the Fujitsu-A64FX.
1166
1167	  If unsure, say Y.
1168
1169config HISILICON_ERRATUM_161600802
1170	bool "Hip07 161600802: Erroneous redistributor VLPI base"
1171	default y
1172	help
1173	  The HiSilicon Hip07 SoC uses the wrong redistributor base
1174	  when issued ITS commands such as VMOVP and VMAPP, and requires
1175	  a 128kB offset to be applied to the target address in this commands.
1176
1177	  If unsure, say Y.
1178
1179config QCOM_FALKOR_ERRATUM_1003
1180	bool "Falkor E1003: Incorrect translation due to ASID change"
1181	default y
1182	help
1183	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1184	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1185	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
1186	  then only for entries in the walk cache, since the leaf translation
1187	  is unchanged. Work around the erratum by invalidating the walk cache
1188	  entries for the trampoline before entering the kernel proper.
1189
1190config QCOM_FALKOR_ERRATUM_1009
1191	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1192	default y
1193	select ARM64_WORKAROUND_REPEAT_TLBI
1194	help
1195	  On Falkor v1, the CPU may prematurely complete a DSB following a
1196	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1197	  one more time to fix the issue.
1198
1199	  If unsure, say Y.
1200
1201config QCOM_QDF2400_ERRATUM_0065
1202	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1203	default y
1204	help
1205	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1206	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1207	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1208
1209	  If unsure, say Y.
1210
1211config QCOM_FALKOR_ERRATUM_E1041
1212	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1213	default y
1214	help
1215	  Falkor CPU may speculatively fetch instructions from an improper
1216	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
1217	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1218
1219	  If unsure, say Y.
1220
1221config NVIDIA_CARMEL_CNP_ERRATUM
1222	bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1223	default y
1224	help
1225	  If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1226	  invalidate shared TLB entries installed by a different core, as it would
1227	  on standard ARM cores.
1228
1229	  If unsure, say Y.
1230
1231config ROCKCHIP_ERRATUM_3588001
1232	bool "Rockchip 3588001: GIC600 can not support shareability attributes"
1233	default y
1234	help
1235	  The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1236	  This means, that its sharability feature may not be used, even though it
1237	  is supported by the IP itself.
1238
1239	  If unsure, say Y.
1240
1241config SOCIONEXT_SYNQUACER_PREITS
1242	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1243	default y
1244	help
1245	  Socionext Synquacer SoCs implement a separate h/w block to generate
1246	  MSI doorbell writes with non-zero values for the device ID.
1247
1248	  If unsure, say Y.
1249
1250endmenu # "ARM errata workarounds via the alternatives framework"
1251
1252choice
1253	prompt "Page size"
1254	default ARM64_4K_PAGES
1255	help
1256	  Page size (translation granule) configuration.
1257
1258config ARM64_4K_PAGES
1259	bool "4KB"
1260	help
1261	  This feature enables 4KB pages support.
1262
1263config ARM64_16K_PAGES
1264	bool "16KB"
1265	help
1266	  The system will use 16KB pages support. AArch32 emulation
1267	  requires applications compiled with 16K (or a multiple of 16K)
1268	  aligned segments.
1269
1270config ARM64_64K_PAGES
1271	bool "64KB"
1272	help
1273	  This feature enables 64KB pages support (4KB by default)
1274	  allowing only two levels of page tables and faster TLB
1275	  look-up. AArch32 emulation requires applications compiled
1276	  with 64K aligned segments.
1277
1278endchoice
1279
1280choice
1281	prompt "Virtual address space size"
1282	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1283	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1284	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1285	help
1286	  Allows choosing one of multiple possible virtual address
1287	  space sizes. The level of translation table is determined by
1288	  a combination of page size and virtual address space size.
1289
1290config ARM64_VA_BITS_36
1291	bool "36-bit" if EXPERT
1292	depends on ARM64_16K_PAGES
1293
1294config ARM64_VA_BITS_39
1295	bool "39-bit"
1296	depends on ARM64_4K_PAGES
1297
1298config ARM64_VA_BITS_42
1299	bool "42-bit"
1300	depends on ARM64_64K_PAGES
1301
1302config ARM64_VA_BITS_47
1303	bool "47-bit"
1304	depends on ARM64_16K_PAGES
1305
1306config ARM64_VA_BITS_48
1307	bool "48-bit"
1308
1309config ARM64_VA_BITS_52
1310	bool "52-bit"
1311	depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1312	help
1313	  Enable 52-bit virtual addressing for userspace when explicitly
1314	  requested via a hint to mmap(). The kernel will also use 52-bit
1315	  virtual addresses for its own mappings (provided HW support for
1316	  this feature is available, otherwise it reverts to 48-bit).
1317
1318	  NOTE: Enabling 52-bit virtual addressing in conjunction with
1319	  ARMv8.3 Pointer Authentication will result in the PAC being
1320	  reduced from 7 bits to 3 bits, which may have a significant
1321	  impact on its susceptibility to brute-force attacks.
1322
1323	  If unsure, select 48-bit virtual addressing instead.
1324
1325endchoice
1326
1327config ARM64_FORCE_52BIT
1328	bool "Force 52-bit virtual addresses for userspace"
1329	depends on ARM64_VA_BITS_52 && EXPERT
1330	help
1331	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
1332	  to maintain compatibility with older software by providing 48-bit VAs
1333	  unless a hint is supplied to mmap.
1334
1335	  This configuration option disables the 48-bit compatibility logic, and
1336	  forces all userspace addresses to be 52-bit on HW that supports it. One
1337	  should only enable this configuration option for stress testing userspace
1338	  memory management code. If unsure say N here.
1339
1340config ARM64_VA_BITS
1341	int
1342	default 36 if ARM64_VA_BITS_36
1343	default 39 if ARM64_VA_BITS_39
1344	default 42 if ARM64_VA_BITS_42
1345	default 47 if ARM64_VA_BITS_47
1346	default 48 if ARM64_VA_BITS_48
1347	default 52 if ARM64_VA_BITS_52
1348
1349choice
1350	prompt "Physical address space size"
1351	default ARM64_PA_BITS_48
1352	help
1353	  Choose the maximum physical address range that the kernel will
1354	  support.
1355
1356config ARM64_PA_BITS_48
1357	bool "48-bit"
1358
1359config ARM64_PA_BITS_52
1360	bool "52-bit (ARMv8.2)"
1361	depends on ARM64_64K_PAGES
1362	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1363	help
1364	  Enable support for a 52-bit physical address space, introduced as
1365	  part of the ARMv8.2-LPA extension.
1366
1367	  With this enabled, the kernel will also continue to work on CPUs that
1368	  do not support ARMv8.2-LPA, but with some added memory overhead (and
1369	  minor performance overhead).
1370
1371endchoice
1372
1373config ARM64_PA_BITS
1374	int
1375	default 48 if ARM64_PA_BITS_48
1376	default 52 if ARM64_PA_BITS_52
1377
1378choice
1379	prompt "Endianness"
1380	default CPU_LITTLE_ENDIAN
1381	help
1382	  Select the endianness of data accesses performed by the CPU. Userspace
1383	  applications will need to be compiled and linked for the endianness
1384	  that is selected here.
1385
1386config CPU_BIG_ENDIAN
1387	bool "Build big-endian kernel"
1388	depends on !LD_IS_LLD || LLD_VERSION >= 130000
1389	# https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1390	depends on AS_IS_GNU || AS_VERSION >= 150000
1391	help
1392	  Say Y if you plan on running a kernel with a big-endian userspace.
1393
1394config CPU_LITTLE_ENDIAN
1395	bool "Build little-endian kernel"
1396	help
1397	  Say Y if you plan on running a kernel with a little-endian userspace.
1398	  This is usually the case for distributions targeting arm64.
1399
1400endchoice
1401
1402config SCHED_MC
1403	bool "Multi-core scheduler support"
1404	help
1405	  Multi-core scheduler support improves the CPU scheduler's decision
1406	  making when dealing with multi-core CPU chips at a cost of slightly
1407	  increased overhead in some places. If unsure say N here.
1408
1409config SCHED_CLUSTER
1410	bool "Cluster scheduler support"
1411	help
1412	  Cluster scheduler support improves the CPU scheduler's decision
1413	  making when dealing with machines that have clusters of CPUs.
1414	  Cluster usually means a couple of CPUs which are placed closely
1415	  by sharing mid-level caches, last-level cache tags or internal
1416	  busses.
1417
1418config SCHED_SMT
1419	bool "SMT scheduler support"
1420	help
1421	  Improves the CPU scheduler's decision making when dealing with
1422	  MultiThreading at a cost of slightly increased overhead in some
1423	  places. If unsure say N here.
1424
1425config NR_CPUS
1426	int "Maximum number of CPUs (2-4096)"
1427	range 2 4096
1428	default "256"
1429
1430config HOTPLUG_CPU
1431	bool "Support for hot-pluggable CPUs"
1432	select GENERIC_IRQ_MIGRATION
1433	help
1434	  Say Y here to experiment with turning CPUs off and on.  CPUs
1435	  can be controlled through /sys/devices/system/cpu.
1436
1437# Common NUMA Features
1438config NUMA
1439	bool "NUMA Memory Allocation and Scheduler Support"
1440	select GENERIC_ARCH_NUMA
1441	select ACPI_NUMA if ACPI
1442	select OF_NUMA
1443	select HAVE_SETUP_PER_CPU_AREA
1444	select NEED_PER_CPU_EMBED_FIRST_CHUNK
1445	select NEED_PER_CPU_PAGE_FIRST_CHUNK
1446	select USE_PERCPU_NUMA_NODE_ID
1447	help
1448	  Enable NUMA (Non-Uniform Memory Access) support.
1449
1450	  The kernel will try to allocate memory used by a CPU on the
1451	  local memory of the CPU and add some more
1452	  NUMA awareness to the kernel.
1453
1454config NODES_SHIFT
1455	int "Maximum NUMA Nodes (as a power of 2)"
1456	range 1 10
1457	default "4"
1458	depends on NUMA
1459	help
1460	  Specify the maximum number of NUMA Nodes available on the target
1461	  system.  Increases memory reserved to accommodate various tables.
1462
1463source "kernel/Kconfig.hz"
1464
1465config ARCH_SPARSEMEM_ENABLE
1466	def_bool y
1467	select SPARSEMEM_VMEMMAP_ENABLE
1468	select SPARSEMEM_VMEMMAP
1469
1470config HW_PERF_EVENTS
1471	def_bool y
1472	depends on ARM_PMU
1473
1474# Supported by clang >= 7.0 or GCC >= 12.0.0
1475config CC_HAVE_SHADOW_CALL_STACK
1476	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1477
1478config PARAVIRT
1479	bool "Enable paravirtualization code"
1480	help
1481	  This changes the kernel so it can modify itself when it is run
1482	  under a hypervisor, potentially improving performance significantly
1483	  over full virtualization.
1484
1485config PARAVIRT_TIME_ACCOUNTING
1486	bool "Paravirtual steal time accounting"
1487	select PARAVIRT
1488	help
1489	  Select this option to enable fine granularity task steal time
1490	  accounting. Time spent executing other tasks in parallel with
1491	  the current vCPU is discounted from the vCPU power. To account for
1492	  that, there can be a small performance impact.
1493
1494	  If in doubt, say N here.
1495
1496config ARCH_SUPPORTS_KEXEC
1497	def_bool PM_SLEEP_SMP
1498
1499config ARCH_SUPPORTS_KEXEC_FILE
1500	def_bool y
1501
1502config ARCH_SELECTS_KEXEC_FILE
1503	def_bool y
1504	depends on KEXEC_FILE
1505	select HAVE_IMA_KEXEC if IMA
1506
1507config ARCH_SUPPORTS_KEXEC_SIG
1508	def_bool y
1509
1510config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG
1511	def_bool y
1512
1513config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG
1514	def_bool y
1515
1516config ARCH_SUPPORTS_CRASH_DUMP
1517	def_bool y
1518
1519config TRANS_TABLE
1520	def_bool y
1521	depends on HIBERNATION || KEXEC_CORE
1522
1523config XEN_DOM0
1524	def_bool y
1525	depends on XEN
1526
1527config XEN
1528	bool "Xen guest support on ARM64"
1529	depends on ARM64 && OF
1530	select SWIOTLB_XEN
1531	select PARAVIRT
1532	help
1533	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1534
1535# include/linux/mmzone.h requires the following to be true:
1536#
1537#   MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1538#
1539# so the maximum value of MAX_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1540#
1541#     | SECTION_SIZE_BITS |  PAGE_SHIFT  |  max MAX_ORDER  |  default MAX_ORDER |
1542# ----+-------------------+--------------+-----------------+--------------------+
1543# 4K  |       27          |      12      |       15        |         10         |
1544# 16K |       27          |      14      |       13        |         11         |
1545# 64K |       29          |      16      |       13        |         13         |
1546config ARCH_FORCE_MAX_ORDER
1547	int
1548	default "13" if ARM64_64K_PAGES
1549	default "11" if ARM64_16K_PAGES
1550	default "10"
1551	help
1552	  The kernel page allocator limits the size of maximal physically
1553	  contiguous allocations. The limit is called MAX_ORDER and it
1554	  defines the maximal power of two of number of pages that can be
1555	  allocated as a single contiguous block. This option allows
1556	  overriding the default setting when ability to allocate very
1557	  large blocks of physically contiguous memory is required.
1558
1559	  The maximal size of allocation cannot exceed the size of the
1560	  section, so the value of MAX_ORDER should satisfy
1561
1562	    MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1563
1564	  Don't change if unsure.
1565
1566config UNMAP_KERNEL_AT_EL0
1567	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1568	default y
1569	help
1570	  Speculation attacks against some high-performance processors can
1571	  be used to bypass MMU permission checks and leak kernel data to
1572	  userspace. This can be defended against by unmapping the kernel
1573	  when running in userspace, mapping it back in on exception entry
1574	  via a trampoline page in the vector table.
1575
1576	  If unsure, say Y.
1577
1578config MITIGATE_SPECTRE_BRANCH_HISTORY
1579	bool "Mitigate Spectre style attacks against branch history" if EXPERT
1580	default y
1581	help
1582	  Speculation attacks against some high-performance processors can
1583	  make use of branch history to influence future speculation.
1584	  When taking an exception from user-space, a sequence of branches
1585	  or a firmware call overwrites the branch history.
1586
1587config RODATA_FULL_DEFAULT_ENABLED
1588	bool "Apply r/o permissions of VM areas also to their linear aliases"
1589	default y
1590	help
1591	  Apply read-only attributes of VM areas to the linear alias of
1592	  the backing pages as well. This prevents code or read-only data
1593	  from being modified (inadvertently or intentionally) via another
1594	  mapping of the same memory page. This additional enhancement can
1595	  be turned off at runtime by passing rodata=[off|on] (and turned on
1596	  with rodata=full if this option is set to 'n')
1597
1598	  This requires the linear region to be mapped down to pages,
1599	  which may adversely affect performance in some cases.
1600
1601config ARM64_SW_TTBR0_PAN
1602	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1603	help
1604	  Enabling this option prevents the kernel from accessing
1605	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1606	  zeroed area and reserved ASID. The user access routines
1607	  restore the valid TTBR0_EL1 temporarily.
1608
1609config ARM64_TAGGED_ADDR_ABI
1610	bool "Enable the tagged user addresses syscall ABI"
1611	default y
1612	help
1613	  When this option is enabled, user applications can opt in to a
1614	  relaxed ABI via prctl() allowing tagged addresses to be passed
1615	  to system calls as pointer arguments. For details, see
1616	  Documentation/arch/arm64/tagged-address-abi.rst.
1617
1618menuconfig COMPAT
1619	bool "Kernel support for 32-bit EL0"
1620	depends on ARM64_4K_PAGES || EXPERT
1621	select HAVE_UID16
1622	select OLD_SIGSUSPEND3
1623	select COMPAT_OLD_SIGACTION
1624	help
1625	  This option enables support for a 32-bit EL0 running under a 64-bit
1626	  kernel at EL1. AArch32-specific components such as system calls,
1627	  the user helper functions, VFP support and the ptrace interface are
1628	  handled appropriately by the kernel.
1629
1630	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1631	  that you will only be able to execute AArch32 binaries that were compiled
1632	  with page size aligned segments.
1633
1634	  If you want to execute 32-bit userspace applications, say Y.
1635
1636if COMPAT
1637
1638config KUSER_HELPERS
1639	bool "Enable kuser helpers page for 32-bit applications"
1640	default y
1641	help
1642	  Warning: disabling this option may break 32-bit user programs.
1643
1644	  Provide kuser helpers to compat tasks. The kernel provides
1645	  helper code to userspace in read only form at a fixed location
1646	  to allow userspace to be independent of the CPU type fitted to
1647	  the system. This permits binaries to be run on ARMv4 through
1648	  to ARMv8 without modification.
1649
1650	  See Documentation/arch/arm/kernel_user_helpers.rst for details.
1651
1652	  However, the fixed address nature of these helpers can be used
1653	  by ROP (return orientated programming) authors when creating
1654	  exploits.
1655
1656	  If all of the binaries and libraries which run on your platform
1657	  are built specifically for your platform, and make no use of
1658	  these helpers, then you can turn this option off to hinder
1659	  such exploits. However, in that case, if a binary or library
1660	  relying on those helpers is run, it will not function correctly.
1661
1662	  Say N here only if you are absolutely certain that you do not
1663	  need these helpers; otherwise, the safe option is to say Y.
1664
1665config COMPAT_VDSO
1666	bool "Enable vDSO for 32-bit applications"
1667	depends on !CPU_BIG_ENDIAN
1668	depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1669	select GENERIC_COMPAT_VDSO
1670	default y
1671	help
1672	  Place in the process address space of 32-bit applications an
1673	  ELF shared object providing fast implementations of gettimeofday
1674	  and clock_gettime.
1675
1676	  You must have a 32-bit build of glibc 2.22 or later for programs
1677	  to seamlessly take advantage of this.
1678
1679config THUMB2_COMPAT_VDSO
1680	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1681	depends on COMPAT_VDSO
1682	default y
1683	help
1684	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1685	  otherwise with '-marm'.
1686
1687config COMPAT_ALIGNMENT_FIXUPS
1688	bool "Fix up misaligned multi-word loads and stores in user space"
1689
1690menuconfig ARMV8_DEPRECATED
1691	bool "Emulate deprecated/obsolete ARMv8 instructions"
1692	depends on SYSCTL
1693	help
1694	  Legacy software support may require certain instructions
1695	  that have been deprecated or obsoleted in the architecture.
1696
1697	  Enable this config to enable selective emulation of these
1698	  features.
1699
1700	  If unsure, say Y
1701
1702if ARMV8_DEPRECATED
1703
1704config SWP_EMULATION
1705	bool "Emulate SWP/SWPB instructions"
1706	help
1707	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1708	  they are always undefined. Say Y here to enable software
1709	  emulation of these instructions for userspace using LDXR/STXR.
1710	  This feature can be controlled at runtime with the abi.swp
1711	  sysctl which is disabled by default.
1712
1713	  In some older versions of glibc [<=2.8] SWP is used during futex
1714	  trylock() operations with the assumption that the code will not
1715	  be preempted. This invalid assumption may be more likely to fail
1716	  with SWP emulation enabled, leading to deadlock of the user
1717	  application.
1718
1719	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1720	  on an external transaction monitoring block called a global
1721	  monitor to maintain update atomicity. If your system does not
1722	  implement a global monitor, this option can cause programs that
1723	  perform SWP operations to uncached memory to deadlock.
1724
1725	  If unsure, say Y
1726
1727config CP15_BARRIER_EMULATION
1728	bool "Emulate CP15 Barrier instructions"
1729	help
1730	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1731	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1732	  strongly recommended to use the ISB, DSB, and DMB
1733	  instructions instead.
1734
1735	  Say Y here to enable software emulation of these
1736	  instructions for AArch32 userspace code. When this option is
1737	  enabled, CP15 barrier usage is traced which can help
1738	  identify software that needs updating. This feature can be
1739	  controlled at runtime with the abi.cp15_barrier sysctl.
1740
1741	  If unsure, say Y
1742
1743config SETEND_EMULATION
1744	bool "Emulate SETEND instruction"
1745	help
1746	  The SETEND instruction alters the data-endianness of the
1747	  AArch32 EL0, and is deprecated in ARMv8.
1748
1749	  Say Y here to enable software emulation of the instruction
1750	  for AArch32 userspace code. This feature can be controlled
1751	  at runtime with the abi.setend sysctl.
1752
1753	  Note: All the cpus on the system must have mixed endian support at EL0
1754	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1755	  endian - is hotplugged in after this feature has been enabled, there could
1756	  be unexpected results in the applications.
1757
1758	  If unsure, say Y
1759endif # ARMV8_DEPRECATED
1760
1761endif # COMPAT
1762
1763menu "ARMv8.1 architectural features"
1764
1765config ARM64_HW_AFDBM
1766	bool "Support for hardware updates of the Access and Dirty page flags"
1767	default y
1768	help
1769	  The ARMv8.1 architecture extensions introduce support for
1770	  hardware updates of the access and dirty information in page
1771	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1772	  capable processors, accesses to pages with PTE_AF cleared will
1773	  set this bit instead of raising an access flag fault.
1774	  Similarly, writes to read-only pages with the DBM bit set will
1775	  clear the read-only bit (AP[2]) instead of raising a
1776	  permission fault.
1777
1778	  Kernels built with this configuration option enabled continue
1779	  to work on pre-ARMv8.1 hardware and the performance impact is
1780	  minimal. If unsure, say Y.
1781
1782config ARM64_PAN
1783	bool "Enable support for Privileged Access Never (PAN)"
1784	default y
1785	help
1786	  Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1787	  prevents the kernel or hypervisor from accessing user-space (EL0)
1788	  memory directly.
1789
1790	  Choosing this option will cause any unprotected (not using
1791	  copy_to_user et al) memory access to fail with a permission fault.
1792
1793	  The feature is detected at runtime, and will remain as a 'nop'
1794	  instruction if the cpu does not implement the feature.
1795
1796config AS_HAS_LSE_ATOMICS
1797	def_bool $(as-instr,.arch_extension lse)
1798
1799config ARM64_LSE_ATOMICS
1800	bool
1801	default ARM64_USE_LSE_ATOMICS
1802	depends on AS_HAS_LSE_ATOMICS
1803
1804config ARM64_USE_LSE_ATOMICS
1805	bool "Atomic instructions"
1806	default y
1807	help
1808	  As part of the Large System Extensions, ARMv8.1 introduces new
1809	  atomic instructions that are designed specifically to scale in
1810	  very large systems.
1811
1812	  Say Y here to make use of these instructions for the in-kernel
1813	  atomic routines. This incurs a small overhead on CPUs that do
1814	  not support these instructions and requires the kernel to be
1815	  built with binutils >= 2.25 in order for the new instructions
1816	  to be used.
1817
1818endmenu # "ARMv8.1 architectural features"
1819
1820menu "ARMv8.2 architectural features"
1821
1822config AS_HAS_ARMV8_2
1823	def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1824
1825config AS_HAS_SHA3
1826	def_bool $(as-instr,.arch armv8.2-a+sha3)
1827
1828config ARM64_PMEM
1829	bool "Enable support for persistent memory"
1830	select ARCH_HAS_PMEM_API
1831	select ARCH_HAS_UACCESS_FLUSHCACHE
1832	help
1833	  Say Y to enable support for the persistent memory API based on the
1834	  ARMv8.2 DCPoP feature.
1835
1836	  The feature is detected at runtime, and the kernel will use DC CVAC
1837	  operations if DC CVAP is not supported (following the behaviour of
1838	  DC CVAP itself if the system does not define a point of persistence).
1839
1840config ARM64_RAS_EXTN
1841	bool "Enable support for RAS CPU Extensions"
1842	default y
1843	help
1844	  CPUs that support the Reliability, Availability and Serviceability
1845	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1846	  errors, classify them and report them to software.
1847
1848	  On CPUs with these extensions system software can use additional
1849	  barriers to determine if faults are pending and read the
1850	  classification from a new set of registers.
1851
1852	  Selecting this feature will allow the kernel to use these barriers
1853	  and access the new registers if the system supports the extension.
1854	  Platform RAS features may additionally depend on firmware support.
1855
1856config ARM64_CNP
1857	bool "Enable support for Common Not Private (CNP) translations"
1858	default y
1859	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1860	help
1861	  Common Not Private (CNP) allows translation table entries to
1862	  be shared between different PEs in the same inner shareable
1863	  domain, so the hardware can use this fact to optimise the
1864	  caching of such entries in the TLB.
1865
1866	  Selecting this option allows the CNP feature to be detected
1867	  at runtime, and does not affect PEs that do not implement
1868	  this feature.
1869
1870endmenu # "ARMv8.2 architectural features"
1871
1872menu "ARMv8.3 architectural features"
1873
1874config ARM64_PTR_AUTH
1875	bool "Enable support for pointer authentication"
1876	default y
1877	help
1878	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1879	  instructions for signing and authenticating pointers against secret
1880	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1881	  and other attacks.
1882
1883	  This option enables these instructions at EL0 (i.e. for userspace).
1884	  Choosing this option will cause the kernel to initialise secret keys
1885	  for each process at exec() time, with these keys being
1886	  context-switched along with the process.
1887
1888	  The feature is detected at runtime. If the feature is not present in
1889	  hardware it will not be advertised to userspace/KVM guest nor will it
1890	  be enabled.
1891
1892	  If the feature is present on the boot CPU but not on a late CPU, then
1893	  the late CPU will be parked. Also, if the boot CPU does not have
1894	  address auth and the late CPU has then the late CPU will still boot
1895	  but with the feature disabled. On such a system, this option should
1896	  not be selected.
1897
1898config ARM64_PTR_AUTH_KERNEL
1899	bool "Use pointer authentication for kernel"
1900	default y
1901	depends on ARM64_PTR_AUTH
1902	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1903	# Modern compilers insert a .note.gnu.property section note for PAC
1904	# which is only understood by binutils starting with version 2.33.1.
1905	depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1906	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1907	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1908	help
1909	  If the compiler supports the -mbranch-protection or
1910	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1911	  will cause the kernel itself to be compiled with return address
1912	  protection. In this case, and if the target hardware is known to
1913	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
1914	  disabled with minimal loss of protection.
1915
1916	  This feature works with FUNCTION_GRAPH_TRACER option only if
1917	  DYNAMIC_FTRACE_WITH_ARGS is enabled.
1918
1919config CC_HAS_BRANCH_PROT_PAC_RET
1920	# GCC 9 or later, clang 8 or later
1921	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1922
1923config CC_HAS_SIGN_RETURN_ADDRESS
1924	# GCC 7, 8
1925	def_bool $(cc-option,-msign-return-address=all)
1926
1927config AS_HAS_ARMV8_3
1928	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1929
1930config AS_HAS_CFI_NEGATE_RA_STATE
1931	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1932
1933config AS_HAS_LDAPR
1934	def_bool $(as-instr,.arch_extension rcpc)
1935
1936endmenu # "ARMv8.3 architectural features"
1937
1938menu "ARMv8.4 architectural features"
1939
1940config ARM64_AMU_EXTN
1941	bool "Enable support for the Activity Monitors Unit CPU extension"
1942	default y
1943	help
1944	  The activity monitors extension is an optional extension introduced
1945	  by the ARMv8.4 CPU architecture. This enables support for version 1
1946	  of the activity monitors architecture, AMUv1.
1947
1948	  To enable the use of this extension on CPUs that implement it, say Y.
1949
1950	  Note that for architectural reasons, firmware _must_ implement AMU
1951	  support when running on CPUs that present the activity monitors
1952	  extension. The required support is present in:
1953	    * Version 1.5 and later of the ARM Trusted Firmware
1954
1955	  For kernels that have this configuration enabled but boot with broken
1956	  firmware, you may need to say N here until the firmware is fixed.
1957	  Otherwise you may experience firmware panics or lockups when
1958	  accessing the counter registers. Even if you are not observing these
1959	  symptoms, the values returned by the register reads might not
1960	  correctly reflect reality. Most commonly, the value read will be 0,
1961	  indicating that the counter is not enabled.
1962
1963config AS_HAS_ARMV8_4
1964	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1965
1966config ARM64_TLB_RANGE
1967	bool "Enable support for tlbi range feature"
1968	default y
1969	depends on AS_HAS_ARMV8_4
1970	help
1971	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1972	  range of input addresses.
1973
1974	  The feature introduces new assembly instructions, and they were
1975	  support when binutils >= 2.30.
1976
1977endmenu # "ARMv8.4 architectural features"
1978
1979menu "ARMv8.5 architectural features"
1980
1981config AS_HAS_ARMV8_5
1982	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1983
1984config ARM64_BTI
1985	bool "Branch Target Identification support"
1986	default y
1987	help
1988	  Branch Target Identification (part of the ARMv8.5 Extensions)
1989	  provides a mechanism to limit the set of locations to which computed
1990	  branch instructions such as BR or BLR can jump.
1991
1992	  To make use of BTI on CPUs that support it, say Y.
1993
1994	  BTI is intended to provide complementary protection to other control
1995	  flow integrity protection mechanisms, such as the Pointer
1996	  authentication mechanism provided as part of the ARMv8.3 Extensions.
1997	  For this reason, it does not make sense to enable this option without
1998	  also enabling support for pointer authentication.  Thus, when
1999	  enabling this option you should also select ARM64_PTR_AUTH=y.
2000
2001	  Userspace binaries must also be specifically compiled to make use of
2002	  this mechanism.  If you say N here or the hardware does not support
2003	  BTI, such binaries can still run, but you get no additional
2004	  enforcement of branch destinations.
2005
2006config ARM64_BTI_KERNEL
2007	bool "Use Branch Target Identification for kernel"
2008	default y
2009	depends on ARM64_BTI
2010	depends on ARM64_PTR_AUTH_KERNEL
2011	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
2012	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
2013	depends on !CC_IS_GCC || GCC_VERSION >= 100100
2014	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
2015	depends on !CC_IS_GCC
2016	# https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
2017	depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
2018	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
2019	help
2020	  Build the kernel with Branch Target Identification annotations
2021	  and enable enforcement of this for kernel code. When this option
2022	  is enabled and the system supports BTI all kernel code including
2023	  modular code must have BTI enabled.
2024
2025config CC_HAS_BRANCH_PROT_PAC_RET_BTI
2026	# GCC 9 or later, clang 8 or later
2027	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2028
2029config ARM64_E0PD
2030	bool "Enable support for E0PD"
2031	default y
2032	help
2033	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
2034	  that EL0 accesses made via TTBR1 always fault in constant time,
2035	  providing similar benefits to KASLR as those provided by KPTI, but
2036	  with lower overhead and without disrupting legitimate access to
2037	  kernel memory such as SPE.
2038
2039	  This option enables E0PD for TTBR1 where available.
2040
2041config ARM64_AS_HAS_MTE
2042	# Initial support for MTE went in binutils 2.32.0, checked with
2043	# ".arch armv8.5-a+memtag" below. However, this was incomplete
2044	# as a late addition to the final architecture spec (LDGM/STGM)
2045	# is only supported in the newer 2.32.x and 2.33 binutils
2046	# versions, hence the extra "stgm" instruction check below.
2047	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2048
2049config ARM64_MTE
2050	bool "Memory Tagging Extension support"
2051	default y
2052	depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2053	depends on AS_HAS_ARMV8_5
2054	depends on AS_HAS_LSE_ATOMICS
2055	# Required for tag checking in the uaccess routines
2056	depends on ARM64_PAN
2057	select ARCH_HAS_SUBPAGE_FAULTS
2058	select ARCH_USES_HIGH_VMA_FLAGS
2059	select ARCH_USES_PG_ARCH_X
2060	help
2061	  Memory Tagging (part of the ARMv8.5 Extensions) provides
2062	  architectural support for run-time, always-on detection of
2063	  various classes of memory error to aid with software debugging
2064	  to eliminate vulnerabilities arising from memory-unsafe
2065	  languages.
2066
2067	  This option enables the support for the Memory Tagging
2068	  Extension at EL0 (i.e. for userspace).
2069
2070	  Selecting this option allows the feature to be detected at
2071	  runtime. Any secondary CPU not implementing this feature will
2072	  not be allowed a late bring-up.
2073
2074	  Userspace binaries that want to use this feature must
2075	  explicitly opt in. The mechanism for the userspace is
2076	  described in:
2077
2078	  Documentation/arch/arm64/memory-tagging-extension.rst.
2079
2080endmenu # "ARMv8.5 architectural features"
2081
2082menu "ARMv8.7 architectural features"
2083
2084config ARM64_EPAN
2085	bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2086	default y
2087	depends on ARM64_PAN
2088	help
2089	  Enhanced Privileged Access Never (EPAN) allows Privileged
2090	  Access Never to be used with Execute-only mappings.
2091
2092	  The feature is detected at runtime, and will remain disabled
2093	  if the cpu does not implement the feature.
2094endmenu # "ARMv8.7 architectural features"
2095
2096config ARM64_SVE
2097	bool "ARM Scalable Vector Extension support"
2098	default y
2099	help
2100	  The Scalable Vector Extension (SVE) is an extension to the AArch64
2101	  execution state which complements and extends the SIMD functionality
2102	  of the base architecture to support much larger vectors and to enable
2103	  additional vectorisation opportunities.
2104
2105	  To enable use of this extension on CPUs that implement it, say Y.
2106
2107	  On CPUs that support the SVE2 extensions, this option will enable
2108	  those too.
2109
2110	  Note that for architectural reasons, firmware _must_ implement SVE
2111	  support when running on SVE capable hardware.  The required support
2112	  is present in:
2113
2114	    * version 1.5 and later of the ARM Trusted Firmware
2115	    * the AArch64 boot wrapper since commit 5e1261e08abf
2116	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
2117
2118	  For other firmware implementations, consult the firmware documentation
2119	  or vendor.
2120
2121	  If you need the kernel to boot on SVE-capable hardware with broken
2122	  firmware, you may need to say N here until you get your firmware
2123	  fixed.  Otherwise, you may experience firmware panics or lockups when
2124	  booting the kernel.  If unsure and you are not observing these
2125	  symptoms, you should assume that it is safe to say Y.
2126
2127config ARM64_SME
2128	bool "ARM Scalable Matrix Extension support"
2129	default y
2130	depends on ARM64_SVE
2131	help
2132	  The Scalable Matrix Extension (SME) is an extension to the AArch64
2133	  execution state which utilises a substantial subset of the SVE
2134	  instruction set, together with the addition of new architectural
2135	  register state capable of holding two dimensional matrix tiles to
2136	  enable various matrix operations.
2137
2138config ARM64_PSEUDO_NMI
2139	bool "Support for NMI-like interrupts"
2140	select ARM_GIC_V3
2141	help
2142	  Adds support for mimicking Non-Maskable Interrupts through the use of
2143	  GIC interrupt priority. This support requires version 3 or later of
2144	  ARM GIC.
2145
2146	  This high priority configuration for interrupts needs to be
2147	  explicitly enabled by setting the kernel parameter
2148	  "irqchip.gicv3_pseudo_nmi" to 1.
2149
2150	  If unsure, say N
2151
2152if ARM64_PSEUDO_NMI
2153config ARM64_DEBUG_PRIORITY_MASKING
2154	bool "Debug interrupt priority masking"
2155	help
2156	  This adds runtime checks to functions enabling/disabling
2157	  interrupts when using priority masking. The additional checks verify
2158	  the validity of ICC_PMR_EL1 when calling concerned functions.
2159
2160	  If unsure, say N
2161endif # ARM64_PSEUDO_NMI
2162
2163config RELOCATABLE
2164	bool "Build a relocatable kernel image" if EXPERT
2165	select ARCH_HAS_RELR
2166	default y
2167	help
2168	  This builds the kernel as a Position Independent Executable (PIE),
2169	  which retains all relocation metadata required to relocate the
2170	  kernel binary at runtime to a different virtual address than the
2171	  address it was linked at.
2172	  Since AArch64 uses the RELA relocation format, this requires a
2173	  relocation pass at runtime even if the kernel is loaded at the
2174	  same address it was linked at.
2175
2176config RANDOMIZE_BASE
2177	bool "Randomize the address of the kernel image"
2178	select RELOCATABLE
2179	help
2180	  Randomizes the virtual address at which the kernel image is
2181	  loaded, as a security feature that deters exploit attempts
2182	  relying on knowledge of the location of kernel internals.
2183
2184	  It is the bootloader's job to provide entropy, by passing a
2185	  random u64 value in /chosen/kaslr-seed at kernel entry.
2186
2187	  When booting via the UEFI stub, it will invoke the firmware's
2188	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2189	  to the kernel proper. In addition, it will randomise the physical
2190	  location of the kernel Image as well.
2191
2192	  If unsure, say N.
2193
2194config RANDOMIZE_MODULE_REGION_FULL
2195	bool "Randomize the module region over a 2 GB range"
2196	depends on RANDOMIZE_BASE
2197	default y
2198	help
2199	  Randomizes the location of the module region inside a 2 GB window
2200	  covering the core kernel. This way, it is less likely for modules
2201	  to leak information about the location of core kernel data structures
2202	  but it does imply that function calls between modules and the core
2203	  kernel will need to be resolved via veneers in the module PLT.
2204
2205	  When this option is not set, the module region will be randomized over
2206	  a limited range that contains the [_stext, _etext] interval of the
2207	  core kernel, so branch relocations are almost always in range unless
2208	  the region is exhausted. In this particular case of region
2209	  exhaustion, modules might be able to fall back to a larger 2GB area.
2210
2211config CC_HAVE_STACKPROTECTOR_SYSREG
2212	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2213
2214config STACKPROTECTOR_PER_TASK
2215	def_bool y
2216	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2217
2218config UNWIND_PATCH_PAC_INTO_SCS
2219	bool "Enable shadow call stack dynamically using code patching"
2220	# needs Clang with https://reviews.llvm.org/D111780 incorporated
2221	depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2222	depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2223	depends on SHADOW_CALL_STACK
2224	select UNWIND_TABLES
2225	select DYNAMIC_SCS
2226
2227endmenu # "Kernel Features"
2228
2229menu "Boot options"
2230
2231config ARM64_ACPI_PARKING_PROTOCOL
2232	bool "Enable support for the ARM64 ACPI parking protocol"
2233	depends on ACPI
2234	help
2235	  Enable support for the ARM64 ACPI parking protocol. If disabled
2236	  the kernel will not allow booting through the ARM64 ACPI parking
2237	  protocol even if the corresponding data is present in the ACPI
2238	  MADT table.
2239
2240config CMDLINE
2241	string "Default kernel command string"
2242	default ""
2243	help
2244	  Provide a set of default command-line options at build time by
2245	  entering them here. As a minimum, you should specify the the
2246	  root device (e.g. root=/dev/nfs).
2247
2248choice
2249	prompt "Kernel command line type" if CMDLINE != ""
2250	default CMDLINE_FROM_BOOTLOADER
2251	help
2252	  Choose how the kernel will handle the provided default kernel
2253	  command line string.
2254
2255config CMDLINE_FROM_BOOTLOADER
2256	bool "Use bootloader kernel arguments if available"
2257	help
2258	  Uses the command-line options passed by the boot loader. If
2259	  the boot loader doesn't provide any, the default kernel command
2260	  string provided in CMDLINE will be used.
2261
2262config CMDLINE_FORCE
2263	bool "Always use the default kernel command string"
2264	help
2265	  Always use the default kernel command string, even if the boot
2266	  loader passes other arguments to the kernel.
2267	  This is useful if you cannot or don't want to change the
2268	  command-line options your boot loader passes to the kernel.
2269
2270endchoice
2271
2272config EFI_STUB
2273	bool
2274
2275config EFI
2276	bool "UEFI runtime support"
2277	depends on OF && !CPU_BIG_ENDIAN
2278	depends on KERNEL_MODE_NEON
2279	select ARCH_SUPPORTS_ACPI
2280	select LIBFDT
2281	select UCS2_STRING
2282	select EFI_PARAMS_FROM_FDT
2283	select EFI_RUNTIME_WRAPPERS
2284	select EFI_STUB
2285	select EFI_GENERIC_STUB
2286	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2287	default y
2288	help
2289	  This option provides support for runtime services provided
2290	  by UEFI firmware (such as non-volatile variables, realtime
2291	  clock, and platform reset). A UEFI stub is also provided to
2292	  allow the kernel to be booted as an EFI application. This
2293	  is only useful on systems that have UEFI firmware.
2294
2295config DMI
2296	bool "Enable support for SMBIOS (DMI) tables"
2297	depends on EFI
2298	default y
2299	help
2300	  This enables SMBIOS/DMI feature for systems.
2301
2302	  This option is only useful on systems that have UEFI firmware.
2303	  However, even with this option, the resultant kernel should
2304	  continue to boot on existing non-UEFI platforms.
2305
2306endmenu # "Boot options"
2307
2308menu "Power management options"
2309
2310source "kernel/power/Kconfig"
2311
2312config ARCH_HIBERNATION_POSSIBLE
2313	def_bool y
2314	depends on CPU_PM
2315
2316config ARCH_HIBERNATION_HEADER
2317	def_bool y
2318	depends on HIBERNATION
2319
2320config ARCH_SUSPEND_POSSIBLE
2321	def_bool y
2322
2323endmenu # "Power management options"
2324
2325menu "CPU Power Management"
2326
2327source "drivers/cpuidle/Kconfig"
2328
2329source "drivers/cpufreq/Kconfig"
2330
2331endmenu # "CPU Power Management"
2332
2333source "drivers/acpi/Kconfig"
2334
2335source "arch/arm64/kvm/Kconfig"
2336
2337