1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4#
5
6config ARC
7	def_bool y
8	select ARC_TIMERS
9	select ARCH_HAS_CACHE_LINE_SIZE
10	select ARCH_HAS_DEBUG_VM_PGTABLE
11	select ARCH_HAS_DMA_PREP_COHERENT
12	select ARCH_HAS_PTE_SPECIAL
13	select ARCH_HAS_SETUP_DMA_OPS
14	select ARCH_HAS_SYNC_DMA_FOR_CPU
15	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16	select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17	select ARCH_32BIT_OFF_T
18	select BUILDTIME_TABLE_SORT
19	select CLONE_BACKWARDS
20	select COMMON_CLK
21	select DMA_DIRECT_REMAP
22	select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23	# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
24	select GENERIC_IRQ_SHOW
25	select GENERIC_PCI_IOMAP
26	select GENERIC_PENDING_IRQ if SMP
27	select GENERIC_SCHED_CLOCK
28	select GENERIC_SMP_IDLE_THREAD
29	select HAVE_ARCH_KGDB
30	select HAVE_ARCH_TRACEHOOK
31	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
32	select HAVE_DEBUG_STACKOVERFLOW
33	select HAVE_DEBUG_KMEMLEAK
34	select HAVE_IOREMAP_PROT
35	select HAVE_KERNEL_GZIP
36	select HAVE_KERNEL_LZMA
37	select HAVE_KPROBES
38	select HAVE_KRETPROBES
39	select HAVE_REGS_AND_STACK_ACCESS_API
40	select HAVE_MOD_ARCH_SPECIFIC
41	select HAVE_PERF_EVENTS
42	select HAVE_SYSCALL_TRACEPOINTS
43	select IRQ_DOMAIN
44	select MODULES_USE_ELF_RELA
45	select OF
46	select OF_EARLY_FLATTREE
47	select PCI_SYSCALL if PCI
48	select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
49	select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
50	select TRACE_IRQFLAGS_SUPPORT
51
52config LOCKDEP_SUPPORT
53	def_bool y
54
55config SCHED_OMIT_FRAME_POINTER
56	def_bool y
57
58config GENERIC_CSUM
59	def_bool y
60
61config ARCH_FLATMEM_ENABLE
62	def_bool y
63
64config MMU
65	def_bool y
66
67config NO_IOPORT_MAP
68	def_bool y
69
70config GENERIC_CALIBRATE_DELAY
71	def_bool y
72
73config GENERIC_HWEIGHT
74	def_bool y
75
76config STACKTRACE_SUPPORT
77	def_bool y
78	select STACKTRACE
79
80menu "ARC Architecture Configuration"
81
82menu "ARC Platform/SoC/Board"
83
84source "arch/arc/plat-tb10x/Kconfig"
85source "arch/arc/plat-axs10x/Kconfig"
86source "arch/arc/plat-hsdk/Kconfig"
87
88endmenu
89
90choice
91	prompt "ARC Instruction Set"
92	default ISA_ARCV2
93
94config ISA_ARCOMPACT
95	bool "ARCompact ISA"
96	select CPU_NO_EFFICIENT_FFS
97	help
98	  The original ARC ISA of ARC600/700 cores
99
100config ISA_ARCV2
101	bool "ARC ISA v2"
102	select ARC_TIMERS_64BIT
103	help
104	  ISA for the Next Generation ARC-HS cores
105
106endchoice
107
108menu "ARC CPU Configuration"
109
110choice
111	prompt "ARC Core"
112	default ARC_CPU_770 if ISA_ARCOMPACT
113	default ARC_CPU_HS if ISA_ARCV2
114
115config ARC_CPU_770
116	bool "ARC770"
117	depends on ISA_ARCOMPACT
118	select ARC_HAS_SWAPE
119	help
120	  Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
121	  This core has a bunch of cool new features:
122	  -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
123	           Shared Address Spaces (for sharing TLB entries in MMU)
124	  -Caches: New Prog Model, Region Flush
125	  -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
126
127config ARC_CPU_HS
128	bool "ARC-HS"
129	depends on ISA_ARCV2
130	help
131	  Support for ARC HS38x Cores based on ARCv2 ISA
132	  The notable features are:
133	    - SMP configurations of up to 4 cores with coherency
134	    - Optional L2 Cache and IO-Coherency
135	    - Revised Interrupt Architecture (multiple priorites, reg banks,
136	        auto stack switch, auto regfile save/restore)
137	    - MMUv4 (PIPT dcache, Huge Pages)
138	    - Instructions for
139		* 64bit load/store: LDD, STD
140		* Hardware assisted divide/remainder: DIV, REM
141		* Function prologue/epilogue: ENTER_S, LEAVE_S
142		* IRQ enable/disable: CLRI, SETI
143		* pop count: FFS, FLS
144		* SETcc, BMSKN, XBFU...
145
146endchoice
147
148config ARC_TUNE_MCPU
149	string "Override default -mcpu compiler flag"
150	default ""
151	help
152	  Override default -mcpu=xxx compiler flag (which is set depending on
153	  the ISA version) with the specified value.
154	  NOTE: If specified flag isn't supported by current compiler the
155	  ISA default value will be used as a fallback.
156
157config CPU_BIG_ENDIAN
158	bool "Enable Big Endian Mode"
159	help
160	  Build kernel for Big Endian Mode of ARC CPU
161
162config SMP
163	bool "Symmetric Multi-Processing"
164	select ARC_MCIP if ISA_ARCV2
165	help
166	  This enables support for systems with more than one CPU.
167
168if SMP
169
170config NR_CPUS
171	int "Maximum number of CPUs (2-4096)"
172	range 2 4096
173	default "4"
174
175config ARC_SMP_HALT_ON_RESET
176	bool "Enable Halt-on-reset boot mode"
177	help
178	  In SMP configuration cores can be configured as Halt-on-reset
179	  or they could all start at same time. For Halt-on-reset, non
180	  masters are parked until Master kicks them so they can start off
181	  at designated entry point. For other case, all jump to common
182	  entry point and spin wait for Master's signal.
183
184endif #SMP
185
186config ARC_MCIP
187	bool "ARConnect Multicore IP (MCIP) Support "
188	depends on ISA_ARCV2
189	default y if SMP
190	help
191	  This IP block enables SMP in ARC-HS38 cores.
192	  It provides for cross-core interrupts, multi-core debug
193	  hardware semaphores, shared memory,....
194
195menuconfig ARC_CACHE
196	bool "Enable Cache Support"
197	default y
198
199if ARC_CACHE
200
201config ARC_CACHE_LINE_SHIFT
202	int "Cache Line Length (as power of 2)"
203	range 5 7
204	default "6"
205	help
206	  Starting with ARC700 4.9, Cache line length is configurable,
207	  This option specifies "N", with Line-len = 2 power N
208	  So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
209	  Linux only supports same line lengths for I and D caches.
210
211config ARC_HAS_ICACHE
212	bool "Use Instruction Cache"
213	default y
214
215config ARC_HAS_DCACHE
216	bool "Use Data Cache"
217	default y
218
219config ARC_CACHE_PAGES
220	bool "Per Page Cache Control"
221	default y
222	depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
223	help
224	  This can be used to over-ride the global I/D Cache Enable on a
225	  per-page basis (but only for pages accessed via MMU such as
226	  Kernel Virtual address or User Virtual Address)
227	  TLB entries have a per-page Cache Enable Bit.
228	  Note that Global I/D ENABLE + Per Page DISABLE works but corollary
229	  Global DISABLE + Per Page ENABLE won't work
230
231config ARC_CACHE_VIPT_ALIASING
232	bool "Support VIPT Aliasing D$"
233	depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
234
235endif #ARC_CACHE
236
237config ARC_HAS_ICCM
238	bool "Use ICCM"
239	help
240	  Single Cycle RAMS to store Fast Path Code
241
242config ARC_ICCM_SZ
243	int "ICCM Size in KB"
244	default "64"
245	depends on ARC_HAS_ICCM
246
247config ARC_HAS_DCCM
248	bool "Use DCCM"
249	help
250	  Single Cycle RAMS to store Fast Path Data
251
252config ARC_DCCM_SZ
253	int "DCCM Size in KB"
254	default "64"
255	depends on ARC_HAS_DCCM
256
257config ARC_DCCM_BASE
258	hex "DCCM map address"
259	default "0xA0000000"
260	depends on ARC_HAS_DCCM
261
262choice
263	prompt "MMU Version"
264	default ARC_MMU_V3 if ISA_ARCOMPACT
265	default ARC_MMU_V4 if ISA_ARCV2
266
267config ARC_MMU_V3
268	bool "MMU v3"
269	depends on ISA_ARCOMPACT
270	help
271	  Introduced with ARC700 4.10: New Features
272	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
273	  Shared Address Spaces (SASID)
274
275config ARC_MMU_V4
276	bool "MMU v4"
277	depends on ISA_ARCV2
278
279endchoice
280
281
282choice
283	prompt "MMU Page Size"
284	default ARC_PAGE_SIZE_8K
285
286config ARC_PAGE_SIZE_8K
287	bool "8KB"
288	help
289	  Choose between 8k vs 16k
290
291config ARC_PAGE_SIZE_16K
292	bool "16KB"
293
294config ARC_PAGE_SIZE_4K
295	bool "4KB"
296	depends on ARC_MMU_V3 || ARC_MMU_V4
297
298endchoice
299
300choice
301	prompt "MMU Super Page Size"
302	depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
303	default ARC_HUGEPAGE_2M
304
305config ARC_HUGEPAGE_2M
306	bool "2MB"
307
308config ARC_HUGEPAGE_16M
309	bool "16MB"
310
311endchoice
312
313config PGTABLE_LEVELS
314	int "Number of Page table levels"
315	default 2
316
317config ARC_COMPACT_IRQ_LEVELS
318	depends on ISA_ARCOMPACT
319	bool "Setup Timer IRQ as high Priority"
320	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
321	depends on !SMP
322
323config ARC_FPU_SAVE_RESTORE
324	bool "Enable FPU state persistence across context switch"
325	help
326	  ARCompact FPU has internal registers to assist with Double precision
327	  Floating Point operations. There are control and stauts registers
328	  for floating point exceptions and rounding modes. These are
329	  preserved across task context switch when enabled.
330
331config ARC_CANT_LLSC
332	def_bool n
333
334config ARC_HAS_LLSC
335	bool "Insn: LLOCK/SCOND (efficient atomic ops)"
336	default y
337	depends on !ARC_CANT_LLSC
338
339config ARC_HAS_SWAPE
340	bool "Insn: SWAPE (endian-swap)"
341	default y
342
343if ISA_ARCV2
344
345config ARC_USE_UNALIGNED_MEM_ACCESS
346	bool "Enable unaligned access in HW"
347	default y
348	select HAVE_EFFICIENT_UNALIGNED_ACCESS
349	help
350	  The ARC HS architecture supports unaligned memory access
351	  which is disabled by default. Enable unaligned access in
352	  hardware and use software to use it
353
354config ARC_HAS_LL64
355	bool "Insn: 64bit LDD/STD"
356	help
357	  Enable gcc to generate 64-bit load/store instructions
358	  ISA mandates even/odd registers to allow encoding of two
359	  dest operands with 2 possible source operands.
360	default y
361
362config ARC_HAS_DIV_REM
363	bool "Insn: div, divu, rem, remu"
364	default y
365
366config ARC_HAS_ACCL_REGS
367	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
368	default y
369	help
370	  Depending on the configuration, CPU can contain accumulator reg-pair
371	  (also referred to as r58:r59). These can also be used by gcc as GPR so
372	  kernel needs to save/restore per process
373
374config ARC_DSP_HANDLED
375	def_bool n
376
377config ARC_DSP_SAVE_RESTORE_REGS
378	def_bool n
379
380choice
381	prompt "DSP support"
382	default ARC_DSP_NONE
383	help
384	  Depending on the configuration, CPU can contain DSP registers
385	  (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
386	  Below are options describing how to handle these registers in
387	  interrupt entry / exit and in context switch.
388
389config ARC_DSP_NONE
390	bool "No DSP extension presence in HW"
391	help
392	  No DSP extension presence in HW
393
394config ARC_DSP_KERNEL
395	bool "DSP extension in HW, no support for userspace"
396	select ARC_HAS_ACCL_REGS
397	select ARC_DSP_HANDLED
398	help
399	  DSP extension presence in HW, no support for DSP-enabled userspace
400	  applications. We don't save / restore DSP registers and only do
401	  some minimal preparations so userspace won't be able to break kernel
402
403config ARC_DSP_USERSPACE
404	bool "Support DSP for userspace apps"
405	select ARC_HAS_ACCL_REGS
406	select ARC_DSP_HANDLED
407	select ARC_DSP_SAVE_RESTORE_REGS
408	help
409	  DSP extension presence in HW, support save / restore DSP registers to
410	  run DSP-enabled userspace applications
411
412config ARC_DSP_AGU_USERSPACE
413	bool "Support DSP with AGU for userspace apps"
414	select ARC_HAS_ACCL_REGS
415	select ARC_DSP_HANDLED
416	select ARC_DSP_SAVE_RESTORE_REGS
417	help
418	  DSP and AGU extensions presence in HW, support save / restore DSP
419	  and AGU registers to run DSP-enabled userspace applications
420endchoice
421
422config ARC_IRQ_NO_AUTOSAVE
423	bool "Disable hardware autosave regfile on interrupts"
424	default n
425	help
426	  On HS cores, taken interrupt auto saves the regfile on stack.
427	  This is programmable and can be optionally disabled in which case
428	  software INTERRUPT_PROLOGUE/EPILGUE do the needed work
429
430config ARC_LPB_DISABLE
431	bool "Disable loop buffer (LPB)"
432	help
433	  On HS cores, loop buffer (LPB) is programmable in runtime and can
434	  be optionally disabled.
435
436endif # ISA_ARCV2
437
438endmenu   # "ARC CPU Configuration"
439
440config LINUX_LINK_BASE
441	hex "Kernel link address"
442	default "0x80000000"
443	help
444	  ARC700 divides the 32 bit phy address space into two equal halves
445	  -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
446	  -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
447	  Typically Linux kernel is linked at the start of untransalted addr,
448	  hence the default value of 0x8zs.
449	  However some customers have peripherals mapped at this addr, so
450	  Linux needs to be scooted a bit.
451	  If you don't know what the above means, leave this setting alone.
452	  This needs to match memory start address specified in Device Tree
453
454config LINUX_RAM_BASE
455	hex "RAM base address"
456	default LINUX_LINK_BASE
457	help
458	  By default Linux is linked at base of RAM. However in some special
459	  cases (such as HSDK), Linux can't be linked at start of DDR, hence
460	  this option.
461
462config HIGHMEM
463	bool "High Memory Support"
464	select HAVE_ARCH_PFN_VALID
465	select KMAP_LOCAL
466	help
467	  With ARC 2G:2G address split, only upper 2G is directly addressable by
468	  kernel. Enable this to potentially allow access to rest of 2G and PAE
469	  in future
470
471config ARC_HAS_PAE40
472	bool "Support for the 40-bit Physical Address Extension"
473	depends on ISA_ARCV2
474	select HIGHMEM
475	select PHYS_ADDR_T_64BIT
476	help
477	  Enable access to physical memory beyond 4G, only supported on
478	  ARC cores with 40 bit Physical Addressing support
479
480config ARC_KVADDR_SIZE
481	int "Kernel Virtual Address Space size (MB)"
482	range 0 512
483	default "256"
484	help
485	  The kernel address space is carved out of 256MB of translated address
486	  space for catering to vmalloc, modules, pkmap, fixmap. This however may
487	  not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
488	  this to be stretched to 512 MB (by extending into the reserved
489	  kernel-user gutter)
490
491config ARC_CURR_IN_REG
492	bool "Dedicate Register r25 for current_task pointer"
493	default y
494	help
495	  This reserved Register R25 to point to Current Task in
496	  kernel mode. This saves memory access for each such access
497
498
499config ARC_EMUL_UNALIGNED
500	bool "Emulate unaligned memory access (userspace only)"
501	select SYSCTL_ARCH_UNALIGN_NO_WARN
502	select SYSCTL_ARCH_UNALIGN_ALLOW
503	depends on ISA_ARCOMPACT
504	help
505	  This enables misaligned 16 & 32 bit memory access from user space.
506	  Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
507	  potential bugs in code
508
509config HZ
510	int "Timer Frequency"
511	default 100
512
513config ARC_METAWARE_HLINK
514	bool "Support for Metaware debugger assisted Host access"
515	help
516	  This options allows a Linux userland apps to directly access
517	  host file system (open/creat/read/write etc) with help from
518	  Metaware Debugger. This can come in handy for Linux-host communication
519	  when there is no real usable peripheral such as EMAC.
520
521menuconfig ARC_DBG
522	bool "ARC debugging"
523	default y
524
525if ARC_DBG
526
527config ARC_DW2_UNWIND
528	bool "Enable DWARF specific kernel stack unwind"
529	default y
530	select KALLSYMS
531	help
532	  Compiles the kernel with DWARF unwind information and can be used
533	  to get stack backtraces.
534
535	  If you say Y here the resulting kernel image will be slightly larger
536	  but not slower, and it will give very useful debugging information.
537	  If you don't debug the kernel, you can say N, but we may not be able
538	  to solve problems without frame unwind information
539
540config ARC_DBG_JUMP_LABEL
541	bool "Paranoid checks in Static Keys (jump labels) code"
542	depends on JUMP_LABEL
543	default y if STATIC_KEYS_SELFTEST
544	help
545	  Enable paranoid checks and self-test of both ARC-specific and generic
546	  part of static keys (jump labels) related code.
547endif
548
549config ARC_BUILTIN_DTB_NAME
550	string "Built in DTB"
551	help
552	  Set the name of the DTB to embed in the vmlinux binary
553	  Leaving it blank selects the minimal "skeleton" dtb
554
555endmenu	 # "ARC Architecture Configuration"
556
557config FORCE_MAX_ZONEORDER
558	int "Maximum zone order"
559	default "12" if ARC_HUGEPAGE_16M
560	default "11"
561
562source "kernel/power/Kconfig"
563