1# SPDX-License-Identifier: GPL-2.0-only
2if ARCH_TEGRA
3
4# 32-bit ARM SoCs
5if ARM
6
7config ARCH_TEGRA_2x_SOC
8	bool "Enable support for Tegra20 family"
9	select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
10	select ARM_ERRATA_720789
11	select ARM_ERRATA_754327 if SMP
12	select ARM_ERRATA_764369 if SMP
13	select PINCTRL_TEGRA20
14	select PL310_ERRATA_727915 if CACHE_L2X0
15	select PL310_ERRATA_769419 if CACHE_L2X0
16	select SOC_TEGRA_FLOWCTRL
17	select SOC_TEGRA_PMC
18	select SOC_TEGRA20_VOLTAGE_COUPLER if REGULATOR
19	select TEGRA_TIMER
20	help
21	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
22	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
23
24config ARCH_TEGRA_3x_SOC
25	bool "Enable support for Tegra30 family"
26	select ARM_ERRATA_754322
27	select ARM_ERRATA_764369 if SMP
28	select PINCTRL_TEGRA30
29	select PL310_ERRATA_769419 if CACHE_L2X0
30	select SOC_TEGRA_FLOWCTRL
31	select SOC_TEGRA_PMC
32	select SOC_TEGRA30_VOLTAGE_COUPLER if REGULATOR
33	select TEGRA_TIMER
34	help
35	  Support for NVIDIA Tegra T30 processor family, based on the
36	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
37
38config ARCH_TEGRA_114_SOC
39	bool "Enable support for Tegra114 family"
40	select ARM_ERRATA_798181 if SMP
41	select HAVE_ARM_ARCH_TIMER
42	select PINCTRL_TEGRA114
43	select SOC_TEGRA_FLOWCTRL
44	select SOC_TEGRA_PMC
45	select TEGRA_TIMER
46	help
47	  Support for NVIDIA Tegra T114 processor family, based on the
48	  ARM CortexA15MP CPU
49
50config ARCH_TEGRA_124_SOC
51	bool "Enable support for Tegra124 family"
52	select HAVE_ARM_ARCH_TIMER
53	select PINCTRL_TEGRA124
54	select SOC_TEGRA_FLOWCTRL
55	select SOC_TEGRA_PMC
56	select TEGRA_TIMER
57	help
58	  Support for NVIDIA Tegra T124 processor family, based on the
59	  ARM CortexA15MP CPU
60
61endif
62
63# 64-bit ARM SoCs
64if ARM64
65
66config ARCH_TEGRA_132_SOC
67	bool "NVIDIA Tegra132 SoC"
68	select PINCTRL_TEGRA124
69	select SOC_TEGRA_FLOWCTRL
70	select SOC_TEGRA_PMC
71	help
72	  Enable support for NVIDIA Tegra132 SoC, based on the Denver
73	  ARMv8 CPU.  The Tegra132 SoC is similar to the Tegra124 SoC,
74	  but contains an NVIDIA Denver CPU complex in place of
75	  Tegra124's "4+1" Cortex-A15 CPU complex.
76
77config ARCH_TEGRA_210_SOC
78	bool "NVIDIA Tegra210 SoC"
79	select PINCTRL_TEGRA210
80	select SOC_TEGRA_FLOWCTRL
81	select SOC_TEGRA_PMC
82	select TEGRA_TIMER
83	help
84	  Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
85	  the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
86	  cores in a switched configuration. It features a GPU of the Maxwell
87	  architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1
88	  and providing 256 CUDA cores. It supports hardware-accelerated en-
89	  and decoding of various video standards including H.265, H.264 and
90	  VP8 at 4K resolution and up to 60 fps.
91
92	  Besides the multimedia features it also comes with a variety of I/O
93	  controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
94	  name only a few.
95
96config ARCH_TEGRA_186_SOC
97	bool "NVIDIA Tegra186 SoC"
98	select MAILBOX
99	select TEGRA_BPMP
100	select TEGRA_HSP_MBOX
101	select TEGRA_IVC
102	select SOC_TEGRA_PMC
103	help
104	  Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
105	  combination of Denver and Cortex-A57 CPU cores and a GPU based on
106	  the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
107	  used for audio processing, hardware video encoders/decoders with
108	  multi-format support, ISP for image capture processing and BPMP for
109	  power management.
110
111config ARCH_TEGRA_194_SOC
112	bool "NVIDIA Tegra194 SoC"
113	select MAILBOX
114	select PINCTRL_TEGRA194
115	select TEGRA_BPMP
116	select TEGRA_HSP_MBOX
117	select TEGRA_IVC
118	select SOC_TEGRA_PMC
119	help
120	  Enable support for the NVIDIA Tegra194 SoC.
121
122config ARCH_TEGRA_234_SOC
123	bool "NVIDIA Tegra234 SoC"
124	select MAILBOX
125	select TEGRA_BPMP
126	select TEGRA_HSP_MBOX
127	select TEGRA_IVC
128	select SOC_TEGRA_PMC
129	help
130	  Enable support for the NVIDIA Tegra234 SoC.
131
132endif
133endif
134
135config SOC_TEGRA_FUSE
136	def_bool y
137	depends on ARCH_TEGRA
138	select SOC_BUS
139
140config SOC_TEGRA_FLOWCTRL
141	bool
142
143config SOC_TEGRA_PMC
144	bool
145	select GENERIC_PINCONF
146	select PM_OPP
147	select PM_GENERIC_DOMAINS
148	select REGMAP
149
150config SOC_TEGRA_POWERGATE_BPMP
151	def_bool y
152	depends on PM_GENERIC_DOMAINS
153	depends on TEGRA_BPMP
154
155config SOC_TEGRA20_VOLTAGE_COUPLER
156	bool "Voltage scaling support for Tegra20 SoCs"
157	depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
158	depends on REGULATOR
159
160config SOC_TEGRA30_VOLTAGE_COUPLER
161	bool "Voltage scaling support for Tegra30 SoCs"
162	depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
163	depends on REGULATOR
164
165config SOC_TEGRA_CBB
166	tristate "Tegra driver to handle error from CBB"
167	depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC
168	default y
169	help
170	  Support for handling error from Tegra Control Backbone(CBB).
171	  This driver handles the errors from CBB and prints debug
172	  information about the failed transactions.
173