1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21 #define _ASM_X86_AMD_IOMMU_TYPES_H
22
23 #include <linux/types.h>
24 #include <linux/mutex.h>
25 #include <linux/list.h>
26 #include <linux/spinlock.h>
27
28 /*
29 * Maximum number of IOMMUs supported
30 */
31 #define MAX_IOMMUS 32
32
33 /*
34 * some size calculation constants
35 */
36 #define DEV_TABLE_ENTRY_SIZE 32
37 #define ALIAS_TABLE_ENTRY_SIZE 2
38 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
39
40 /* Length of the MMIO region for the AMD IOMMU */
41 #define MMIO_REGION_LENGTH 0x4000
42
43 /* Capability offsets used by the driver */
44 #define MMIO_CAP_HDR_OFFSET 0x00
45 #define MMIO_RANGE_OFFSET 0x0c
46 #define MMIO_MISC_OFFSET 0x10
47
48 /* Masks, shifts and macros to parse the device range capability */
49 #define MMIO_RANGE_LD_MASK 0xff000000
50 #define MMIO_RANGE_FD_MASK 0x00ff0000
51 #define MMIO_RANGE_BUS_MASK 0x0000ff00
52 #define MMIO_RANGE_LD_SHIFT 24
53 #define MMIO_RANGE_FD_SHIFT 16
54 #define MMIO_RANGE_BUS_SHIFT 8
55 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
56 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
59
60 /* Flag masks for the AMD IOMMU exclusion range */
61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
62 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
63
64 /* Used offsets into the MMIO space */
65 #define MMIO_DEV_TABLE_OFFSET 0x0000
66 #define MMIO_CMD_BUF_OFFSET 0x0008
67 #define MMIO_EVT_BUF_OFFSET 0x0010
68 #define MMIO_CONTROL_OFFSET 0x0018
69 #define MMIO_EXCL_BASE_OFFSET 0x0020
70 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
71 #define MMIO_CMD_HEAD_OFFSET 0x2000
72 #define MMIO_CMD_TAIL_OFFSET 0x2008
73 #define MMIO_EVT_HEAD_OFFSET 0x2010
74 #define MMIO_EVT_TAIL_OFFSET 0x2018
75 #define MMIO_STATUS_OFFSET 0x2020
76
77 /* MMIO status bits */
78 #define MMIO_STATUS_COM_WAIT_INT_MASK 0x04
79
80 /* event logging constants */
81 #define EVENT_ENTRY_SIZE 0x10
82 #define EVENT_TYPE_SHIFT 28
83 #define EVENT_TYPE_MASK 0xf
84 #define EVENT_TYPE_ILL_DEV 0x1
85 #define EVENT_TYPE_IO_FAULT 0x2
86 #define EVENT_TYPE_DEV_TAB_ERR 0x3
87 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
88 #define EVENT_TYPE_ILL_CMD 0x5
89 #define EVENT_TYPE_CMD_HARD_ERR 0x6
90 #define EVENT_TYPE_IOTLB_INV_TO 0x7
91 #define EVENT_TYPE_INV_DEV_REQ 0x8
92 #define EVENT_DEVID_MASK 0xffff
93 #define EVENT_DEVID_SHIFT 0
94 #define EVENT_DOMID_MASK 0xffff
95 #define EVENT_DOMID_SHIFT 0
96 #define EVENT_FLAGS_MASK 0xfff
97 #define EVENT_FLAGS_SHIFT 0x10
98
99 /* feature control bits */
100 #define CONTROL_IOMMU_EN 0x00ULL
101 #define CONTROL_HT_TUN_EN 0x01ULL
102 #define CONTROL_EVT_LOG_EN 0x02ULL
103 #define CONTROL_EVT_INT_EN 0x03ULL
104 #define CONTROL_COMWAIT_EN 0x04ULL
105 #define CONTROL_PASSPW_EN 0x08ULL
106 #define CONTROL_RESPASSPW_EN 0x09ULL
107 #define CONTROL_COHERENT_EN 0x0aULL
108 #define CONTROL_ISOC_EN 0x0bULL
109 #define CONTROL_CMDBUF_EN 0x0cULL
110 #define CONTROL_PPFLOG_EN 0x0dULL
111 #define CONTROL_PPFINT_EN 0x0eULL
112
113 /* command specific defines */
114 #define CMD_COMPL_WAIT 0x01
115 #define CMD_INV_DEV_ENTRY 0x02
116 #define CMD_INV_IOMMU_PAGES 0x03
117
118 #define CMD_COMPL_WAIT_STORE_MASK 0x01
119 #define CMD_COMPL_WAIT_INT_MASK 0x02
120 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
121 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
122
123 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
124
125 /* macros and definitions for device table entries */
126 #define DEV_ENTRY_VALID 0x00
127 #define DEV_ENTRY_TRANSLATION 0x01
128 #define DEV_ENTRY_IR 0x3d
129 #define DEV_ENTRY_IW 0x3e
130 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
131 #define DEV_ENTRY_EX 0x67
132 #define DEV_ENTRY_SYSMGT1 0x68
133 #define DEV_ENTRY_SYSMGT2 0x69
134 #define DEV_ENTRY_INIT_PASS 0xb8
135 #define DEV_ENTRY_EINT_PASS 0xb9
136 #define DEV_ENTRY_NMI_PASS 0xba
137 #define DEV_ENTRY_LINT0_PASS 0xbe
138 #define DEV_ENTRY_LINT1_PASS 0xbf
139 #define DEV_ENTRY_MODE_MASK 0x07
140 #define DEV_ENTRY_MODE_SHIFT 0x09
141
142 /* constants to configure the command buffer */
143 #define CMD_BUFFER_SIZE 8192
144 #define CMD_BUFFER_UNINITIALIZED 1
145 #define CMD_BUFFER_ENTRIES 512
146 #define MMIO_CMD_SIZE_SHIFT 56
147 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
148
149 /* constants for event buffer handling */
150 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
151 #define EVT_LEN_MASK (0x9ULL << 56)
152
153 #define PAGE_MODE_NONE 0x00
154 #define PAGE_MODE_1_LEVEL 0x01
155 #define PAGE_MODE_2_LEVEL 0x02
156 #define PAGE_MODE_3_LEVEL 0x03
157 #define PAGE_MODE_4_LEVEL 0x04
158 #define PAGE_MODE_5_LEVEL 0x05
159 #define PAGE_MODE_6_LEVEL 0x06
160
161 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
162 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
163 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
164 (0xffffffffffffffffULL))
165 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
166 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
167 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
168 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
169 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
170
171 #define PM_MAP_4k 0
172 #define PM_ADDR_MASK 0x000ffffffffff000ULL
173 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
174 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
175 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
176
177 /*
178 * Returns the page table level to use for a given page size
179 * Pagesize is expected to be a power-of-two
180 */
181 #define PAGE_SIZE_LEVEL(pagesize) \
182 ((__ffs(pagesize) - 12) / 9)
183 /*
184 * Returns the number of ptes to use for a given page size
185 * Pagesize is expected to be a power-of-two
186 */
187 #define PAGE_SIZE_PTE_COUNT(pagesize) \
188 (1ULL << ((__ffs(pagesize) - 12) % 9))
189
190 /*
191 * Aligns a given io-virtual address to a given page size
192 * Pagesize is expected to be a power-of-two
193 */
194 #define PAGE_SIZE_ALIGN(address, pagesize) \
195 ((address) & ~((pagesize) - 1))
196 /*
197 * Creates an IOMMU PTE for an address an a given pagesize
198 * The PTE has no permission bits set
199 * Pagesize is expected to be a power-of-two larger than 4096
200 */
201 #define PAGE_SIZE_PTE(address, pagesize) \
202 (((address) | ((pagesize) - 1)) & \
203 (~(pagesize >> 1)) & PM_ADDR_MASK)
204
205 /*
206 * Takes a PTE value with mode=0x07 and returns the page size it maps
207 */
208 #define PTE_PAGE_SIZE(pte) \
209 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
210
211 #define IOMMU_PTE_P (1ULL << 0)
212 #define IOMMU_PTE_TV (1ULL << 1)
213 #define IOMMU_PTE_U (1ULL << 59)
214 #define IOMMU_PTE_FC (1ULL << 60)
215 #define IOMMU_PTE_IR (1ULL << 61)
216 #define IOMMU_PTE_IW (1ULL << 62)
217
218 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
219 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
220 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
221 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
222
223 #define IOMMU_PROT_MASK 0x03
224 #define IOMMU_PROT_IR 0x01
225 #define IOMMU_PROT_IW 0x02
226
227 /* IOMMU capabilities */
228 #define IOMMU_CAP_IOTLB 24
229 #define IOMMU_CAP_NPCACHE 26
230
231 #define MAX_DOMAIN_ID 65536
232
233 /* FIXME: move this macro to <linux/pci.h> */
234 #define PCI_BUS(x) (((x) >> 8) & 0xff)
235
236 /* Protection domain flags */
237 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
238 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
239 domain for an IOMMU */
240 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
241 translation */
242
243 extern bool amd_iommu_dump;
244 #define DUMP_printk(format, arg...) \
245 do { \
246 if (amd_iommu_dump) \
247 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
248 } while(0);
249
250 /* global flag if IOMMUs cache non-present entries */
251 extern bool amd_iommu_np_cache;
252
253 /*
254 * Make iterating over all IOMMUs easier
255 */
256 #define for_each_iommu(iommu) \
257 list_for_each_entry((iommu), &amd_iommu_list, list)
258 #define for_each_iommu_safe(iommu, next) \
259 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
260
261 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */
262 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
263 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
264 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
265 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
266 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
267
268 /*
269 * This structure contains generic data for IOMMU protection domains
270 * independent of their use.
271 */
272 struct protection_domain {
273 struct list_head list; /* for list of all protection domains */
274 struct list_head dev_list; /* List of all devices in this domain */
275 spinlock_t lock; /* mostly used to lock the page table*/
276 struct mutex api_lock; /* protect page tables in the iommu-api path */
277 u16 id; /* the domain id written to the device table */
278 int mode; /* paging mode (0-6 levels) */
279 u64 *pt_root; /* page table root pointer */
280 unsigned long flags; /* flags to find out type of domain */
281 bool updated; /* complete domain flush required */
282 unsigned dev_cnt; /* devices assigned to this domain */
283 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
284 void *priv; /* private data */
285
286 };
287
288 /*
289 * This struct contains device specific data for the IOMMU
290 */
291 struct iommu_dev_data {
292 struct list_head list; /* For domain->dev_list */
293 struct device *dev; /* Device this data belong to */
294 struct device *alias; /* The Alias Device */
295 struct protection_domain *domain; /* Domain the device is bound to */
296 atomic_t bind; /* Domain attach reverent count */
297 };
298
299 /*
300 * For dynamic growth the aperture size is split into ranges of 128MB of
301 * DMA address space each. This struct represents one such range.
302 */
303 struct aperture_range {
304
305 /* address allocation bitmap */
306 unsigned long *bitmap;
307
308 /*
309 * Array of PTE pages for the aperture. In this array we save all the
310 * leaf pages of the domain page table used for the aperture. This way
311 * we don't need to walk the page table to find a specific PTE. We can
312 * just calculate its address in constant time.
313 */
314 u64 *pte_pages[64];
315
316 unsigned long offset;
317 };
318
319 /*
320 * Data container for a dma_ops specific protection domain
321 */
322 struct dma_ops_domain {
323 struct list_head list;
324
325 /* generic protection domain information */
326 struct protection_domain domain;
327
328 /* size of the aperture for the mappings */
329 unsigned long aperture_size;
330
331 /* address we start to search for free addresses */
332 unsigned long next_address;
333
334 /* address space relevant data */
335 struct aperture_range *aperture[APERTURE_MAX_RANGES];
336
337 /* This will be set to true when TLB needs to be flushed */
338 bool need_flush;
339
340 /*
341 * if this is a preallocated domain, keep the device for which it was
342 * preallocated in this variable
343 */
344 u16 target_dev;
345 };
346
347 /*
348 * Structure where we save information about one hardware AMD IOMMU in the
349 * system.
350 */
351 struct amd_iommu {
352 struct list_head list;
353
354 /* Index within the IOMMU array */
355 int index;
356
357 /* locks the accesses to the hardware */
358 spinlock_t lock;
359
360 /* Pointer to PCI device of this IOMMU */
361 struct pci_dev *dev;
362
363 /* physical address of MMIO space */
364 u64 mmio_phys;
365 /* virtual address of MMIO space */
366 u8 *mmio_base;
367
368 /* capabilities of that IOMMU read from ACPI */
369 u32 cap;
370
371 /* flags read from acpi table */
372 u8 acpi_flags;
373
374 /*
375 * Capability pointer. There could be more than one IOMMU per PCI
376 * device function if there are more than one AMD IOMMU capability
377 * pointers.
378 */
379 u16 cap_ptr;
380
381 /* pci domain of this IOMMU */
382 u16 pci_seg;
383
384 /* first device this IOMMU handles. read from PCI */
385 u16 first_device;
386 /* last device this IOMMU handles. read from PCI */
387 u16 last_device;
388
389 /* start of exclusion range of that IOMMU */
390 u64 exclusion_start;
391 /* length of exclusion range of that IOMMU */
392 u64 exclusion_length;
393
394 /* command buffer virtual address */
395 u8 *cmd_buf;
396 /* size of command buffer */
397 u32 cmd_buf_size;
398
399 /* size of event buffer */
400 u32 evt_buf_size;
401 /* event buffer virtual address */
402 u8 *evt_buf;
403 /* MSI number for event interrupt */
404 u16 evt_msi_num;
405
406 /* true if interrupts for this IOMMU are already enabled */
407 bool int_enabled;
408
409 /* if one, we need to send a completion wait command */
410 bool need_sync;
411
412 /* becomes true if a command buffer reset is running */
413 bool reset_in_progress;
414
415 /* default dma_ops domain for that IOMMU */
416 struct dma_ops_domain *default_dom;
417
418 /*
419 * We can't rely on the BIOS to restore all values on reinit, so we
420 * need to stash them
421 */
422
423 /* The iommu BAR */
424 u32 stored_addr_lo;
425 u32 stored_addr_hi;
426
427 /*
428 * Each iommu has 6 l1s, each of which is documented as having 0x12
429 * registers
430 */
431 u32 stored_l1[6][0x12];
432
433 /* The l2 indirect registers */
434 u32 stored_l2[0x83];
435 };
436
437 /*
438 * List with all IOMMUs in the system. This list is not locked because it is
439 * only written and read at driver initialization or suspend time
440 */
441 extern struct list_head amd_iommu_list;
442
443 /*
444 * Array with pointers to each IOMMU struct
445 * The indices are referenced in the protection domains
446 */
447 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
448
449 /* Number of IOMMUs present in the system */
450 extern int amd_iommus_present;
451
452 /*
453 * Declarations for the global list of all protection domains
454 */
455 extern spinlock_t amd_iommu_pd_lock;
456 extern struct list_head amd_iommu_pd_list;
457
458 /*
459 * Structure defining one entry in the device table
460 */
461 struct dev_table_entry {
462 u32 data[8];
463 };
464
465 /*
466 * One entry for unity mappings parsed out of the ACPI table.
467 */
468 struct unity_map_entry {
469 struct list_head list;
470
471 /* starting device id this entry is used for (including) */
472 u16 devid_start;
473 /* end device id this entry is used for (including) */
474 u16 devid_end;
475
476 /* start address to unity map (including) */
477 u64 address_start;
478 /* end address to unity map (including) */
479 u64 address_end;
480
481 /* required protection */
482 int prot;
483 };
484
485 /*
486 * List of all unity mappings. It is not locked because as runtime it is only
487 * read. It is created at ACPI table parsing time.
488 */
489 extern struct list_head amd_iommu_unity_map;
490
491 /*
492 * Data structures for device handling
493 */
494
495 /*
496 * Device table used by hardware. Read and write accesses by software are
497 * locked with the amd_iommu_pd_table lock.
498 */
499 extern struct dev_table_entry *amd_iommu_dev_table;
500
501 /*
502 * Alias table to find requestor ids to device ids. Not locked because only
503 * read on runtime.
504 */
505 extern u16 *amd_iommu_alias_table;
506
507 /*
508 * Reverse lookup table to find the IOMMU which translates a specific device.
509 */
510 extern struct amd_iommu **amd_iommu_rlookup_table;
511
512 /* size of the dma_ops aperture as power of 2 */
513 extern unsigned amd_iommu_aperture_order;
514
515 /* largest PCI device id we expect translation requests for */
516 extern u16 amd_iommu_last_bdf;
517
518 /* allocation bitmap for domain ids */
519 extern unsigned long *amd_iommu_pd_alloc_bitmap;
520
521 /*
522 * If true, the addresses will be flushed on unmap time, not when
523 * they are reused
524 */
525 extern bool amd_iommu_unmap_flush;
526
527 /* takes bus and device/function and returns the device id
528 * FIXME: should that be in generic PCI code? */
calc_devid(u8 bus,u8 devfn)529 static inline u16 calc_devid(u8 bus, u8 devfn)
530 {
531 return (((u16)bus) << 8) | devfn;
532 }
533
534 #ifdef CONFIG_AMD_IOMMU_STATS
535
536 struct __iommu_counter {
537 char *name;
538 struct dentry *dent;
539 u64 value;
540 };
541
542 #define DECLARE_STATS_COUNTER(nm) \
543 static struct __iommu_counter nm = { \
544 .name = #nm, \
545 }
546
547 #define INC_STATS_COUNTER(name) name.value += 1
548 #define ADD_STATS_COUNTER(name, x) name.value += (x)
549 #define SUB_STATS_COUNTER(name, x) name.value -= (x)
550
551 #else /* CONFIG_AMD_IOMMU_STATS */
552
553 #define DECLARE_STATS_COUNTER(name)
554 #define INC_STATS_COUNTER(name)
555 #define ADD_STATS_COUNTER(name, x)
556 #define SUB_STATS_COUNTER(name, x)
557
558 #endif /* CONFIG_AMD_IOMMU_STATS */
559
560 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
561