1 /* drivers/atm/firestream.h - FireStream 155 (MB86697) and 2 * FireStream 50 (MB86695) device driver 3 */ 4 5 /* Written & (C) 2000 by R.E.Wolff@BitWizard.nl 6 * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA 7 * and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd 8 */ 9 10 /* 11 This program is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 2 of the License, or 14 (at your option) any later version. 15 16 This program is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software 23 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24 25 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian 26 system and in the file COPYING in the Linux kernel source. 27 */ 28 29 30 /*********************************************************************** 31 * first the defines for the chip. * 32 ***********************************************************************/ 33 34 35 /********************* General chip parameters. ************************/ 36 37 #define FS_NR_FREE_POOLS 8 38 #define FS_NR_RX_QUEUES 4 39 40 41 /********************* queues and queue access macros ******************/ 42 43 44 /* A queue entry. */ 45 struct FS_QENTRY { 46 u32 cmd; 47 u32 p0, p1, p2; 48 }; 49 50 51 /* A freepool entry. */ 52 struct FS_BPENTRY { 53 u32 flags; 54 u32 next; 55 u32 bsa; 56 u32 aal_bufsize; 57 58 /* The hardware doesn't look at this, but we need the SKB somewhere... */ 59 struct sk_buff *skb; 60 struct freepool *fp; 61 struct fs_dev *dev; 62 }; 63 64 65 #define STATUS_CODE(qe) ((qe->cmd >> 22) & 0x3f) 66 67 68 /* OFFSETS against the base of a QUEUE... */ 69 #define QSA 0x00 70 #define QEA 0x04 71 #define QRP 0x08 72 #define QWP 0x0c 73 #define QCNF 0x10 /* Only for Release queues! */ 74 /* Not for the transmit pending queue. */ 75 76 77 /* OFFSETS against the base of a FREE POOL... */ 78 #define FPCNF 0x00 79 #define FPSA 0x04 80 #define FPEA 0x08 81 #define FPCNT 0x0c 82 #define FPCTU 0x10 83 84 #define Q_SA(b) (b + QSA ) 85 #define Q_EA(b) (b + QEA ) 86 #define Q_RP(b) (b + QRP ) 87 #define Q_WP(b) (b + QWP ) 88 #define Q_CNF(b) (b + QCNF) 89 90 #define FP_CNF(b) (b + FPCNF) 91 #define FP_SA(b) (b + FPSA) 92 #define FP_EA(b) (b + FPEA) 93 #define FP_CNT(b) (b + FPCNT) 94 #define FP_CTU(b) (b + FPCTU) 95 96 /* bits in a queue register. */ 97 #define Q_FULL 0x1 98 #define Q_EMPTY 0x2 99 #define Q_INCWRAP 0x4 100 #define Q_ADDR_MASK 0xfffffff0 101 102 /* bits in a FreePool config register */ 103 #define RBFP_RBS (0x1 << 16) 104 #define RBFP_RBSVAL (0x1 << 15) 105 #define RBFP_CME (0x1 << 12) 106 #define RBFP_DLP (0x1 << 11) 107 #define RBFP_BFPWT (0x1 << 0) 108 109 110 111 112 /* FireStream commands. */ 113 #define QE_CMD_NULL (0x00 << 22) 114 #define QE_CMD_REG_RD (0x01 << 22) 115 #define QE_CMD_REG_RDM (0x02 << 22) 116 #define QE_CMD_REG_WR (0x03 << 22) 117 #define QE_CMD_REG_WRM (0x04 << 22) 118 #define QE_CMD_CONFIG_TX (0x05 << 22) 119 #define QE_CMD_CONFIG_RX (0x06 << 22) 120 #define QE_CMD_PRP_RD (0x07 << 22) 121 #define QE_CMD_PRP_RDM (0x2a << 22) 122 #define QE_CMD_PRP_WR (0x09 << 22) 123 #define QE_CMD_PRP_WRM (0x2b << 22) 124 #define QE_CMD_RX_EN (0x0a << 22) 125 #define QE_CMD_RX_PURGE (0x0b << 22) 126 #define QE_CMD_RX_PURGE_INH (0x0c << 22) 127 #define QE_CMD_TX_EN (0x0d << 22) 128 #define QE_CMD_TX_PURGE (0x0e << 22) 129 #define QE_CMD_TX_PURGE_INH (0x0f << 22) 130 #define QE_CMD_RST_CG (0x10 << 22) 131 #define QE_CMD_SET_CG (0x11 << 22) 132 #define QE_CMD_RST_CLP (0x12 << 22) 133 #define QE_CMD_SET_CLP (0x13 << 22) 134 #define QE_CMD_OVERRIDE (0x14 << 22) 135 #define QE_CMD_ADD_BFP (0x15 << 22) 136 #define QE_CMD_DUMP_TX (0x16 << 22) 137 #define QE_CMD_DUMP_RX (0x17 << 22) 138 #define QE_CMD_LRAM_RD (0x18 << 22) 139 #define QE_CMD_LRAM_RDM (0x28 << 22) 140 #define QE_CMD_LRAM_WR (0x19 << 22) 141 #define QE_CMD_LRAM_WRM (0x29 << 22) 142 #define QE_CMD_LRAM_BSET (0x1a << 22) 143 #define QE_CMD_LRAM_BCLR (0x1b << 22) 144 #define QE_CMD_CONFIG_SEGM (0x1c << 22) 145 #define QE_CMD_READ_SEGM (0x1d << 22) 146 #define QE_CMD_CONFIG_ROUT (0x1e << 22) 147 #define QE_CMD_READ_ROUT (0x1f << 22) 148 #define QE_CMD_CONFIG_TM (0x20 << 22) 149 #define QE_CMD_READ_TM (0x21 << 22) 150 #define QE_CMD_CONFIG_TXBM (0x22 << 22) 151 #define QE_CMD_READ_TXBM (0x23 << 22) 152 #define QE_CMD_CONFIG_RXBM (0x24 << 22) 153 #define QE_CMD_READ_RXBM (0x25 << 22) 154 #define QE_CMD_CONFIG_REAS (0x26 << 22) 155 #define QE_CMD_READ_REAS (0x27 << 22) 156 157 #define QE_TRANSMIT_DE (0x0 << 30) 158 #define QE_CMD_LINKED (0x1 << 30) 159 #define QE_CMD_IMM (0x2 << 30) 160 #define QE_CMD_IMM_INQ (0x3 << 30) 161 162 #define TD_EPI (0x1 << 27) 163 #define TD_COMMAND (0x1 << 28) 164 165 #define TD_DATA (0x0 << 29) 166 #define TD_RM_CELL (0x1 << 29) 167 #define TD_OAM_CELL (0x2 << 29) 168 #define TD_OAM_CELL_SEGMENT (0x3 << 29) 169 170 #define TD_BPI (0x1 << 20) 171 172 #define FP_FLAGS_EPI (0x1 << 27) 173 174 175 #define TX_PQ(i) (0x00 + (i) * 0x10) 176 #define TXB_RQ (0x20) 177 #define ST_Q (0x48) 178 #define RXB_FP(i) (0x90 + (i) * 0x14) 179 #define RXB_RQ(i) (0x134 + (i) * 0x14) 180 181 182 #define TXQ_HP 0 183 #define TXQ_LP 1 184 185 /* Phew. You don't want to know how many revisions these simple queue 186 * address macros went through before I got them nice and compact as 187 * they are now. -- REW 188 */ 189 190 191 /* And now for something completely different: 192 * The rest of the registers... */ 193 194 195 #define CMDR0 0x34 196 #define CMDR1 0x38 197 #define CMDR2 0x3c 198 #define CMDR3 0x40 199 200 201 #define SARMODE0 0x5c 202 203 #define SARMODE0_TXVCS_0 (0x0 << 0) 204 #define SARMODE0_TXVCS_1k (0x1 << 0) 205 #define SARMODE0_TXVCS_2k (0x2 << 0) 206 #define SARMODE0_TXVCS_4k (0x3 << 0) 207 #define SARMODE0_TXVCS_8k (0x4 << 0) 208 #define SARMODE0_TXVCS_16k (0x5 << 0) 209 #define SARMODE0_TXVCS_32k (0x6 << 0) 210 #define SARMODE0_TXVCS_64k (0x7 << 0) 211 #define SARMODE0_TXVCS_32 (0x8 << 0) 212 213 #define SARMODE0_ABRVCS_0 (0x0 << 4) 214 #define SARMODE0_ABRVCS_512 (0x1 << 4) 215 #define SARMODE0_ABRVCS_1k (0x2 << 4) 216 #define SARMODE0_ABRVCS_2k (0x3 << 4) 217 #define SARMODE0_ABRVCS_4k (0x4 << 4) 218 #define SARMODE0_ABRVCS_8k (0x5 << 4) 219 #define SARMODE0_ABRVCS_16k (0x6 << 4) 220 #define SARMODE0_ABRVCS_32k (0x7 << 4) 221 #define SARMODE0_ABRVCS_32 (0x9 << 4) /* The others are "8", this one really has to 222 be 9. Tell me you don't believe me. -- REW */ 223 224 #define SARMODE0_RXVCS_0 (0x0 << 8) 225 #define SARMODE0_RXVCS_1k (0x1 << 8) 226 #define SARMODE0_RXVCS_2k (0x2 << 8) 227 #define SARMODE0_RXVCS_4k (0x3 << 8) 228 #define SARMODE0_RXVCS_8k (0x4 << 8) 229 #define SARMODE0_RXVCS_16k (0x5 << 8) 230 #define SARMODE0_RXVCS_32k (0x6 << 8) 231 #define SARMODE0_RXVCS_64k (0x7 << 8) 232 #define SARMODE0_RXVCS_32 (0x8 << 8) 233 234 #define SARMODE0_CALSUP_1 (0x0 << 12) 235 #define SARMODE0_CALSUP_2 (0x1 << 12) 236 #define SARMODE0_CALSUP_3 (0x2 << 12) 237 #define SARMODE0_CALSUP_4 (0x3 << 12) 238 239 #define SARMODE0_PRPWT_FS50_0 (0x0 << 14) 240 #define SARMODE0_PRPWT_FS50_2 (0x1 << 14) 241 #define SARMODE0_PRPWT_FS50_5 (0x2 << 14) 242 #define SARMODE0_PRPWT_FS50_11 (0x3 << 14) 243 244 #define SARMODE0_PRPWT_FS155_0 (0x0 << 14) 245 #define SARMODE0_PRPWT_FS155_1 (0x1 << 14) 246 #define SARMODE0_PRPWT_FS155_2 (0x2 << 14) 247 #define SARMODE0_PRPWT_FS155_3 (0x3 << 14) 248 249 #define SARMODE0_SRTS0 (0x1 << 23) 250 #define SARMODE0_SRTS1 (0x1 << 24) 251 252 #define SARMODE0_RUN (0x1 << 25) 253 254 #define SARMODE0_UNLOCK (0x1 << 26) 255 #define SARMODE0_CWRE (0x1 << 27) 256 257 258 #define SARMODE0_INTMODE_READCLEAR (0x0 << 28) 259 #define SARMODE0_INTMODE_READNOCLEAR (0x1 << 28) 260 #define SARMODE0_INTMODE_READNOCLEARINHIBIT (0x2 << 28) 261 #define SARMODE0_INTMODE_READCLEARINHIBIT (0x3 << 28) /* Tell me you don't believe me. */ 262 263 #define SARMODE0_GINT (0x1 << 30) 264 #define SARMODE0_SHADEN (0x1 << 31) 265 266 267 #define SARMODE1 0x60 268 269 270 #define SARMODE1_TRTL_SHIFT 0 /* Program to 0 */ 271 #define SARMODE1_RRTL_SHIFT 4 /* Program to 0 */ 272 273 #define SARMODE1_TAGM (0x1 << 8) /* Program to 0 */ 274 275 #define SARMODE1_HECM0 (0x1 << 9) 276 #define SARMODE1_HECM1 (0x1 << 10) 277 #define SARMODE1_HECM2 (0x1 << 11) 278 279 #define SARMODE1_GFCE (0x1 << 14) 280 #define SARMODE1_GFCR (0x1 << 15) 281 #define SARMODE1_PMS (0x1 << 18) 282 #define SARMODE1_GPRI (0x1 << 19) 283 #define SARMODE1_GPAS (0x1 << 20) 284 #define SARMODE1_GVAS (0x1 << 21) 285 #define SARMODE1_GNAM (0x1 << 22) 286 #define SARMODE1_GPLEN (0x1 << 23) 287 #define SARMODE1_DUMPE (0x1 << 24) 288 #define SARMODE1_OAMCRC (0x1 << 25) 289 #define SARMODE1_DCOAM (0x1 << 26) 290 #define SARMODE1_DCRM (0x1 << 27) 291 #define SARMODE1_TSTLP (0x1 << 28) 292 #define SARMODE1_DEFHEC (0x1 << 29) 293 294 295 #define ISR 0x64 296 #define IUSR 0x68 297 #define IMR 0x6c 298 299 #define ISR_LPCO (0x1 << 0) 300 #define ISR_DPCO (0x1 << 1) 301 #define ISR_RBRQ0_W (0x1 << 2) 302 #define ISR_RBRQ1_W (0x1 << 3) 303 #define ISR_RBRQ2_W (0x1 << 4) 304 #define ISR_RBRQ3_W (0x1 << 5) 305 #define ISR_RBRQ0_NF (0x1 << 6) 306 #define ISR_RBRQ1_NF (0x1 << 7) 307 #define ISR_RBRQ2_NF (0x1 << 8) 308 #define ISR_RBRQ3_NF (0x1 << 9) 309 #define ISR_BFP_SC (0x1 << 10) 310 #define ISR_INIT (0x1 << 11) 311 #define ISR_INIT_ERR (0x1 << 12) /* Documented as "reserved" */ 312 #define ISR_USCEO (0x1 << 13) 313 #define ISR_UPEC0 (0x1 << 14) 314 #define ISR_VPFCO (0x1 << 15) 315 #define ISR_CRCCO (0x1 << 16) 316 #define ISR_HECO (0x1 << 17) 317 #define ISR_TBRQ_W (0x1 << 18) 318 #define ISR_TBRQ_NF (0x1 << 19) 319 #define ISR_CTPQ_E (0x1 << 20) 320 #define ISR_GFC_C0 (0x1 << 21) 321 #define ISR_PCI_FTL (0x1 << 22) 322 #define ISR_CSQ_W (0x1 << 23) 323 #define ISR_CSQ_NF (0x1 << 24) 324 #define ISR_EXT_INT (0x1 << 25) 325 #define ISR_RXDMA_S (0x1 << 26) 326 327 328 #define TMCONF 0x78 329 /* Bits? */ 330 331 332 #define CALPRESCALE 0x7c 333 /* Bits? */ 334 335 #define CELLOSCONF 0x84 336 #define CELLOSCONF_COTS (0x1 << 28) 337 #define CELLOSCONF_CEN (0x1 << 27) 338 #define CELLOSCONF_SC8 (0x3 << 24) 339 #define CELLOSCONF_SC4 (0x2 << 24) 340 #define CELLOSCONF_SC2 (0x1 << 24) 341 #define CELLOSCONF_SC1 (0x0 << 24) 342 343 #define CELLOSCONF_COBS (0x1 << 16) 344 #define CELLOSCONF_COPK (0x1 << 8) 345 #define CELLOSCONF_COST (0x1 << 0) 346 /* Bits? */ 347 348 #define RAS0 0x1bc 349 #define RAS0_DCD_XHLT (0x1 << 31) 350 351 #define RAS0_VPSEL (0x1 << 16) 352 #define RAS0_VCSEL (0x1 << 0) 353 354 #define RAS1 0x1c0 355 #define RAS1_UTREG (0x1 << 5) 356 357 358 #define DMAMR 0x1cc 359 #define DMAMR_TX_MODE_FULL (0x0 << 0) 360 #define DMAMR_TX_MODE_PART (0x1 << 0) 361 #define DMAMR_TX_MODE_NONE (0x2 << 0) /* And 3 */ 362 363 364 365 #define RAS2 0x280 366 367 #define RAS2_NNI (0x1 << 0) 368 #define RAS2_USEL (0x1 << 1) 369 #define RAS2_UBS (0x1 << 2) 370 371 372 373 struct fs_transmit_config { 374 u32 flags; 375 u32 atm_hdr; 376 u32 TMC[4]; 377 u32 spec; 378 u32 rtag[3]; 379 }; 380 381 #define TC_FLAGS_AAL5 (0x0 << 29) 382 #define TC_FLAGS_TRANSPARENT_PAYLOAD (0x1 << 29) 383 #define TC_FLAGS_TRANSPARENT_CELL (0x2 << 29) 384 #define TC_FLAGS_STREAMING (0x1 << 28) 385 #define TC_FLAGS_PACKET (0x0) 386 #define TC_FLAGS_TYPE_ABR (0x0 << 22) 387 #define TC_FLAGS_TYPE_CBR (0x1 << 22) 388 #define TC_FLAGS_TYPE_VBR (0x2 << 22) 389 #define TC_FLAGS_TYPE_UBR (0x3 << 22) 390 #define TC_FLAGS_CAL0 (0x0 << 20) 391 #define TC_FLAGS_CAL1 (0x1 << 20) 392 #define TC_FLAGS_CAL2 (0x2 << 20) 393 #define TC_FLAGS_CAL3 (0x3 << 20) 394 395 396 #define RC_FLAGS_NAM (0x1 << 13) 397 #define RC_FLAGS_RXBM_PSB (0x0 << 14) 398 #define RC_FLAGS_RXBM_CIF (0x1 << 14) 399 #define RC_FLAGS_RXBM_PMB (0x2 << 14) 400 #define RC_FLAGS_RXBM_STR (0x4 << 14) 401 #define RC_FLAGS_RXBM_SAF (0x6 << 14) 402 #define RC_FLAGS_RXBM_POS (0x6 << 14) 403 #define RC_FLAGS_BFPS (0x1 << 17) 404 405 #define RC_FLAGS_BFPS_BFP (0x1 << 17) 406 407 #define RC_FLAGS_BFPS_BFP0 (0x0 << 17) 408 #define RC_FLAGS_BFPS_BFP1 (0x1 << 17) 409 #define RC_FLAGS_BFPS_BFP2 (0x2 << 17) 410 #define RC_FLAGS_BFPS_BFP3 (0x3 << 17) 411 #define RC_FLAGS_BFPS_BFP4 (0x4 << 17) 412 #define RC_FLAGS_BFPS_BFP5 (0x5 << 17) 413 #define RC_FLAGS_BFPS_BFP6 (0x6 << 17) 414 #define RC_FLAGS_BFPS_BFP7 (0x7 << 17) 415 #define RC_FLAGS_BFPS_BFP01 (0x8 << 17) 416 #define RC_FLAGS_BFPS_BFP23 (0x9 << 17) 417 #define RC_FLAGS_BFPS_BFP45 (0xa << 17) 418 #define RC_FLAGS_BFPS_BFP67 (0xb << 17) 419 #define RC_FLAGS_BFPS_BFP07 (0xc << 17) 420 #define RC_FLAGS_BFPS_BFP27 (0xd << 17) 421 #define RC_FLAGS_BFPS_BFP47 (0xe << 17) 422 423 #define RC_FLAGS_BFPS (0x1 << 17) 424 #define RC_FLAGS_BFPP (0x1 << 21) 425 #define RC_FLAGS_TEVC (0x1 << 22) 426 #define RC_FLAGS_TEP (0x1 << 23) 427 #define RC_FLAGS_AAL5 (0x0 << 24) 428 #define RC_FLAGS_TRANSP (0x1 << 24) 429 #define RC_FLAGS_TRANSC (0x2 << 24) 430 #define RC_FLAGS_ML (0x1 << 27) 431 #define RC_FLAGS_TRBRM (0x1 << 28) 432 #define RC_FLAGS_PRI (0x1 << 29) 433 #define RC_FLAGS_HOAM (0x1 << 30) 434 #define RC_FLAGS_CRC10 (0x1 << 31) 435 436 437 #define RAC 0x1c8 438 #define RAM 0x1c4 439 440 441 442 /************************************************************************ 443 * Then the datastructures that the DRIVER uses. * 444 ************************************************************************/ 445 446 #define TXQ_NENTRIES 32 447 #define RXRQ_NENTRIES 1024 448 449 450 struct fs_vcc { 451 int channo; 452 wait_queue_head_t close_wait; 453 struct sk_buff *last_skb; 454 }; 455 456 457 struct queue { 458 struct FS_QENTRY *sa, *ea; 459 int offset; 460 }; 461 462 struct freepool { 463 int offset; 464 int bufsize; 465 int nr_buffers; 466 int n; 467 }; 468 469 470 struct fs_dev { 471 struct fs_dev *next; /* other FS devices */ 472 int flags; 473 474 unsigned char irq; /* IRQ */ 475 struct pci_dev *pci_dev; /* PCI stuff */ 476 struct atm_dev *atm_dev; 477 struct timer_list timer; 478 479 unsigned long hw_base; /* mem base address */ 480 unsigned long base; /* Mapping of base address */ 481 int channo; 482 unsigned long channel_mask; 483 484 struct queue hp_txq, lp_txq, tx_relq, st_q; 485 struct freepool rx_fp[FS_NR_FREE_POOLS]; 486 struct queue rx_rq[FS_NR_RX_QUEUES]; 487 488 int nchannels; 489 struct atm_vcc **atm_vccs; 490 void *tx_inuse; 491 int ntxpckts; 492 }; 493 494 495 496 497 /* Number of channesl that the FS50 supports. */ 498 #define FS50_CHANNEL_BITS 5 499 #define FS50_NR_CHANNELS (1 << FS50_CHANNEL_BITS) 500 501 502 #define FS_DEV(atm_dev) ((struct fs_dev *) (atm_dev)->dev_data) 503 #define FS_VCC(atm_vcc) ((struct fs_vcc *) (atm_vcc)->dev_data) 504 505 506 #define FS_IS50 0x1 507 #define FS_IS155 0x2 508 509 #define IS_FS50(dev) (dev->flags & FS_IS50) 510 #define IS_FS155(dev) (dev->flags & FS_IS155) 511 512 /* Within limits this is user-configurable. */ 513 /* Note: Currently the sum (10 -> 1k channels) is hardcoded in the driver. */ 514 #define FS155_VPI_BITS 4 515 #define FS155_VCI_BITS 6 516 517 #define FS155_CHANNEL_BITS (FS155_VPI_BITS + FS155_VCI_BITS) 518 #define FS155_NR_CHANNELS (1 << FS155_CHANNEL_BITS) 519