1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_S390_PCI_CLP_H
3 #define _ASM_S390_PCI_CLP_H
4 
5 #include <asm/clp.h>
6 
7 /*
8  * Call Logical Processor - Command Codes
9  */
10 #define CLP_SLPC		0x0001
11 #define CLP_LIST_PCI		0x0002
12 #define CLP_QUERY_PCI_FN	0x0003
13 #define CLP_QUERY_PCI_FNGRP	0x0004
14 #define CLP_SET_PCI_FN		0x0005
15 
16 /* PCI function handle list entry */
17 struct clp_fh_list_entry {
18 	u16 device_id;
19 	u16 vendor_id;
20 	u32 config_state :  1;
21 	u32		 : 31;
22 	u32 fid;		/* PCI function id */
23 	u32 fh;			/* PCI function handle */
24 } __packed;
25 
26 #define CLP_RC_SETPCIFN_FH	0x0101	/* Invalid PCI fn handle */
27 #define CLP_RC_SETPCIFN_FHOP	0x0102	/* Fn handle not valid for op */
28 #define CLP_RC_SETPCIFN_DMAAS	0x0103	/* Invalid DMA addr space */
29 #define CLP_RC_SETPCIFN_RES	0x0104	/* Insufficient resources */
30 #define CLP_RC_SETPCIFN_ALRDY	0x0105	/* Fn already in requested state */
31 #define CLP_RC_SETPCIFN_ERR	0x0106	/* Fn in permanent error state */
32 #define CLP_RC_SETPCIFN_RECPND	0x0107	/* Error recovery pending */
33 #define CLP_RC_SETPCIFN_BUSY	0x0108	/* Fn busy */
34 #define CLP_RC_LISTPCI_BADRT	0x010a	/* Resume token not recognized */
35 #define CLP_RC_QUERYPCIFG_PFGID	0x010b	/* Unrecognized PFGID */
36 
37 /* request or response block header length */
38 #define LIST_PCI_HDR_LEN	32
39 
40 /* Number of function handles fitting in response block */
41 #define CLP_FH_LIST_NR_ENTRIES				\
42 	((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN)		\
43 		/ sizeof(struct clp_fh_list_entry))
44 
45 #define CLP_SET_ENABLE_PCI_FN	0	/* Yes, 0 enables it */
46 #define CLP_SET_DISABLE_PCI_FN	1	/* Yes, 1 disables it */
47 #define CLP_SET_ENABLE_MIO	2
48 #define CLP_SET_DISABLE_MIO	3
49 
50 #define CLP_UTIL_STR_LEN	64
51 #define CLP_PFIP_NR_SEGMENTS	4
52 
53 extern bool zpci_unique_uid;
54 
55 struct clp_rsp_slpc_pci {
56 	struct clp_rsp_hdr hdr;
57 	u32 reserved2[4];
58 	u32 lpif[8];
59 	u32 reserved3[4];
60 	u32 vwb		:  1;
61 	u32		:  1;
62 	u32 mio_wb	:  6;
63 	u32		: 24;
64 	u32 reserved5[3];
65 	u32 lpic[8];
66 } __packed;
67 
68 /* List PCI functions request */
69 struct clp_req_list_pci {
70 	struct clp_req_hdr hdr;
71 	u64 resume_token;
72 	u64 reserved2;
73 } __packed;
74 
75 /* List PCI functions response */
76 struct clp_rsp_list_pci {
77 	struct clp_rsp_hdr hdr;
78 	u64 resume_token;
79 	u32 reserved2;
80 	u16 max_fn;
81 	u8			: 7;
82 	u8 uid_checking		: 1;
83 	u8 entry_size;
84 	struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
85 } __packed;
86 
87 struct mio_info {
88 	u32 valid : 6;
89 	u32 : 26;
90 	u32 : 32;
91 	struct {
92 		u64 wb;
93 		u64 wt;
94 	} addr[PCI_STD_NUM_BARS];
95 	u32 reserved[6];
96 } __packed;
97 
98 /* Query PCI function request */
99 struct clp_req_query_pci {
100 	struct clp_req_hdr hdr;
101 	u32 fh;				/* function handle */
102 	u32 reserved2;
103 	u64 reserved3;
104 } __packed;
105 
106 /* Query PCI function response */
107 struct clp_rsp_query_pci {
108 	struct clp_rsp_hdr hdr;
109 	u16 vfn;			/* virtual fn number */
110 	u16			:  3;
111 	u16 rid_avail		:  1;
112 	u16 is_physfn		:  1;
113 	u16 reserved1		:  1;
114 	u16 mio_addr_avail	:  1;
115 	u16 util_str_avail	:  1;	/* utility string available? */
116 	u16 pfgid		:  8;	/* pci function group id */
117 	u32 fid;			/* pci function id */
118 	u8 bar_size[PCI_STD_NUM_BARS];
119 	u16 pchid;
120 	__le32 bar[PCI_STD_NUM_BARS];
121 	u8 pfip[CLP_PFIP_NR_SEGMENTS];	/* pci function internal path */
122 	u16			: 12;
123 	u16 port		:  4;
124 	u8 fmb_len;
125 	u8 pft;				/* pci function type */
126 	u64 sdma;			/* start dma as */
127 	u64 edma;			/* end dma as */
128 #define ZPCI_RID_MASK_DEVFN 0x00ff
129 	u16 rid;			/* BUS/DEVFN PCI address */
130 	u16 reserved0;
131 	u32 reserved[10];
132 	u32 uid;			/* user defined id */
133 	u8 util_str[CLP_UTIL_STR_LEN];	/* utility string */
134 	u32 reserved2[16];
135 	struct mio_info mio;
136 } __packed;
137 
138 /* Query PCI function group request */
139 struct clp_req_query_pci_grp {
140 	struct clp_req_hdr hdr;
141 	u32 reserved2		: 24;
142 	u32 pfgid		:  8;	/* function group id */
143 	u32 reserved3;
144 	u64 reserved4;
145 } __packed;
146 
147 /* Query PCI function group response */
148 struct clp_rsp_query_pci_grp {
149 	struct clp_rsp_hdr hdr;
150 	u16			:  4;
151 	u16 noi			: 12;	/* number of interrupts */
152 	u8 version;
153 	u8			:  6;
154 	u8 frame		:  1;
155 	u8 refresh		:  1;	/* TLB refresh mode */
156 	u16			:  3;
157 	u16 maxstbl		: 13;	/* Maximum store block size */
158 	u16 mui;
159 	u8 dtsm;			/* Supported DT mask */
160 	u8 reserved3;
161 	u16 maxfaal;
162 	u16			:  4;
163 	u16 dnoi		: 12;
164 	u16 maxcpu;
165 	u64 dasm;			/* dma address space mask */
166 	u64 msia;			/* MSI address */
167 	u64 reserved4;
168 	u64 reserved5;
169 } __packed;
170 
171 /* Set PCI function request */
172 struct clp_req_set_pci {
173 	struct clp_req_hdr hdr;
174 	u32 fh;				/* function handle */
175 	u16 reserved2;
176 	u8 oc;				/* operation controls */
177 	u8 ndas;			/* number of dma spaces */
178 	u32 reserved3;
179 	u32 gisa;			/* GISA designation */
180 } __packed;
181 
182 /* Set PCI function response */
183 struct clp_rsp_set_pci {
184 	struct clp_rsp_hdr hdr;
185 	u32 fh;				/* function handle */
186 	u32 reserved1;
187 	u64 reserved2;
188 	struct mio_info mio;
189 } __packed;
190 
191 /* Combined request/response block structures used by clp insn */
192 struct clp_req_rsp_slpc_pci {
193 	struct clp_req_slpc request;
194 	struct clp_rsp_slpc_pci response;
195 } __packed;
196 
197 struct clp_req_rsp_list_pci {
198 	struct clp_req_list_pci request;
199 	struct clp_rsp_list_pci response;
200 } __packed;
201 
202 struct clp_req_rsp_set_pci {
203 	struct clp_req_set_pci request;
204 	struct clp_rsp_set_pci response;
205 } __packed;
206 
207 struct clp_req_rsp_query_pci {
208 	struct clp_req_query_pci request;
209 	struct clp_rsp_query_pci response;
210 } __packed;
211 
212 struct clp_req_rsp_query_pci_grp {
213 	struct clp_req_query_pci_grp request;
214 	struct clp_rsp_query_pci_grp response;
215 } __packed;
216 
217 #endif
218