1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11
12 /*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
35
36 struct clk;
37 struct clk_hw;
38 struct clk_core;
39 struct dentry;
40
41 /**
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
44 *
45 * Should be initialized by calling clk_hw_init_rate_request().
46 *
47 * @rate: Requested clock rate. This field will be adjusted by
48 * clock drivers according to hardware capabilities.
49 * @min_rate: Minimum rate imposed by clk users.
50 * @max_rate: Maximum rate imposed by clk users.
51 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
52 * requested constraints.
53 * @best_parent_hw: The most appropriate parent clock that fulfills the
54 * requested constraints.
55 *
56 */
57 struct clk_rate_request {
58 unsigned long rate;
59 unsigned long min_rate;
60 unsigned long max_rate;
61 unsigned long best_parent_rate;
62 struct clk_hw *best_parent_hw;
63 };
64
65 void clk_hw_init_rate_request(const struct clk_hw *hw,
66 struct clk_rate_request *req,
67 unsigned long rate);
68 void clk_hw_forward_rate_request(const struct clk_hw *core,
69 const struct clk_rate_request *old_req,
70 const struct clk_hw *parent,
71 struct clk_rate_request *req,
72 unsigned long parent_rate);
73
74 /**
75 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
76 *
77 * @num: Numerator of the duty cycle ratio
78 * @den: Denominator of the duty cycle ratio
79 */
80 struct clk_duty {
81 unsigned int num;
82 unsigned int den;
83 };
84
85 /**
86 * struct clk_ops - Callback operations for hardware clocks; these are to
87 * be provided by the clock implementation, and will be called by drivers
88 * through the clk_* api.
89 *
90 * @prepare: Prepare the clock for enabling. This must not return until
91 * the clock is fully prepared, and it's safe to call clk_enable.
92 * This callback is intended to allow clock implementations to
93 * do any initialisation that may sleep. Called with
94 * prepare_lock held.
95 *
96 * @unprepare: Release the clock from its prepared state. This will typically
97 * undo any work done in the @prepare callback. Called with
98 * prepare_lock held.
99 *
100 * @is_prepared: Queries the hardware to determine if the clock is prepared.
101 * This function is allowed to sleep. Optional, if this op is not
102 * set then the prepare count will be used.
103 *
104 * @unprepare_unused: Unprepare the clock atomically. Only called from
105 * clk_disable_unused for prepare clocks with special needs.
106 * Called with prepare mutex held. This function may sleep.
107 *
108 * @enable: Enable the clock atomically. This must not return until the
109 * clock is generating a valid clock signal, usable by consumer
110 * devices. Called with enable_lock held. This function must not
111 * sleep.
112 *
113 * @disable: Disable the clock atomically. Called with enable_lock held.
114 * This function must not sleep.
115 *
116 * @is_enabled: Queries the hardware to determine if the clock is enabled.
117 * This function must not sleep. Optional, if this op is not
118 * set then the enable count will be used.
119 *
120 * @disable_unused: Disable the clock atomically. Only called from
121 * clk_disable_unused for gate clocks with special needs.
122 * Called with enable_lock held. This function must not
123 * sleep.
124 *
125 * @save_context: Save the context of the clock in prepration for poweroff.
126 *
127 * @restore_context: Restore the context of the clock after a restoration
128 * of power.
129 *
130 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
131 * parent rate is an input parameter. It is up to the caller to
132 * ensure that the prepare_mutex is held across this call. If the
133 * driver cannot figure out a rate for this clock, it must return
134 * 0. Returns the calculated rate. Optional, but recommended - if
135 * this op is not set then clock rate will be initialized to 0.
136 *
137 * @round_rate: Given a target rate as input, returns the closest rate actually
138 * supported by the clock. The parent rate is an input/output
139 * parameter.
140 *
141 * @determine_rate: Given a target rate as input, returns the closest rate
142 * actually supported by the clock, and optionally the parent clock
143 * that should be used to provide the clock rate.
144 *
145 * @set_parent: Change the input source of this clock; for clocks with multiple
146 * possible parents specify a new parent by passing in the index
147 * as a u8 corresponding to the parent in either the .parent_names
148 * or .parents arrays. This function in affect translates an
149 * array index into the value programmed into the hardware.
150 * Returns 0 on success, -EERROR otherwise.
151 *
152 * @get_parent: Queries the hardware to determine the parent of a clock. The
153 * return value is a u8 which specifies the index corresponding to
154 * the parent clock. This index can be applied to either the
155 * .parent_names or .parents arrays. In short, this function
156 * translates the parent value read from hardware into an array
157 * index. Currently only called when the clock is initialized by
158 * __clk_init. This callback is mandatory for clocks with
159 * multiple parents. It is optional (and unnecessary) for clocks
160 * with 0 or 1 parents.
161 *
162 * @set_rate: Change the rate of this clock. The requested rate is specified
163 * by the second argument, which should typically be the return
164 * of .round_rate call. The third argument gives the parent rate
165 * which is likely helpful for most .set_rate implementation.
166 * Returns 0 on success, -EERROR otherwise.
167 *
168 * @set_rate_and_parent: Change the rate and the parent of this clock. The
169 * requested rate is specified by the second argument, which
170 * should typically be the return of .round_rate call. The
171 * third argument gives the parent rate which is likely helpful
172 * for most .set_rate_and_parent implementation. The fourth
173 * argument gives the parent index. This callback is optional (and
174 * unnecessary) for clocks with 0 or 1 parents as well as
175 * for clocks that can tolerate switching the rate and the parent
176 * separately via calls to .set_parent and .set_rate.
177 * Returns 0 on success, -EERROR otherwise.
178 *
179 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
180 * is expressed in ppb (parts per billion). The parent accuracy is
181 * an input parameter.
182 * Returns the calculated accuracy. Optional - if this op is not
183 * set then clock accuracy will be initialized to parent accuracy
184 * or 0 (perfect clock) if clock has no parent.
185 *
186 * @get_phase: Queries the hardware to get the current phase of a clock.
187 * Returned values are 0-359 degrees on success, negative
188 * error codes on failure.
189 *
190 * @set_phase: Shift the phase this clock signal in degrees specified
191 * by the second argument. Valid values for degrees are
192 * 0-359. Return 0 on success, otherwise -EERROR.
193 *
194 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
195 * of a clock. Returned values denominator cannot be 0 and must be
196 * superior or equal to the numerator.
197 *
198 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
199 * the numerator (2nd argurment) and denominator (3rd argument).
200 * Argument must be a valid ratio (denominator > 0
201 * and >= numerator) Return 0 on success, otherwise -EERROR.
202 *
203 * @init: Perform platform-specific initialization magic.
204 * This is not used by any of the basic clock types.
205 * This callback exist for HW which needs to perform some
206 * initialisation magic for CCF to get an accurate view of the
207 * clock. It may also be used dynamic resource allocation is
208 * required. It shall not used to deal with clock parameters,
209 * such as rate or parents.
210 * Returns 0 on success, -EERROR otherwise.
211 *
212 * @terminate: Free any resource allocated by init.
213 *
214 * @debug_init: Set up type-specific debugfs entries for this clock. This
215 * is called once, after the debugfs directory entry for this
216 * clock has been created. The dentry pointer representing that
217 * directory is provided as an argument. Called with
218 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
219 *
220 *
221 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
222 * implementations to split any work between atomic (enable) and sleepable
223 * (prepare) contexts. If enabling a clock requires code that might sleep,
224 * this must be done in clk_prepare. Clock enable code that will never be
225 * called in a sleepable context may be implemented in clk_enable.
226 *
227 * Typically, drivers will call clk_prepare when a clock may be needed later
228 * (eg. when a device is opened), and clk_enable when the clock is actually
229 * required (eg. from an interrupt). Note that clk_prepare MUST have been
230 * called before clk_enable.
231 */
232 struct clk_ops {
233 int (*prepare)(struct clk_hw *hw);
234 void (*unprepare)(struct clk_hw *hw);
235 int (*is_prepared)(struct clk_hw *hw);
236 void (*unprepare_unused)(struct clk_hw *hw);
237 int (*enable)(struct clk_hw *hw);
238 void (*disable)(struct clk_hw *hw);
239 int (*is_enabled)(struct clk_hw *hw);
240 void (*disable_unused)(struct clk_hw *hw);
241 int (*save_context)(struct clk_hw *hw);
242 void (*restore_context)(struct clk_hw *hw);
243 unsigned long (*recalc_rate)(struct clk_hw *hw,
244 unsigned long parent_rate);
245 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
246 unsigned long *parent_rate);
247 int (*determine_rate)(struct clk_hw *hw,
248 struct clk_rate_request *req);
249 int (*set_parent)(struct clk_hw *hw, u8 index);
250 u8 (*get_parent)(struct clk_hw *hw);
251 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
252 unsigned long parent_rate);
253 int (*set_rate_and_parent)(struct clk_hw *hw,
254 unsigned long rate,
255 unsigned long parent_rate, u8 index);
256 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
257 unsigned long parent_accuracy);
258 int (*get_phase)(struct clk_hw *hw);
259 int (*set_phase)(struct clk_hw *hw, int degrees);
260 int (*get_duty_cycle)(struct clk_hw *hw,
261 struct clk_duty *duty);
262 int (*set_duty_cycle)(struct clk_hw *hw,
263 struct clk_duty *duty);
264 int (*init)(struct clk_hw *hw);
265 void (*terminate)(struct clk_hw *hw);
266 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
267 };
268
269 /**
270 * struct clk_parent_data - clk parent information
271 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
272 * @fw_name: parent name local to provider registering clk
273 * @name: globally unique parent name (used as a fallback)
274 * @index: parent index local to provider registering clk (if @fw_name absent)
275 */
276 struct clk_parent_data {
277 const struct clk_hw *hw;
278 const char *fw_name;
279 const char *name;
280 int index;
281 };
282
283 /**
284 * struct clk_init_data - holds init data that's common to all clocks and is
285 * shared between the clock provider and the common clock framework.
286 *
287 * @name: clock name
288 * @ops: operations this clock supports
289 * @parent_names: array of string names for all possible parents
290 * @parent_data: array of parent data for all possible parents (when some
291 * parents are external to the clk controller)
292 * @parent_hws: array of pointers to all possible parents (when all parents
293 * are internal to the clk controller)
294 * @num_parents: number of possible parents
295 * @flags: framework-level hints and quirks
296 */
297 struct clk_init_data {
298 const char *name;
299 const struct clk_ops *ops;
300 /* Only one of the following three should be assigned */
301 const char * const *parent_names;
302 const struct clk_parent_data *parent_data;
303 const struct clk_hw **parent_hws;
304 u8 num_parents;
305 unsigned long flags;
306 };
307
308 /**
309 * struct clk_hw - handle for traversing from a struct clk to its corresponding
310 * hardware-specific structure. struct clk_hw should be declared within struct
311 * clk_foo and then referenced by the struct clk instance that uses struct
312 * clk_foo's clk_ops
313 *
314 * @core: pointer to the struct clk_core instance that points back to this
315 * struct clk_hw instance
316 *
317 * @clk: pointer to the per-user struct clk instance that can be used to call
318 * into the clk API
319 *
320 * @init: pointer to struct clk_init_data that contains the init data shared
321 * with the common clock framework. This pointer will be set to NULL once
322 * a clk_register() variant is called on this clk_hw pointer.
323 */
324 struct clk_hw {
325 struct clk_core *core;
326 struct clk *clk;
327 const struct clk_init_data *init;
328 };
329
330 /*
331 * DOC: Basic clock implementations common to many platforms
332 *
333 * Each basic clock hardware type is comprised of a structure describing the
334 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
335 * unique flags for that hardware type, a registration function and an
336 * alternative macro for static initialization
337 */
338
339 /**
340 * struct clk_fixed_rate - fixed-rate clock
341 * @hw: handle between common and hardware-specific interfaces
342 * @fixed_rate: constant frequency of clock
343 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
344 * @flags: hardware specific flags
345 *
346 * Flags:
347 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
348 * instead of what's set in @fixed_accuracy.
349 */
350 struct clk_fixed_rate {
351 struct clk_hw hw;
352 unsigned long fixed_rate;
353 unsigned long fixed_accuracy;
354 unsigned long flags;
355 };
356
357 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
358
359 extern const struct clk_ops clk_fixed_rate_ops;
360 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
361 struct device_node *np, const char *name,
362 const char *parent_name, const struct clk_hw *parent_hw,
363 const struct clk_parent_data *parent_data, unsigned long flags,
364 unsigned long fixed_rate, unsigned long fixed_accuracy,
365 unsigned long clk_fixed_flags, bool devm);
366 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
367 const char *parent_name, unsigned long flags,
368 unsigned long fixed_rate);
369 /**
370 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
371 * framework
372 * @dev: device that is registering this clock
373 * @name: name of this clock
374 * @parent_name: name of clock's parent
375 * @flags: framework-specific flags
376 * @fixed_rate: non-adjustable clock rate
377 */
378 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
379 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
380 NULL, (flags), (fixed_rate), 0, 0, false)
381
382 /**
383 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
384 * framework
385 * @dev: device that is registering this clock
386 * @name: name of this clock
387 * @parent_name: name of clock's parent
388 * @flags: framework-specific flags
389 * @fixed_rate: non-adjustable clock rate
390 */
391 #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
392 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
393 NULL, (flags), (fixed_rate), 0, 0, true)
394 /**
395 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
396 * the clock framework
397 * @dev: device that is registering this clock
398 * @name: name of this clock
399 * @parent_hw: pointer to parent clk
400 * @flags: framework-specific flags
401 * @fixed_rate: non-adjustable clock rate
402 */
403 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
404 fixed_rate) \
405 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
406 NULL, (flags), (fixed_rate), 0, 0, false)
407 /**
408 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
409 * the clock framework
410 * @dev: device that is registering this clock
411 * @name: name of this clock
412 * @parent_data: parent clk data
413 * @flags: framework-specific flags
414 * @fixed_rate: non-adjustable clock rate
415 */
416 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
417 fixed_rate) \
418 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
419 (parent_data), (flags), (fixed_rate), 0, \
420 0, false)
421 /**
422 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
423 * the clock framework
424 * @dev: device that is registering this clock
425 * @name: name of this clock
426 * @parent_name: name of clock's parent
427 * @flags: framework-specific flags
428 * @fixed_rate: non-adjustable clock rate
429 * @fixed_accuracy: non-adjustable clock accuracy
430 */
431 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
432 flags, fixed_rate, \
433 fixed_accuracy) \
434 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
435 NULL, NULL, (flags), (fixed_rate), \
436 (fixed_accuracy), 0, false)
437 /**
438 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
439 * clock with the clock framework
440 * @dev: device that is registering this clock
441 * @name: name of this clock
442 * @parent_hw: pointer to parent clk
443 * @flags: framework-specific flags
444 * @fixed_rate: non-adjustable clock rate
445 * @fixed_accuracy: non-adjustable clock accuracy
446 */
447 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
448 parent_hw, flags, fixed_rate, fixed_accuracy) \
449 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
450 NULL, NULL, (flags), (fixed_rate), \
451 (fixed_accuracy), 0, false)
452 /**
453 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
454 * clock with the clock framework
455 * @dev: device that is registering this clock
456 * @name: name of this clock
457 * @parent_name: name of clock's parent
458 * @flags: framework-specific flags
459 * @fixed_rate: non-adjustable clock rate
460 * @fixed_accuracy: non-adjustable clock accuracy
461 */
462 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
463 parent_data, flags, fixed_rate, fixed_accuracy) \
464 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
465 (parent_data), NULL, (flags), \
466 (fixed_rate), (fixed_accuracy), 0, false)
467 /**
468 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
469 * the clock framework
470 * @dev: device that is registering this clock
471 * @name: name of this clock
472 * @parent_name: name of clock's parent
473 * @flags: framework-specific flags
474 * @fixed_rate: non-adjustable clock rate
475 */
476 #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
477 flags, fixed_rate) \
478 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
479 (parent_data), (flags), (fixed_rate), 0, \
480 CLK_FIXED_RATE_PARENT_ACCURACY, false)
481
482 void clk_unregister_fixed_rate(struct clk *clk);
483 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
484
485 void of_fixed_clk_setup(struct device_node *np);
486
487 /**
488 * struct clk_gate - gating clock
489 *
490 * @hw: handle between common and hardware-specific interfaces
491 * @reg: register controlling gate
492 * @bit_idx: single bit controlling gate
493 * @flags: hardware-specific flags
494 * @lock: register lock
495 *
496 * Clock which can gate its output. Implements .enable & .disable
497 *
498 * Flags:
499 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
500 * enable the clock. Setting this flag does the opposite: setting the bit
501 * disable the clock and clearing it enables the clock
502 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
503 * of this register, and mask of gate bits are in higher 16-bit of this
504 * register. While setting the gate bits, higher 16-bit should also be
505 * updated to indicate changing gate bits.
506 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
507 * the gate register. Setting this flag makes the register accesses big
508 * endian.
509 */
510 struct clk_gate {
511 struct clk_hw hw;
512 void __iomem *reg;
513 u8 bit_idx;
514 u8 flags;
515 spinlock_t *lock;
516 };
517
518 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
519
520 #define CLK_GATE_SET_TO_DISABLE BIT(0)
521 #define CLK_GATE_HIWORD_MASK BIT(1)
522 #define CLK_GATE_BIG_ENDIAN BIT(2)
523
524 extern const struct clk_ops clk_gate_ops;
525 struct clk_hw *__clk_hw_register_gate(struct device *dev,
526 struct device_node *np, const char *name,
527 const char *parent_name, const struct clk_hw *parent_hw,
528 const struct clk_parent_data *parent_data,
529 unsigned long flags,
530 void __iomem *reg, u8 bit_idx,
531 u8 clk_gate_flags, spinlock_t *lock);
532 struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
533 struct device_node *np, const char *name,
534 const char *parent_name, const struct clk_hw *parent_hw,
535 const struct clk_parent_data *parent_data,
536 unsigned long flags,
537 void __iomem *reg, u8 bit_idx,
538 u8 clk_gate_flags, spinlock_t *lock);
539 struct clk *clk_register_gate(struct device *dev, const char *name,
540 const char *parent_name, unsigned long flags,
541 void __iomem *reg, u8 bit_idx,
542 u8 clk_gate_flags, spinlock_t *lock);
543 /**
544 * clk_hw_register_gate - register a gate clock with the clock framework
545 * @dev: device that is registering this clock
546 * @name: name of this clock
547 * @parent_name: name of this clock's parent
548 * @flags: framework-specific flags for this clock
549 * @reg: register address to control gating of this clock
550 * @bit_idx: which bit in the register controls gating of this clock
551 * @clk_gate_flags: gate-specific flags for this clock
552 * @lock: shared register lock for this clock
553 */
554 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
555 clk_gate_flags, lock) \
556 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
557 NULL, (flags), (reg), (bit_idx), \
558 (clk_gate_flags), (lock))
559 /**
560 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
561 * framework
562 * @dev: device that is registering this clock
563 * @name: name of this clock
564 * @parent_hw: pointer to parent clk
565 * @flags: framework-specific flags for this clock
566 * @reg: register address to control gating of this clock
567 * @bit_idx: which bit in the register controls gating of this clock
568 * @clk_gate_flags: gate-specific flags for this clock
569 * @lock: shared register lock for this clock
570 */
571 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
572 bit_idx, clk_gate_flags, lock) \
573 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
574 NULL, (flags), (reg), (bit_idx), \
575 (clk_gate_flags), (lock))
576 /**
577 * clk_hw_register_gate_parent_data - register a gate clock with the clock
578 * framework
579 * @dev: device that is registering this clock
580 * @name: name of this clock
581 * @parent_data: parent clk data
582 * @flags: framework-specific flags for this clock
583 * @reg: register address to control gating of this clock
584 * @bit_idx: which bit in the register controls gating of this clock
585 * @clk_gate_flags: gate-specific flags for this clock
586 * @lock: shared register lock for this clock
587 */
588 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
589 bit_idx, clk_gate_flags, lock) \
590 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
591 (flags), (reg), (bit_idx), \
592 (clk_gate_flags), (lock))
593 /**
594 * devm_clk_hw_register_gate - register a gate clock with the clock framework
595 * @dev: device that is registering this clock
596 * @name: name of this clock
597 * @parent_name: name of this clock's parent
598 * @flags: framework-specific flags for this clock
599 * @reg: register address to control gating of this clock
600 * @bit_idx: which bit in the register controls gating of this clock
601 * @clk_gate_flags: gate-specific flags for this clock
602 * @lock: shared register lock for this clock
603 */
604 #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
605 clk_gate_flags, lock) \
606 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
607 NULL, (flags), (reg), (bit_idx), \
608 (clk_gate_flags), (lock))
609 void clk_unregister_gate(struct clk *clk);
610 void clk_hw_unregister_gate(struct clk_hw *hw);
611 int clk_gate_is_enabled(struct clk_hw *hw);
612
613 struct clk_div_table {
614 unsigned int val;
615 unsigned int div;
616 };
617
618 /**
619 * struct clk_divider - adjustable divider clock
620 *
621 * @hw: handle between common and hardware-specific interfaces
622 * @reg: register containing the divider
623 * @shift: shift to the divider bit field
624 * @width: width of the divider bit field
625 * @table: array of value/divider pairs, last entry should have div = 0
626 * @lock: register lock
627 *
628 * Clock with an adjustable divider affecting its output frequency. Implements
629 * .recalc_rate, .set_rate and .round_rate
630 *
631 * Flags:
632 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
633 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
634 * the raw value read from the register, with the value of zero considered
635 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
636 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
637 * the hardware register
638 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
639 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
640 * Some hardware implementations gracefully handle this case and allow a
641 * zero divisor by not modifying their input clock
642 * (divide by one / bypass).
643 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
644 * of this register, and mask of divider bits are in higher 16-bit of this
645 * register. While setting the divider bits, higher 16-bit should also be
646 * updated to indicate changing divider bits.
647 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
648 * to the closest integer instead of the up one.
649 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
650 * not be changed by the clock framework.
651 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
652 * except when the value read from the register is zero, the divisor is
653 * 2^width of the field.
654 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
655 * for the divider register. Setting this flag makes the register accesses
656 * big endian.
657 */
658 struct clk_divider {
659 struct clk_hw hw;
660 void __iomem *reg;
661 u8 shift;
662 u8 width;
663 u8 flags;
664 const struct clk_div_table *table;
665 spinlock_t *lock;
666 };
667
668 #define clk_div_mask(width) ((1 << (width)) - 1)
669 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
670
671 #define CLK_DIVIDER_ONE_BASED BIT(0)
672 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
673 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
674 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
675 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
676 #define CLK_DIVIDER_READ_ONLY BIT(5)
677 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
678 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
679
680 extern const struct clk_ops clk_divider_ops;
681 extern const struct clk_ops clk_divider_ro_ops;
682
683 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
684 unsigned int val, const struct clk_div_table *table,
685 unsigned long flags, unsigned long width);
686 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
687 unsigned long rate, unsigned long *prate,
688 const struct clk_div_table *table,
689 u8 width, unsigned long flags);
690 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
691 unsigned long rate, unsigned long *prate,
692 const struct clk_div_table *table, u8 width,
693 unsigned long flags, unsigned int val);
694 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
695 const struct clk_div_table *table, u8 width,
696 unsigned long flags);
697 int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
698 const struct clk_div_table *table, u8 width,
699 unsigned long flags, unsigned int val);
700 int divider_get_val(unsigned long rate, unsigned long parent_rate,
701 const struct clk_div_table *table, u8 width,
702 unsigned long flags);
703
704 struct clk_hw *__clk_hw_register_divider(struct device *dev,
705 struct device_node *np, const char *name,
706 const char *parent_name, const struct clk_hw *parent_hw,
707 const struct clk_parent_data *parent_data, unsigned long flags,
708 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
709 const struct clk_div_table *table, spinlock_t *lock);
710 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
711 struct device_node *np, const char *name,
712 const char *parent_name, const struct clk_hw *parent_hw,
713 const struct clk_parent_data *parent_data, unsigned long flags,
714 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
715 const struct clk_div_table *table, spinlock_t *lock);
716 struct clk *clk_register_divider_table(struct device *dev, const char *name,
717 const char *parent_name, unsigned long flags,
718 void __iomem *reg, u8 shift, u8 width,
719 u8 clk_divider_flags, const struct clk_div_table *table,
720 spinlock_t *lock);
721 /**
722 * clk_register_divider - register a divider clock with the clock framework
723 * @dev: device registering this clock
724 * @name: name of this clock
725 * @parent_name: name of clock's parent
726 * @flags: framework-specific flags
727 * @reg: register address to adjust divider
728 * @shift: number of bits to shift the bitfield
729 * @width: width of the bitfield
730 * @clk_divider_flags: divider-specific flags for this clock
731 * @lock: shared register lock for this clock
732 */
733 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
734 clk_divider_flags, lock) \
735 clk_register_divider_table((dev), (name), (parent_name), (flags), \
736 (reg), (shift), (width), \
737 (clk_divider_flags), NULL, (lock))
738 /**
739 * clk_hw_register_divider - register a divider clock with the clock framework
740 * @dev: device registering this clock
741 * @name: name of this clock
742 * @parent_name: name of clock's parent
743 * @flags: framework-specific flags
744 * @reg: register address to adjust divider
745 * @shift: number of bits to shift the bitfield
746 * @width: width of the bitfield
747 * @clk_divider_flags: divider-specific flags for this clock
748 * @lock: shared register lock for this clock
749 */
750 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
751 width, clk_divider_flags, lock) \
752 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
753 NULL, (flags), (reg), (shift), (width), \
754 (clk_divider_flags), NULL, (lock))
755 /**
756 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
757 * framework
758 * @dev: device registering this clock
759 * @name: name of this clock
760 * @parent_hw: pointer to parent clk
761 * @flags: framework-specific flags
762 * @reg: register address to adjust divider
763 * @shift: number of bits to shift the bitfield
764 * @width: width of the bitfield
765 * @clk_divider_flags: divider-specific flags for this clock
766 * @lock: shared register lock for this clock
767 */
768 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
769 shift, width, clk_divider_flags, \
770 lock) \
771 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
772 NULL, (flags), (reg), (shift), (width), \
773 (clk_divider_flags), NULL, (lock))
774 /**
775 * clk_hw_register_divider_parent_data - register a divider clock with the clock
776 * framework
777 * @dev: device registering this clock
778 * @name: name of this clock
779 * @parent_data: parent clk data
780 * @flags: framework-specific flags
781 * @reg: register address to adjust divider
782 * @shift: number of bits to shift the bitfield
783 * @width: width of the bitfield
784 * @clk_divider_flags: divider-specific flags for this clock
785 * @lock: shared register lock for this clock
786 */
787 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
788 reg, shift, width, \
789 clk_divider_flags, lock) \
790 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
791 (parent_data), (flags), (reg), (shift), \
792 (width), (clk_divider_flags), NULL, (lock))
793 /**
794 * clk_hw_register_divider_table - register a table based divider clock with
795 * the clock framework
796 * @dev: device registering this clock
797 * @name: name of this clock
798 * @parent_name: name of clock's parent
799 * @flags: framework-specific flags
800 * @reg: register address to adjust divider
801 * @shift: number of bits to shift the bitfield
802 * @width: width of the bitfield
803 * @clk_divider_flags: divider-specific flags for this clock
804 * @table: array of divider/value pairs ending with a div set to 0
805 * @lock: shared register lock for this clock
806 */
807 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
808 shift, width, clk_divider_flags, table, \
809 lock) \
810 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
811 NULL, (flags), (reg), (shift), (width), \
812 (clk_divider_flags), (table), (lock))
813 /**
814 * clk_hw_register_divider_table_parent_hw - register a table based divider
815 * clock with the clock framework
816 * @dev: device registering this clock
817 * @name: name of this clock
818 * @parent_hw: pointer to parent clk
819 * @flags: framework-specific flags
820 * @reg: register address to adjust divider
821 * @shift: number of bits to shift the bitfield
822 * @width: width of the bitfield
823 * @clk_divider_flags: divider-specific flags for this clock
824 * @table: array of divider/value pairs ending with a div set to 0
825 * @lock: shared register lock for this clock
826 */
827 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
828 reg, shift, width, \
829 clk_divider_flags, table, \
830 lock) \
831 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
832 NULL, (flags), (reg), (shift), (width), \
833 (clk_divider_flags), (table), (lock))
834 /**
835 * clk_hw_register_divider_table_parent_data - register a table based divider
836 * clock with the clock framework
837 * @dev: device registering this clock
838 * @name: name of this clock
839 * @parent_data: parent clk data
840 * @flags: framework-specific flags
841 * @reg: register address to adjust divider
842 * @shift: number of bits to shift the bitfield
843 * @width: width of the bitfield
844 * @clk_divider_flags: divider-specific flags for this clock
845 * @table: array of divider/value pairs ending with a div set to 0
846 * @lock: shared register lock for this clock
847 */
848 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
849 flags, reg, shift, width, \
850 clk_divider_flags, table, \
851 lock) \
852 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
853 (parent_data), (flags), (reg), (shift), \
854 (width), (clk_divider_flags), (table), \
855 (lock))
856 /**
857 * devm_clk_hw_register_divider - register a divider clock with the clock framework
858 * @dev: device registering this clock
859 * @name: name of this clock
860 * @parent_name: name of clock's parent
861 * @flags: framework-specific flags
862 * @reg: register address to adjust divider
863 * @shift: number of bits to shift the bitfield
864 * @width: width of the bitfield
865 * @clk_divider_flags: divider-specific flags for this clock
866 * @lock: shared register lock for this clock
867 */
868 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
869 width, clk_divider_flags, lock) \
870 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
871 NULL, (flags), (reg), (shift), (width), \
872 (clk_divider_flags), NULL, (lock))
873 /**
874 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
875 * @dev: device registering this clock
876 * @name: name of this clock
877 * @parent_hw: pointer to parent clk
878 * @flags: framework-specific flags
879 * @reg: register address to adjust divider
880 * @shift: number of bits to shift the bitfield
881 * @width: width of the bitfield
882 * @clk_divider_flags: divider-specific flags for this clock
883 * @lock: shared register lock for this clock
884 */
885 #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \
886 reg, shift, width, \
887 clk_divider_flags, lock) \
888 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \
889 (parent_hw), NULL, (flags), (reg), \
890 (shift), (width), (clk_divider_flags), \
891 NULL, (lock))
892 /**
893 * devm_clk_hw_register_divider_table - register a table based divider clock
894 * with the clock framework (devres variant)
895 * @dev: device registering this clock
896 * @name: name of this clock
897 * @parent_name: name of clock's parent
898 * @flags: framework-specific flags
899 * @reg: register address to adjust divider
900 * @shift: number of bits to shift the bitfield
901 * @width: width of the bitfield
902 * @clk_divider_flags: divider-specific flags for this clock
903 * @table: array of divider/value pairs ending with a div set to 0
904 * @lock: shared register lock for this clock
905 */
906 #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
907 reg, shift, width, \
908 clk_divider_flags, table, lock) \
909 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
910 NULL, NULL, (flags), (reg), (shift), \
911 (width), (clk_divider_flags), (table), \
912 (lock))
913
914 void clk_unregister_divider(struct clk *clk);
915 void clk_hw_unregister_divider(struct clk_hw *hw);
916
917 /**
918 * struct clk_mux - multiplexer clock
919 *
920 * @hw: handle between common and hardware-specific interfaces
921 * @reg: register controlling multiplexer
922 * @table: array of register values corresponding to the parent index
923 * @shift: shift to multiplexer bit field
924 * @mask: mask of mutliplexer bit field
925 * @flags: hardware-specific flags
926 * @lock: register lock
927 *
928 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
929 * and .recalc_rate
930 *
931 * Flags:
932 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
933 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
934 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
935 * register, and mask of mux bits are in higher 16-bit of this register.
936 * While setting the mux bits, higher 16-bit should also be updated to
937 * indicate changing mux bits.
938 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
939 * .get_parent clk_op.
940 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
941 * frequency.
942 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
943 * the mux register. Setting this flag makes the register accesses big
944 * endian.
945 */
946 struct clk_mux {
947 struct clk_hw hw;
948 void __iomem *reg;
949 const u32 *table;
950 u32 mask;
951 u8 shift;
952 u8 flags;
953 spinlock_t *lock;
954 };
955
956 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
957
958 #define CLK_MUX_INDEX_ONE BIT(0)
959 #define CLK_MUX_INDEX_BIT BIT(1)
960 #define CLK_MUX_HIWORD_MASK BIT(2)
961 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
962 #define CLK_MUX_ROUND_CLOSEST BIT(4)
963 #define CLK_MUX_BIG_ENDIAN BIT(5)
964
965 extern const struct clk_ops clk_mux_ops;
966 extern const struct clk_ops clk_mux_ro_ops;
967
968 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
969 const char *name, u8 num_parents,
970 const char * const *parent_names,
971 const struct clk_hw **parent_hws,
972 const struct clk_parent_data *parent_data,
973 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
974 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
975 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
976 const char *name, u8 num_parents,
977 const char * const *parent_names,
978 const struct clk_hw **parent_hws,
979 const struct clk_parent_data *parent_data,
980 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
981 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
982 struct clk *clk_register_mux_table(struct device *dev, const char *name,
983 const char * const *parent_names, u8 num_parents,
984 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
985 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
986
987 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
988 shift, width, clk_mux_flags, lock) \
989 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
990 (flags), (reg), (shift), BIT((width)) - 1, \
991 (clk_mux_flags), NULL, (lock))
992 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
993 flags, reg, shift, mask, clk_mux_flags, \
994 table, lock) \
995 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
996 (parent_names), NULL, NULL, (flags), (reg), \
997 (shift), (mask), (clk_mux_flags), (table), \
998 (lock))
999 #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
1000 num_parents, flags, reg, shift, mask, \
1001 clk_mux_flags, table, lock) \
1002 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1003 NULL, NULL, (parent_data), (flags), (reg), \
1004 (shift), (mask), (clk_mux_flags), (table), \
1005 (lock))
1006 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1007 shift, width, clk_mux_flags, lock) \
1008 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1009 (parent_names), NULL, NULL, (flags), (reg), \
1010 (shift), BIT((width)) - 1, (clk_mux_flags), \
1011 NULL, (lock))
1012 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
1013 reg, shift, width, clk_mux_flags, lock) \
1014 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1015 (parent_hws), NULL, (flags), (reg), (shift), \
1016 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1017 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
1018 flags, reg, shift, width, \
1019 clk_mux_flags, lock) \
1020 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1021 (parent_data), (flags), (reg), (shift), \
1022 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1023 #define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1024 num_parents, flags, reg, shift, \
1025 width, clk_mux_flags, table, \
1026 lock) \
1027 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1028 (parent_data), (flags), (reg), (shift), \
1029 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1030 #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1031 shift, width, clk_mux_flags, lock) \
1032 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1033 (parent_names), NULL, NULL, (flags), (reg), \
1034 (shift), BIT((width)) - 1, (clk_mux_flags), \
1035 NULL, (lock))
1036 #define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \
1037 num_parents, flags, reg, shift, \
1038 width, clk_mux_flags, lock) \
1039 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1040 (parent_hws), NULL, (flags), (reg), \
1041 (shift), BIT((width)) - 1, \
1042 (clk_mux_flags), NULL, (lock))
1043 #define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1044 num_parents, flags, reg, shift, \
1045 width, clk_mux_flags, table, \
1046 lock) \
1047 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1048 NULL, (parent_data), (flags), (reg), (shift), \
1049 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1050
1051 int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
1052 unsigned int val);
1053 unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index);
1054
1055 void clk_unregister_mux(struct clk *clk);
1056 void clk_hw_unregister_mux(struct clk_hw *hw);
1057
1058 void of_fixed_factor_clk_setup(struct device_node *node);
1059
1060 /**
1061 * struct clk_fixed_factor - fixed multiplier and divider clock
1062 *
1063 * @hw: handle between common and hardware-specific interfaces
1064 * @mult: multiplier
1065 * @div: divider
1066 *
1067 * Clock with a fixed multiplier and divider. The output frequency is the
1068 * parent clock rate divided by div and multiplied by mult.
1069 * Implements .recalc_rate, .set_rate and .round_rate
1070 */
1071
1072 struct clk_fixed_factor {
1073 struct clk_hw hw;
1074 unsigned int mult;
1075 unsigned int div;
1076 };
1077
1078 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
1079
1080 extern const struct clk_ops clk_fixed_factor_ops;
1081 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1082 const char *parent_name, unsigned long flags,
1083 unsigned int mult, unsigned int div);
1084 void clk_unregister_fixed_factor(struct clk *clk);
1085 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
1086 const char *name, const char *parent_name, unsigned long flags,
1087 unsigned int mult, unsigned int div);
1088 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
1089 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
1090 const char *name, const char *parent_name, unsigned long flags,
1091 unsigned int mult, unsigned int div);
1092 struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1093 const char *name, unsigned int index, unsigned long flags,
1094 unsigned int mult, unsigned int div);
1095
1096 struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1097 const char *name, const struct clk_hw *parent_hw,
1098 unsigned long flags, unsigned int mult, unsigned int div);
1099
1100 struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1101 const char *name, const struct clk_hw *parent_hw,
1102 unsigned long flags, unsigned int mult, unsigned int div);
1103 /**
1104 * struct clk_fractional_divider - adjustable fractional divider clock
1105 *
1106 * @hw: handle between common and hardware-specific interfaces
1107 * @reg: register containing the divider
1108 * @mshift: shift to the numerator bit field
1109 * @mwidth: width of the numerator bit field
1110 * @nshift: shift to the denominator bit field
1111 * @nwidth: width of the denominator bit field
1112 * @lock: register lock
1113 *
1114 * Clock with adjustable fractional divider affecting its output frequency.
1115 *
1116 * Flags:
1117 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1118 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
1119 * is set then the numerator and denominator are both the value read
1120 * plus one.
1121 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1122 * used for the divider register. Setting this flag makes the register
1123 * accesses big endian.
1124 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1125 * be saturated and the caller will get quite far from the good enough
1126 * approximation. Instead the caller may require, by setting this flag,
1127 * to shift left by a few bits in case, when the asked one is quite small
1128 * to satisfy the desired range of denominator. It assumes that on the
1129 * caller's side the power-of-two capable prescaler exists.
1130 */
1131 struct clk_fractional_divider {
1132 struct clk_hw hw;
1133 void __iomem *reg;
1134 u8 mshift;
1135 u8 mwidth;
1136 u32 mmask;
1137 u8 nshift;
1138 u8 nwidth;
1139 u32 nmask;
1140 u8 flags;
1141 void (*approximation)(struct clk_hw *hw,
1142 unsigned long rate, unsigned long *parent_rate,
1143 unsigned long *m, unsigned long *n);
1144 spinlock_t *lock;
1145 };
1146
1147 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
1148
1149 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
1150 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
1151 #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
1152
1153 struct clk *clk_register_fractional_divider(struct device *dev,
1154 const char *name, const char *parent_name, unsigned long flags,
1155 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1156 u8 clk_divider_flags, spinlock_t *lock);
1157 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1158 const char *name, const char *parent_name, unsigned long flags,
1159 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1160 u8 clk_divider_flags, spinlock_t *lock);
1161 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1162
1163 /**
1164 * struct clk_multiplier - adjustable multiplier clock
1165 *
1166 * @hw: handle between common and hardware-specific interfaces
1167 * @reg: register containing the multiplier
1168 * @shift: shift to the multiplier bit field
1169 * @width: width of the multiplier bit field
1170 * @lock: register lock
1171 *
1172 * Clock with an adjustable multiplier affecting its output frequency.
1173 * Implements .recalc_rate, .set_rate and .round_rate
1174 *
1175 * Flags:
1176 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1177 * from the register, with 0 being a valid value effectively
1178 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1179 * set, then a null multiplier will be considered as a bypass,
1180 * leaving the parent rate unmodified.
1181 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1182 * rounded to the closest integer instead of the down one.
1183 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1184 * used for the multiplier register. Setting this flag makes the register
1185 * accesses big endian.
1186 */
1187 struct clk_multiplier {
1188 struct clk_hw hw;
1189 void __iomem *reg;
1190 u8 shift;
1191 u8 width;
1192 u8 flags;
1193 spinlock_t *lock;
1194 };
1195
1196 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1197
1198 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1199 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1200 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1201
1202 extern const struct clk_ops clk_multiplier_ops;
1203
1204 /***
1205 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1206 *
1207 * @hw: handle between common and hardware-specific interfaces
1208 * @mux_hw: handle between composite and hardware-specific mux clock
1209 * @rate_hw: handle between composite and hardware-specific rate clock
1210 * @gate_hw: handle between composite and hardware-specific gate clock
1211 * @mux_ops: clock ops for mux
1212 * @rate_ops: clock ops for rate
1213 * @gate_ops: clock ops for gate
1214 */
1215 struct clk_composite {
1216 struct clk_hw hw;
1217 struct clk_ops ops;
1218
1219 struct clk_hw *mux_hw;
1220 struct clk_hw *rate_hw;
1221 struct clk_hw *gate_hw;
1222
1223 const struct clk_ops *mux_ops;
1224 const struct clk_ops *rate_ops;
1225 const struct clk_ops *gate_ops;
1226 };
1227
1228 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1229
1230 struct clk *clk_register_composite(struct device *dev, const char *name,
1231 const char * const *parent_names, int num_parents,
1232 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1233 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1234 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1235 unsigned long flags);
1236 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1237 const struct clk_parent_data *parent_data, int num_parents,
1238 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1239 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1240 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1241 unsigned long flags);
1242 void clk_unregister_composite(struct clk *clk);
1243 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1244 const char * const *parent_names, int num_parents,
1245 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1246 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1247 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1248 unsigned long flags);
1249 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1250 const char *name,
1251 const struct clk_parent_data *parent_data, int num_parents,
1252 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1253 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1254 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1255 unsigned long flags);
1256 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1257 const char *name, const struct clk_parent_data *parent_data,
1258 int num_parents,
1259 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1260 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1261 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1262 unsigned long flags);
1263 void clk_hw_unregister_composite(struct clk_hw *hw);
1264
1265 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1266 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1267
1268 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1269 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1270 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1271
1272 void clk_unregister(struct clk *clk);
1273
1274 void clk_hw_unregister(struct clk_hw *hw);
1275
1276 /* helper functions */
1277 const char *__clk_get_name(const struct clk *clk);
1278 const char *clk_hw_get_name(const struct clk_hw *hw);
1279 #ifdef CONFIG_COMMON_CLK
1280 struct clk_hw *__clk_get_hw(struct clk *clk);
1281 #else
__clk_get_hw(struct clk * clk)1282 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1283 {
1284 return (struct clk_hw *)clk;
1285 }
1286 #endif
1287
1288 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1289 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1290 const char *con_id);
1291
1292 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1293 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1294 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1295 unsigned int index);
1296 int clk_hw_get_parent_index(struct clk_hw *hw);
1297 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1298 unsigned int __clk_get_enable_count(struct clk *clk);
1299 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1300 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1301 #define clk_hw_can_set_rate_parent(hw) \
1302 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1303
1304 bool clk_hw_is_prepared(const struct clk_hw *hw);
1305 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1306 bool clk_hw_is_enabled(const struct clk_hw *hw);
1307 bool __clk_is_enabled(struct clk *clk);
1308 struct clk *__clk_lookup(const char *name);
1309 int __clk_mux_determine_rate(struct clk_hw *hw,
1310 struct clk_rate_request *req);
1311 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1312 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1313 struct clk_rate_request *req);
1314 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1315 struct clk_rate_request *req,
1316 unsigned long flags);
1317 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1318 void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,
1319 unsigned long *max_rate);
1320 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1321 unsigned long max_rate);
1322
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)1323 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1324 {
1325 dst->clk = src->clk;
1326 dst->core = src->core;
1327 }
1328
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)1329 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1330 unsigned long *prate,
1331 const struct clk_div_table *table,
1332 u8 width, unsigned long flags)
1333 {
1334 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1335 rate, prate, table, width, flags);
1336 }
1337
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)1338 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1339 unsigned long *prate,
1340 const struct clk_div_table *table,
1341 u8 width, unsigned long flags,
1342 unsigned int val)
1343 {
1344 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1345 rate, prate, table, width, flags,
1346 val);
1347 }
1348
1349 /*
1350 * FIXME clock api without lock protection
1351 */
1352 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1353
1354 struct clk_onecell_data {
1355 struct clk **clks;
1356 unsigned int clk_num;
1357 };
1358
1359 struct clk_hw_onecell_data {
1360 unsigned int num;
1361 struct clk_hw *hws[];
1362 };
1363
1364 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1365
1366 /*
1367 * Use this macro when you have a driver that requires two initialization
1368 * routines, one at of_clk_init(), and one at platform device probe
1369 */
1370 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1371 static void __init name##_of_clk_init_driver(struct device_node *np) \
1372 { \
1373 of_node_clear_flag(np, OF_POPULATED); \
1374 fn(np); \
1375 } \
1376 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1377
1378 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1379 (&(struct clk_init_data) { \
1380 .flags = _flags, \
1381 .name = _name, \
1382 .parent_names = (const char *[]) { _parent }, \
1383 .num_parents = 1, \
1384 .ops = _ops, \
1385 })
1386
1387 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1388 (&(struct clk_init_data) { \
1389 .flags = _flags, \
1390 .name = _name, \
1391 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1392 .num_parents = 1, \
1393 .ops = _ops, \
1394 })
1395
1396 /*
1397 * This macro is intended for drivers to be able to share the otherwise
1398 * individual struct clk_hw[] compound literals created by the compiler
1399 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1400 */
1401 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1402 (&(struct clk_init_data) { \
1403 .flags = _flags, \
1404 .name = _name, \
1405 .parent_hws = _parent, \
1406 .num_parents = 1, \
1407 .ops = _ops, \
1408 })
1409
1410 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1411 (&(struct clk_init_data) { \
1412 .flags = _flags, \
1413 .name = _name, \
1414 .parent_data = (const struct clk_parent_data[]) { \
1415 { .fw_name = _parent }, \
1416 }, \
1417 .num_parents = 1, \
1418 .ops = _ops, \
1419 })
1420
1421 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1422 (&(struct clk_init_data) { \
1423 .flags = _flags, \
1424 .name = _name, \
1425 .parent_names = _parents, \
1426 .num_parents = ARRAY_SIZE(_parents), \
1427 .ops = _ops, \
1428 })
1429
1430 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1431 (&(struct clk_init_data) { \
1432 .flags = _flags, \
1433 .name = _name, \
1434 .parent_hws = _parents, \
1435 .num_parents = ARRAY_SIZE(_parents), \
1436 .ops = _ops, \
1437 })
1438
1439 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1440 (&(struct clk_init_data) { \
1441 .flags = _flags, \
1442 .name = _name, \
1443 .parent_data = _parents, \
1444 .num_parents = ARRAY_SIZE(_parents), \
1445 .ops = _ops, \
1446 })
1447
1448 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1449 (&(struct clk_init_data) { \
1450 .flags = _flags, \
1451 .name = _name, \
1452 .parent_names = NULL, \
1453 .num_parents = 0, \
1454 .ops = _ops, \
1455 })
1456
1457 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1458 _div, _mult, _flags) \
1459 struct clk_fixed_factor _struct = { \
1460 .div = _div, \
1461 .mult = _mult, \
1462 .hw.init = CLK_HW_INIT(_name, \
1463 _parent, \
1464 &clk_fixed_factor_ops, \
1465 _flags), \
1466 }
1467
1468 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1469 _div, _mult, _flags) \
1470 struct clk_fixed_factor _struct = { \
1471 .div = _div, \
1472 .mult = _mult, \
1473 .hw.init = CLK_HW_INIT_HW(_name, \
1474 _parent, \
1475 &clk_fixed_factor_ops, \
1476 _flags), \
1477 }
1478
1479 /*
1480 * This macro allows the driver to reuse the _parent array for multiple
1481 * fixed factor clk declarations.
1482 */
1483 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1484 _div, _mult, _flags) \
1485 struct clk_fixed_factor _struct = { \
1486 .div = _div, \
1487 .mult = _mult, \
1488 .hw.init = CLK_HW_INIT_HWS(_name, \
1489 _parent, \
1490 &clk_fixed_factor_ops, \
1491 _flags), \
1492 }
1493
1494 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1495 _div, _mult, _flags) \
1496 struct clk_fixed_factor _struct = { \
1497 .div = _div, \
1498 .mult = _mult, \
1499 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1500 _parent, \
1501 &clk_fixed_factor_ops, \
1502 _flags), \
1503 }
1504
1505 #ifdef CONFIG_OF
1506 int of_clk_add_provider(struct device_node *np,
1507 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1508 void *data),
1509 void *data);
1510 int of_clk_add_hw_provider(struct device_node *np,
1511 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1512 void *data),
1513 void *data);
1514 int devm_of_clk_add_hw_provider(struct device *dev,
1515 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1516 void *data),
1517 void *data);
1518 void of_clk_del_provider(struct device_node *np);
1519
1520 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1521 void *data);
1522 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1523 void *data);
1524 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1525 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1526 void *data);
1527 int of_clk_parent_fill(struct device_node *np, const char **parents,
1528 unsigned int size);
1529 int of_clk_detect_critical(struct device_node *np, int index,
1530 unsigned long *flags);
1531
1532 #else /* !CONFIG_OF */
1533
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1534 static inline int of_clk_add_provider(struct device_node *np,
1535 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1536 void *data),
1537 void *data)
1538 {
1539 return 0;
1540 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1541 static inline int of_clk_add_hw_provider(struct device_node *np,
1542 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1543 void *data),
1544 void *data)
1545 {
1546 return 0;
1547 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1548 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1549 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1550 void *data),
1551 void *data)
1552 {
1553 return 0;
1554 }
of_clk_del_provider(struct device_node * np)1555 static inline void of_clk_del_provider(struct device_node *np) {}
1556
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1557 static inline struct clk *of_clk_src_simple_get(
1558 struct of_phandle_args *clkspec, void *data)
1559 {
1560 return ERR_PTR(-ENOENT);
1561 }
1562 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1563 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1564 {
1565 return ERR_PTR(-ENOENT);
1566 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1567 static inline struct clk *of_clk_src_onecell_get(
1568 struct of_phandle_args *clkspec, void *data)
1569 {
1570 return ERR_PTR(-ENOENT);
1571 }
1572 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1573 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1574 {
1575 return ERR_PTR(-ENOENT);
1576 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1577 static inline int of_clk_parent_fill(struct device_node *np,
1578 const char **parents, unsigned int size)
1579 {
1580 return 0;
1581 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1582 static inline int of_clk_detect_critical(struct device_node *np, int index,
1583 unsigned long *flags)
1584 {
1585 return 0;
1586 }
1587 #endif /* CONFIG_OF */
1588
1589 void clk_gate_restore_context(struct clk_hw *hw);
1590
1591 #endif /* CLK_PROVIDER_H */
1592