1 /* 2 * cfgdefs.h 3 * 4 * DSP-BIOS Bridge driver support functions for TI OMAP processors. 5 * 6 * Global CFG constants and types, shared between DSP API and Bridge driver. 7 * 8 * Copyright (C) 2005-2006 Texas Instruments, Inc. 9 * 10 * This package is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 17 */ 18 19 #ifndef CFGDEFS_ 20 #define CFGDEFS_ 21 22 /* Host Resources: */ 23 #define CFG_MAXMEMREGISTERS 9 24 25 /* IRQ flag */ 26 #define CFG_IRQSHARED 0x01 /* IRQ can be shared */ 27 28 /* A platform-related device handle: */ 29 struct cfg_devnode; 30 31 /* 32 * Host resource structure. 33 */ 34 struct cfg_hostres { 35 u32 num_mem_windows; /* Set to default */ 36 /* This is the base.memory */ 37 u32 mem_base[CFG_MAXMEMREGISTERS]; /* shm virtual address */ 38 u32 mem_length[CFG_MAXMEMREGISTERS]; /* Length of the Base */ 39 u32 mem_phys[CFG_MAXMEMREGISTERS]; /* shm Physical address */ 40 u8 birq_registers; /* IRQ Number */ 41 u8 birq_attrib; /* IRQ Attribute */ 42 u32 offset_for_monitor; /* The Shared memory starts from 43 * mem_base + this offset */ 44 /* 45 * Info needed by NODE for allocating channels to communicate with RMS: 46 * chnl_offset: Offset of RMS channels. Lower channels are 47 * reserved. 48 * chnl_buf_size: Size of channel buffer to send to RMS 49 * num_chnls: Total number of channels 50 * (including reserved). 51 */ 52 u32 chnl_offset; 53 u32 chnl_buf_size; 54 u32 num_chnls; 55 void __iomem *per_base; 56 u32 per_pm_base; 57 u32 core_pm_base; 58 void __iomem *dmmu_base; 59 }; 60 61 #endif /* CFGDEFS_ */ 62