1 /*
2  *  linux/arch/h8300/kernel/timer/tpu.c
3  *
4  *  Yoshinori Sato <ysato@users.sourceforge.jp>
5  *
6  *  TPU Timer Handler
7  *
8  */
9 
10 #include <linux/errno.h>
11 #include <linux/sched.h>
12 #include <linux/kernel.h>
13 #include <linux/param.h>
14 #include <linux/string.h>
15 #include <linux/mm.h>
16 #include <linux/interrupt.h>
17 #include <linux/init.h>
18 #include <linux/timex.h>
19 
20 #include <asm/segment.h>
21 #include <asm/io.h>
22 #include <asm/irq.h>
23 #include <asm/regs267x.h>
24 
25 /* TPU */
26 #if CONFIG_H8300_TPU_CH == 0
27 #define TPUBASE	0xffffd0
28 #define TPUIRQ	40
29 #elif CONFIG_H8300_TPU_CH == 1
30 #define TPUBASE	0xffffe0
31 #define TPUIRQ	48
32 #elif CONFIG_H8300_TPU_CH == 2
33 #define TPUBASE	0xfffff0
34 #define TPUIRQ	52
35 #elif CONFIG_H8300_TPU_CH == 3
36 #define TPUBASE	0xfffe80
37 #define TPUIRQ	56
38 #elif CONFIG_H8300_TPU_CH == 4
39 #define TPUBASE	0xfffe90
40 #define TPUIRQ	64
41 #else
42 #error Unknown timer channel.
43 #endif
44 
45 #define _TCR	0
46 #define _TMDR	1
47 #define _TIOR	2
48 #define _TIER	4
49 #define _TSR	5
50 #define _TCNT	6
51 #define _GRA	8
52 #define _GRB	10
53 
54 #define CCLR0	0x20
55 
timer_interrupt(int irq,void * dev_id)56 static irqreturn_t timer_interrupt(int irq, void *dev_id)
57 {
58 	h8300_timer_tick();
59 	ctrl_bclr(0, TPUBASE + _TSR);
60 	return IRQ_HANDLED;
61 }
62 
63 static struct irqaction tpu_irq = {
64 	.name		= "tpu",
65 	.handler	= timer_interrupt,
66 	.flags		= IRQF_DISABLED | IRQF_TIMER,
67 };
68 
69 static const int __initdata divide_rate[] = {
70 #if CONFIG_H8300_TPU_CH == 0
71 	1,4,16,64,0,0,0,0,
72 #elif (CONFIG_H8300_TPU_CH == 1) || (CONFIG_H8300_TPU_CH == 5)
73 	1,4,16,64,0,0,256,0,
74 #elif (CONFIG_H8300_TPU_CH == 2) || (CONFIG_H8300_TPU_CH == 4)
75 	1,4,16,64,0,0,0,1024,
76 #elif CONFIG_H8300_TPU_CH == 3
77 	1,4,16,64,0,1024,256,4096,
78 #endif
79 };
80 
h8300_timer_setup(void)81 void __init h8300_timer_setup(void)
82 {
83 	unsigned int cnt;
84 	unsigned int div;
85 
86 	calc_param(cnt, div, divide_rate, 0x10000);
87 
88 	setup_irq(TPUIRQ, &tpu_irq);
89 
90 	/* TPU module enabled */
91 	ctrl_bclr(3, MSTPCRH);
92 
93 	ctrl_outb(0, TSTR);
94 	ctrl_outb(CCLR0 | div, TPUBASE + _TCR);
95 	ctrl_outb(0, TPUBASE + _TMDR);
96 	ctrl_outw(0, TPUBASE + _TIOR);
97 	ctrl_outb(0x01, TPUBASE + _TIER);
98 	ctrl_outw(cnt, TPUBASE + _GRA);
99 	ctrl_bset(CONFIG_H8300_TPU_CH, TSTR);
100 }
101