1 /******************************************************************************* 2 3 4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 2 of the License, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 59 18 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 20 The full GNU General Public License is included in this distribution in the 21 file called LICENSE. 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 *******************************************************************************/ 27 28 #ifndef _E100_CONFIG_INC_ 29 #define _E100_CONFIG_INC_ 30 31 #include "e100.h" 32 33 #define E100_CONFIG(bdp, X) ((bdp)->config[0] = max_t(u8, (bdp)->config[0], (X)+1)) 34 35 #define CB_CFIG_MIN_PARAMS 8 36 37 /* byte 0 bit definitions*/ 38 #define CB_CFIG_BYTE_COUNT_MASK BIT_0_5 /* Byte count occupies bit 5-0 */ 39 40 /* byte 1 bit definitions*/ 41 #define CB_CFIG_RXFIFO_LIMIT_MASK BIT_0_4 /* RxFifo limit mask */ 42 #define CB_CFIG_TXFIFO_LIMIT_MASK BIT_4_7 /* TxFifo limit mask */ 43 44 /* byte 2 bit definitions -- ADAPTIVE_IFS*/ 45 46 /* word 3 bit definitions -- RESERVED*/ 47 /* Changed for 82558 enhancements */ 48 /* byte 3 bit definitions */ 49 #define CB_CFIG_MWI_EN BIT_0 /* Enable MWI on PCI bus */ 50 #define CB_CFIG_TYPE_EN BIT_1 /* Type Enable */ 51 #define CB_CFIG_READAL_EN BIT_2 /* Enable Read Align */ 52 #define CB_CFIG_TERMCL_EN BIT_3 /* Cache line write */ 53 54 /* byte 4 bit definitions*/ 55 #define CB_CFIG_RX_MIN_DMA_MASK BIT_0_6 /* Rx minimum DMA count mask */ 56 57 /* byte 5 bit definitions*/ 58 #define CB_CFIG_TX_MIN_DMA_MASK BIT_0_6 /* Tx minimum DMA count mask */ 59 #define CB_CFIG_DMBC_EN BIT_7 /* Enable Tx/Rx min. DMA counts */ 60 61 /* Changed for 82558 enhancements */ 62 /* byte 6 bit definitions*/ 63 #define CB_CFIG_LATE_SCB BIT_0 /* Update SCB After New Tx Start */ 64 #define CB_CFIG_DIRECT_DMA_DIS BIT_1 /* Direct DMA mode */ 65 #define CB_CFIG_TNO_INT BIT_2 /* Tx Not OK Interrupt */ 66 #define CB_CFIG_TCO_STAT BIT_2 /* TCO statistics in 559 and above */ 67 #define CB_CFIG_CI_INT BIT_3 /* Command Complete Interrupt */ 68 #define CB_CFIG_EXT_TCB_DIS BIT_4 /* Extended TCB */ 69 #define CB_CFIG_EXT_STAT_DIS BIT_5 /* Extended Stats */ 70 #define CB_CFIG_SAVE_BAD_FRAMES BIT_7 /* Save Bad Frames Enabled */ 71 72 /* byte 7 bit definitions*/ 73 #define CB_CFIG_DISC_SHORT_FRAMES BIT_0 /* Discard Short Frames */ 74 #define CB_CFIG_DYNTBD_EN BIT_7 /* Enable dynamic TBD */ 75 /* Enable extended RFD's on D102 */ 76 #define CB_CFIG_EXTENDED_RFD BIT_5 77 78 /* byte 8 bit definitions*/ 79 #define CB_CFIG_503_MII BIT_0 /* 503 vs. MII mode */ 80 81 /* byte 9 bit definitions -- pre-defined all zeros*/ 82 #define CB_LINK_STATUS_WOL BIT_5 83 84 /* byte 10 bit definitions*/ 85 #define CB_CFIG_NO_SRCADR BIT_3 /* No Source Address Insertion */ 86 #define CB_CFIG_PREAMBLE_LEN BIT_4_5 /* Preamble Length */ 87 #define CB_CFIG_LOOPBACK_MODE BIT_6_7 /* Loopback Mode */ 88 #define CB_CFIG_LOOPBACK_NORMAL 0 89 #define CB_CFIG_LOOPBACK_INTERNAL BIT_6 90 #define CB_CFIG_LOOPBACK_EXTERNAL BIT_6_7 91 92 /* byte 11 bit definitions*/ 93 #define CB_CFIG_LINEAR_PRIORITY BIT_0_2 /* Linear Priority */ 94 95 /* byte 12 bit definitions*/ 96 #define CB_CFIG_LINEAR_PRI_MODE BIT_0 /* Linear Priority mode */ 97 #define CB_CFIG_IFS_MASK BIT_4_7 /* Interframe Spacing mask */ 98 99 /* byte 13 bit definitions -- pre-defined all zeros*/ 100 101 /* byte 14 bit definitions -- pre-defined 0xf2*/ 102 103 /* byte 15 bit definitions*/ 104 #define CB_CFIG_PROMISCUOUS BIT_0 /* Promiscuous Mode Enable */ 105 #define CB_CFIG_BROADCAST_DIS BIT_1 /* Broadcast Mode Disable */ 106 #define CB_CFIG_CRS_OR_CDT BIT_7 /* CRS Or CDT */ 107 108 /* byte 16 bit definitions -- pre-defined all zeros*/ 109 #define DFLT_FC_DELAY_LSB 0x1f /* Delay for outgoing Pause frames */ 110 #define DFLT_NO_FC_DELAY_LSB 0x00 /* no flow control default value */ 111 112 /* byte 17 bit definitions -- pre-defined 0x40*/ 113 #define DFLT_FC_DELAY_MSB 0x01 /* Delay for outgoing Pause frames */ 114 #define DFLT_NO_FC_DELAY_MSB 0x40 /* no flow control default value */ 115 116 /* byte 18 bit definitions*/ 117 #define CB_CFIG_STRIPPING BIT_0 /* Padding Disabled */ 118 #define CB_CFIG_PADDING BIT_1 /* Padding Disabled */ 119 #define CB_CFIG_CRC_IN_MEM BIT_2 /* Transfer CRC To Memory */ 120 121 /* byte 19 bit definitions*/ 122 #define CB_CFIG_TX_ADDR_WAKE BIT_0 /* Address Wakeup */ 123 #define CB_DISABLE_MAGPAK_WAKE BIT_1 /* Magic Packet Wakeup disable */ 124 /* Changed TX_FC_EN to TX_FC_DIS because 0 enables, 1 disables. Jul 8, 1999 */ 125 #define CB_CFIG_TX_FC_DIS BIT_2 /* Tx Flow Control Disable */ 126 #define CB_CFIG_FC_RESTOP BIT_3 /* Rx Flow Control Restop */ 127 #define CB_CFIG_FC_RESTART BIT_4 /* Rx Flow Control Restart */ 128 #define CB_CFIG_FC_REJECT BIT_5 /* Rx Flow Control Restart */ 129 #define CB_CFIG_FC_OPTS (CB_CFIG_FC_RESTOP | CB_CFIG_FC_RESTART | CB_CFIG_FC_REJECT) 130 131 /* end 82558/9 specifics */ 132 133 #define CB_CFIG_FORCE_FDX BIT_6 /* Force Full Duplex */ 134 #define CB_CFIG_FDX_ENABLE BIT_7 /* Full Duplex Enabled */ 135 136 /* byte 20 bit definitions*/ 137 #define CB_CFIG_MULTI_IA BIT_6 /* Multiple IA Addr */ 138 139 /* byte 21 bit definitions*/ 140 #define CB_CFIG_MULTICAST_ALL BIT_3 /* Multicast All */ 141 142 /* byte 22 bit defines */ 143 #define CB_CFIG_RECEIVE_GAMLA_MODE BIT_0 /* D102 receive mode */ 144 #define CB_CFIG_VLAN_DROP_ENABLE BIT_1 /* vlan stripping */ 145 146 #define CB_CFIG_LONG_RX_OK BIT_3 147 148 #define NO_LOOPBACK 0 149 #define MAC_LOOPBACK 0x01 150 #define PHY_LOOPBACK 0x02 151 152 /* function prototypes */ 153 extern void e100_config_init(struct e100_private *bdp); 154 extern void e100_config_init_82557(struct e100_private *bdp); 155 extern unsigned char e100_force_config(struct e100_private *bdp); 156 extern unsigned char e100_config(struct e100_private *bdp); 157 extern void e100_config_fc(struct e100_private *bdp); 158 extern void e100_config_promisc(struct e100_private *bdp, unsigned char enable); 159 extern void e100_config_brdcast_dsbl(struct e100_private *bdp); 160 extern void e100_config_mulcast_enbl(struct e100_private *bdp, 161 unsigned char enable); 162 extern void e100_config_ifs(struct e100_private *bdp); 163 extern void e100_config_force_dplx(struct e100_private *bdp); 164 extern u8 e100_config_loopback_mode(struct e100_private *bdp, u8 mode); 165 extern u8 e100_config_dynamic_tbd(struct e100_private *bdp, u8 enable); 166 extern u8 e100_config_tcb_ext_enable(struct e100_private *bdp, u8 enable); 167 extern void e100_config_vlan_drop(struct e100_private *bdp, unsigned char enable); 168 #endif /* _E100_CONFIG_INC_ */ 169