1 /*
2 * Intel i810 and friends ICH driver for Linux
3 * Alan Cox <alan@redhat.com>
4 *
5 * Built from:
6 * Low level code: Zach Brown (original nonworking i810 OSS driver)
7 * Jaroslav Kysela <perex@suse.cz> (working ALSA driver)
8 *
9 * Framework: Thomas Sailer <sailer@ife.ee.ethz.ch>
10 * Extended by: Zach Brown <zab@redhat.com>
11 * and others..
12 *
13 * Hardware Provided By:
14 * Analog Devices (A major AC97 codec maker)
15 * Intel Corp (you've probably heard of them already)
16 *
17 * AC97 clues and assistance provided by
18 * Analog Devices
19 * Zach 'Fufu' Brown
20 * Jeff Garzik
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35 *
36 *
37 * Intel 810 theory of operation
38 *
39 * The chipset provides three DMA channels that talk to an AC97
40 * CODEC (AC97 is a digital/analog mixer standard). At its simplest
41 * you get 48Khz audio with basic volume and mixer controls. At the
42 * best you get rate adaption in the codec. We set the card up so
43 * that we never take completion interrupts but instead keep the card
44 * chasing its tail around a ring buffer. This is needed for mmap
45 * mode audio and happens to work rather well for non-mmap modes too.
46 *
47 * The board has one output channel for PCM audio (supported) and
48 * a stereo line in and mono microphone input. Again these are normally
49 * locked to 48Khz only. Right now recording is not finished.
50 *
51 * There is no midi support, no synth support. Use timidity. To get
52 * esd working you need to use esd -r 48000 as it won't probe 48KHz
53 * by default. mpg123 can't handle 48Khz only audio so use xmms.
54 *
55 * Fix The Sound On Dell
56 *
57 * Not everyone uses 48KHz. We know of no way to detect this reliably
58 * and certainly not to get the right data. If your i810 audio sounds
59 * stupid you may need to investigate other speeds. According to Analog
60 * they tend to use a 14.318MHz clock which gives you a base rate of
61 * 41194Hz.
62 *
63 * This is available via the 'ftsodell=1' option.
64 *
65 * If you need to force a specific rate set the clocking= option
66 *
67 * This driver is cursed. (Ben LaHaise)
68 *
69 * ICH 3 caveats
70 * Intel errata #7 for ICH3 IO. We need to disable SMI stuff
71 * when codec probing. [Not Yet Done]
72 *
73 * ICH 4 caveats
74 *
75 * The ICH4 has the feature, that the codec ID doesn't have to be
76 * congruent with the IO connection.
77 *
78 * Therefore, from driver version 0.23 on, there is a "codec ID" <->
79 * "IO register base offset" mapping (card->ac97_id_map) field.
80 *
81 * Juergen "George" Sawinski (jsaw)
82 */
83
84 #include <linux/module.h>
85 #include <linux/string.h>
86 #include <linux/ctype.h>
87 #include <linux/ioport.h>
88 #include <linux/sched.h>
89 #include <linux/delay.h>
90 #include <linux/sound.h>
91 #include <linux/slab.h>
92 #include <linux/soundcard.h>
93 #include <linux/pci.h>
94 #include <linux/interrupt.h>
95 #include <asm/io.h>
96 #include <asm/dma.h>
97 #include <linux/init.h>
98 #include <linux/poll.h>
99 #include <linux/spinlock.h>
100 #include <linux/smp_lock.h>
101 #include <linux/ac97_codec.h>
102 #include <linux/bitops.h>
103 #include <asm/uaccess.h>
104 #include <asm/hardirq.h>
105
106 #define DRIVER_VERSION "1.01"
107
108 #define MODULOP2(a, b) ((a) & ((b) - 1))
109 #define MASKP2(a, b) ((a) & ~((b) - 1))
110
111 static int ftsodell;
112 static int strict_clocking;
113 static unsigned int clocking;
114 static int spdif_locked;
115
116 //#define DEBUG
117 //#define DEBUG2
118 //#define DEBUG_INTERRUPTS
119 //#define DEBUG_MMAP
120 //#define DEBUG_MMIO
121
122 #define ADC_RUNNING 1
123 #define DAC_RUNNING 2
124
125 #define I810_FMT_16BIT 1
126 #define I810_FMT_STEREO 2
127 #define I810_FMT_MASK 3
128
129 #define SPDIF_ON 0x0004
130 #define SURR_ON 0x0010
131 #define CENTER_LFE_ON 0x0020
132 #define VOL_MUTED 0x8000
133
134 /* the 810's array of pointers to data buffers */
135
136 struct sg_item {
137 #define BUSADDR_MASK 0xFFFFFFFE
138 u32 busaddr;
139 #define CON_IOC 0x80000000 /* interrupt on completion */
140 #define CON_BUFPAD 0x40000000 /* pad underrun with last sample, else 0 */
141 #define CON_BUFLEN_MASK 0x0000ffff /* buffer length in samples */
142 u32 control;
143 };
144
145 /* an instance of the i810 channel */
146 #define SG_LEN 32
147 struct i810_channel
148 {
149 /* these sg guys should probably be allocated
150 separately as nocache. Must be 8 byte aligned */
151 struct sg_item sg[SG_LEN]; /* 32*8 */
152 u32 offset; /* 4 */
153 u32 port; /* 4 */
154 u32 used;
155 u32 num;
156 };
157
158 /*
159 * we have 3 separate dma engines. pcm in, pcm out, and mic.
160 * each dma engine has controlling registers. These goofy
161 * names are from the datasheet, but make it easy to write
162 * code while leafing through it.
163 *
164 * ICH4 has 6 dma engines, pcm in, pcm out, mic, pcm in 2,
165 * mic in 2, s/pdif. Of special interest is the fact that
166 * the upper 3 DMA engines on the ICH4 *must* be accessed
167 * via mmio access instead of pio access.
168 */
169
170 #define ENUM_ENGINE(PRE,DIG) \
171 enum { \
172 PRE##_BASE = 0x##DIG##0, /* Base Address */ \
173 PRE##_BDBAR = 0x##DIG##0, /* Buffer Descriptor list Base Address */ \
174 PRE##_CIV = 0x##DIG##4, /* Current Index Value */ \
175 PRE##_LVI = 0x##DIG##5, /* Last Valid Index */ \
176 PRE##_SR = 0x##DIG##6, /* Status Register */ \
177 PRE##_PICB = 0x##DIG##8, /* Position In Current Buffer */ \
178 PRE##_PIV = 0x##DIG##a, /* Prefetched Index Value */ \
179 PRE##_CR = 0x##DIG##b /* Control Register */ \
180 }
181
182 ENUM_ENGINE(OFF,0); /* Offsets */
183 ENUM_ENGINE(PI,0); /* PCM In */
184 ENUM_ENGINE(PO,1); /* PCM Out */
185 ENUM_ENGINE(MC,2); /* Mic In */
186
187 enum {
188 GLOB_CNT = 0x2c, /* Global Control */
189 GLOB_STA = 0x30, /* Global Status */
190 CAS = 0x34 /* Codec Write Semaphore Register */
191 };
192
193 ENUM_ENGINE(MC2,4); /* Mic In 2 */
194 ENUM_ENGINE(PI2,5); /* PCM In 2 */
195 ENUM_ENGINE(SP,6); /* S/PDIF */
196
197 enum {
198 SDM = 0x80 /* SDATA_IN Map Register */
199 };
200
201 /* interrupts for a dma engine */
202 #define DMA_INT_FIFO (1<<4) /* fifo under/over flow */
203 #define DMA_INT_COMPLETE (1<<3) /* buffer read/write complete and ioc set */
204 #define DMA_INT_LVI (1<<2) /* last valid done */
205 #define DMA_INT_CELV (1<<1) /* last valid is current */
206 #define DMA_INT_DCH (1) /* DMA Controller Halted (happens on LVI interrupts) */
207 #define DMA_INT_MASK (DMA_INT_FIFO|DMA_INT_COMPLETE|DMA_INT_LVI)
208
209 /* interrupts for the whole chip */
210 #define INT_SEC (1<<11)
211 #define INT_PRI (1<<10)
212 #define INT_MC (1<<7)
213 #define INT_PO (1<<6)
214 #define INT_PI (1<<5)
215 #define INT_MO (1<<2)
216 #define INT_NI (1<<1)
217 #define INT_GPI (1<<0)
218 #define INT_MASK (INT_SEC|INT_PRI|INT_MC|INT_PO|INT_PI|INT_MO|INT_NI|INT_GPI)
219
220 /* magic numbers to protect our data structures */
221 #define I810_CARD_MAGIC 0x5072696E /* "Prin" */
222 #define I810_STATE_MAGIC 0x63657373 /* "cess" */
223 #define I810_DMA_MASK 0xffffffff /* DMA buffer mask for pci_alloc_consist */
224 #define NR_HW_CH 3
225
226 /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
227 #define NR_AC97 4
228
229 /* Please note that an 8bit mono stream is not valid on this card, you must have a 16bit */
230 /* stream at a minimum for this card to be happy */
231 static const unsigned sample_size[] = { 1, 2, 2, 4 };
232 /* Samples are 16bit values, so we are shifting to a word, not to a byte, hence shift */
233 /* values are one less than might be expected */
234 static const unsigned sample_shift[] = { -1, 0, 0, 1 };
235
236 enum {
237 ICH82801AA = 0,
238 ICH82901AB,
239 INTEL440MX,
240 INTELICH2,
241 INTELICH3,
242 INTELICH4,
243 INTELICH5,
244 SI7012,
245 NVIDIA_NFORCE,
246 AMD768,
247 AMD8111
248 };
249
250 static char * card_names[] = {
251 "Intel ICH 82801AA",
252 "Intel ICH 82901AB",
253 "Intel 440MX",
254 "Intel ICH2",
255 "Intel ICH3",
256 "Intel ICH4",
257 "Intel ICH5",
258 "SiS 7012",
259 "NVIDIA nForce Audio",
260 "AMD 768",
261 "AMD-8111 IOHub"
262 };
263
264 /* These are capabilities (and bugs) the chipsets _can_ have */
265 static struct {
266 int16_t nr_ac97;
267 #define CAP_MMIO 0x0001
268 #define CAP_20BIT_AUDIO_SUPPORT 0x0002
269 u_int16_t flags;
270 } card_cap[] = {
271 { 1, 0x0000 }, /* ICH82801AA */
272 { 1, 0x0000 }, /* ICH82901AB */
273 { 1, 0x0000 }, /* INTEL440MX */
274 { 1, 0x0000 }, /* INTELICH2 */
275 { 2, 0x0000 }, /* INTELICH3 */
276 { 3, 0x0003 }, /* INTELICH4 */
277 { 3, 0x0003 }, /* INTELICH5 */
278 /*@FIXME to be verified*/ { 2, 0x0000 }, /* SI7012 */
279 /*@FIXME to be verified*/ { 2, 0x0000 }, /* NVIDIA_NFORCE */
280 /*@FIXME to be verified*/ { 2, 0x0000 }, /* AMD768 */
281 /*@FIXME to be verified*/ { 3, 0x0001 }, /* AMD8111 */
282 };
283
284 static struct pci_device_id i810_pci_tbl [] = {
285 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_5,
286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82801AA},
287 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_5,
288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82901AB},
289 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_440MX,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTEL440MX},
291 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_4,
292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH2},
293 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_5,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH3},
295 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_5,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
297 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_5,
298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH5},
299 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7012,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SI7012},
301 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
303 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
305 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO,
306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
307 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP2S_AUDIO,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
309 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO,
310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
311 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_AUDIO,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
313 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP04_AUDIO,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
315 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7445,
316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD768},
317 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_AUDIO,
318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD8111},
319 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_5,
320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
321 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_18,
322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
323
324 {0,}
325 };
326
327 MODULE_DEVICE_TABLE (pci, i810_pci_tbl);
328
329 #ifdef CONFIG_PM
330 #define PM_SUSPENDED(card) (card->pm_suspended)
331 #else
332 #define PM_SUSPENDED(card) (0)
333 #endif
334
335 /* "software" or virtual channel, an instance of opened /dev/dsp */
336 struct i810_state {
337 unsigned int magic;
338 struct i810_card *card; /* Card info */
339
340 /* single open lock mechanism, only used for recording */
341 struct semaphore open_sem;
342 wait_queue_head_t open_wait;
343
344 /* file mode */
345 mode_t open_mode;
346
347 /* virtual channel number */
348 int virt;
349
350 #ifdef CONFIG_PM
351 unsigned int pm_saved_dac_rate,pm_saved_adc_rate;
352 #endif
353 struct dmabuf {
354 /* wave sample stuff */
355 unsigned int rate;
356 unsigned char fmt, enable, trigger;
357
358 /* hardware channel */
359 struct i810_channel *read_channel;
360 struct i810_channel *write_channel;
361
362 /* OSS buffer management stuff */
363 void *rawbuf;
364 dma_addr_t dma_handle;
365 unsigned buforder;
366 unsigned numfrag;
367 unsigned fragshift;
368
369 /* our buffer acts like a circular ring */
370 unsigned hwptr; /* where dma last started, updated by update_ptr */
371 unsigned swptr; /* where driver last clear/filled, updated by read/write */
372 int count; /* bytes to be consumed or been generated by dma machine */
373 unsigned total_bytes; /* total bytes dmaed by hardware */
374
375 unsigned error; /* number of over/underruns */
376 wait_queue_head_t wait; /* put process on wait queue when no more space in buffer */
377
378 /* redundant, but makes calculations easier */
379 /* what the hardware uses */
380 unsigned dmasize;
381 unsigned fragsize;
382 unsigned fragsamples;
383
384 /* what we tell the user to expect */
385 unsigned userfrags;
386 unsigned userfragsize;
387
388 /* OSS stuff */
389 unsigned mapped:1;
390 unsigned ready:1;
391 unsigned update_flag;
392 unsigned ossfragsize;
393 unsigned ossmaxfrags;
394 unsigned subdivision;
395 } dmabuf;
396 };
397
398
399 struct i810_card {
400 unsigned int magic;
401
402 /* We keep i810 cards in a linked list */
403 struct i810_card *next;
404
405 /* The i810 has a certain amount of cross channel interaction
406 so we use a single per card lock */
407 spinlock_t lock;
408
409 /* Control AC97 access serialization */
410 spinlock_t ac97_lock;
411
412 /* PCI device stuff */
413 struct pci_dev * pci_dev;
414 u16 pci_id;
415 u16 pci_id_internal; /* used to access card_cap[] */
416 #ifdef CONFIG_PM
417 u16 pm_suspended;
418 u32 pm_save_state[64/sizeof(u32)];
419 int pm_saved_mixer_settings[SOUND_MIXER_NRDEVICES][NR_AC97];
420 #endif
421 /* soundcore stuff */
422 int dev_audio;
423
424 /* structures for abstraction of hardware facilities, codecs, banks and channels*/
425 u16 ac97_id_map[NR_AC97];
426 struct ac97_codec *ac97_codec[NR_AC97];
427 struct i810_state *states[NR_HW_CH];
428 struct i810_channel *channel; /* 1:1 to states[] but diff. lifetime */
429 dma_addr_t chandma;
430
431 u16 ac97_features;
432 u16 ac97_status;
433 u16 channels;
434
435 /* hardware resources */
436 unsigned long ac97base;
437 unsigned long iobase;
438 u32 irq;
439
440 unsigned long ac97base_mmio_phys;
441 unsigned long iobase_mmio_phys;
442 u_int8_t *ac97base_mmio;
443 u_int8_t *iobase_mmio;
444
445 int use_mmio;
446
447 /* Function support */
448 struct i810_channel *(*alloc_pcm_channel)(struct i810_card *);
449 struct i810_channel *(*alloc_rec_pcm_channel)(struct i810_card *);
450 struct i810_channel *(*alloc_rec_mic_channel)(struct i810_card *);
451 void (*free_pcm_channel)(struct i810_card *, int chan);
452
453 /* We have a *very* long init time possibly, so use this to block */
454 /* attempts to open our devices before we are ready (stops oops'es) */
455 int initializing;
456 };
457
458 /* extract register offset from codec struct */
459 #define IO_REG_OFF(codec) (((struct i810_card *) codec->private_data)->ac97_id_map[codec->id])
460
461 #define I810_IOREAD(size, type, card, off) \
462 ({ \
463 type val; \
464 if (card->use_mmio) \
465 val=read##size(card->iobase_mmio+off); \
466 else \
467 val=in##size(card->iobase+off); \
468 val; \
469 })
470
471 #define I810_IOREADL(card, off) I810_IOREAD(l, u32, card, off)
472 #define I810_IOREADW(card, off) I810_IOREAD(w, u16, card, off)
473 #define I810_IOREADB(card, off) I810_IOREAD(b, u8, card, off)
474
475 #define I810_IOWRITE(size, val, card, off) \
476 ({ \
477 if (card->use_mmio) \
478 write##size(val, card->iobase_mmio+off); \
479 else \
480 out##size(val, card->iobase+off); \
481 })
482
483 #define I810_IOWRITEL(val, card, off) I810_IOWRITE(l, val, card, off)
484 #define I810_IOWRITEW(val, card, off) I810_IOWRITE(w, val, card, off)
485 #define I810_IOWRITEB(val, card, off) I810_IOWRITE(b, val, card, off)
486
487 #define GET_CIV(card, port) MODULOP2(I810_IOREADB((card), (port) + OFF_CIV), SG_LEN)
488 #define GET_LVI(card, port) MODULOP2(I810_IOREADB((card), (port) + OFF_LVI), SG_LEN)
489
490 /* set LVI from CIV */
491 #define CIV_TO_LVI(card, port, off) \
492 I810_IOWRITEB(MODULOP2(GET_CIV((card), (port)) + (off), SG_LEN), (card), (port) + OFF_LVI)
493
494 static struct i810_card *devs = NULL;
495
496 static int i810_open_mixdev(struct inode *inode, struct file *file);
497 static int i810_ioctl_mixdev(struct inode *inode, struct file *file,
498 unsigned int cmd, unsigned long arg);
499 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg);
500 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data);
501 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg);
502 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data);
503 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg);
504 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data);
505
i810_alloc_pcm_channel(struct i810_card * card)506 static struct i810_channel *i810_alloc_pcm_channel(struct i810_card *card)
507 {
508 if(card->channel[1].used==1)
509 return NULL;
510 card->channel[1].used=1;
511 return &card->channel[1];
512 }
513
i810_alloc_rec_pcm_channel(struct i810_card * card)514 static struct i810_channel *i810_alloc_rec_pcm_channel(struct i810_card *card)
515 {
516 if(card->channel[0].used==1)
517 return NULL;
518 card->channel[0].used=1;
519 return &card->channel[0];
520 }
521
i810_alloc_rec_mic_channel(struct i810_card * card)522 static struct i810_channel *i810_alloc_rec_mic_channel(struct i810_card *card)
523 {
524 if(card->channel[2].used==1)
525 return NULL;
526 card->channel[2].used=1;
527 return &card->channel[2];
528 }
529
i810_free_pcm_channel(struct i810_card * card,int channel)530 static void i810_free_pcm_channel(struct i810_card *card, int channel)
531 {
532 card->channel[channel].used=0;
533 }
534
i810_valid_spdif_rate(struct ac97_codec * codec,int rate)535 static int i810_valid_spdif_rate ( struct ac97_codec *codec, int rate )
536 {
537 unsigned long id = 0L;
538
539 id = (i810_ac97_get(codec, AC97_VENDOR_ID1) << 16);
540 id |= i810_ac97_get(codec, AC97_VENDOR_ID2) & 0xffff;
541 #ifdef DEBUG
542 printk ( "i810_audio: codec = %s, codec_id = 0x%08lx\n", codec->name, id);
543 #endif
544 switch ( id ) {
545 case 0x41445361: /* AD1886 */
546 if (rate == 48000) {
547 return 1;
548 }
549 break;
550 default: /* all other codecs, until we know otherwiae */
551 if (rate == 48000 || rate == 44100 || rate == 32000) {
552 return 1;
553 }
554 break;
555 }
556 return (0);
557 }
558
559 /* i810_set_spdif_output
560 *
561 * Configure the S/PDIF output transmitter. When we turn on
562 * S/PDIF, we turn off the analog output. This may not be
563 * the right thing to do.
564 *
565 * Assumptions:
566 * The DSP sample rate must already be set to a supported
567 * S/PDIF rate (32kHz, 44.1kHz, or 48kHz) or we abort.
568 */
i810_set_spdif_output(struct i810_state * state,int slots,int rate)569 static int i810_set_spdif_output(struct i810_state *state, int slots, int rate)
570 {
571 int vol;
572 int aud_reg;
573 int r = 0;
574 struct ac97_codec *codec = state->card->ac97_codec[0];
575
576 if(!codec->codec_ops->digital) {
577 state->card->ac97_status &= ~SPDIF_ON;
578 } else {
579 if ( slots == -1 ) { /* Turn off S/PDIF */
580 codec->codec_ops->digital(codec, 0, 0, 0);
581 /* If the volume wasn't muted before we turned on S/PDIF, unmute it */
582 if ( !(state->card->ac97_status & VOL_MUTED) ) {
583 aud_reg = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
584 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (aud_reg & ~VOL_MUTED));
585 }
586 state->card->ac97_status &= ~(VOL_MUTED | SPDIF_ON);
587 return 0;
588 }
589
590 vol = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
591 state->card->ac97_status = vol & VOL_MUTED;
592
593 r = codec->codec_ops->digital(codec, slots, rate, 0);
594
595 if(r)
596 state->card->ac97_status |= SPDIF_ON;
597 else
598 state->card->ac97_status &= ~SPDIF_ON;
599
600 /* Mute the analog output */
601 /* Should this only mute the PCM volume??? */
602 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (vol | VOL_MUTED));
603 }
604 return r;
605 }
606
607 /* i810_set_dac_channels
608 *
609 * Configure the codec's multi-channel DACs
610 *
611 * The logic is backwards. Setting the bit to 1 turns off the DAC.
612 *
613 * What about the ICH? We currently configure it using the
614 * SNDCTL_DSP_CHANNELS ioctl. If we're turnning on the DAC,
615 * does that imply that we want the ICH set to support
616 * these channels?
617 *
618 * TODO:
619 * vailidate that the codec really supports these DACs
620 * before turning them on.
621 */
i810_set_dac_channels(struct i810_state * state,int channel)622 static void i810_set_dac_channels(struct i810_state *state, int channel)
623 {
624 int aud_reg;
625 struct ac97_codec *codec = state->card->ac97_codec[0];
626
627 /* No codec, no setup */
628
629 if(codec == NULL)
630 return;
631
632 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
633 aud_reg |= AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK;
634 state->card->ac97_status &= ~(SURR_ON | CENTER_LFE_ON);
635
636 switch ( channel ) {
637 case 2: /* always enabled */
638 break;
639 case 4:
640 aud_reg &= ~AC97_EA_PRJ;
641 state->card->ac97_status |= SURR_ON;
642 break;
643 case 6:
644 aud_reg &= ~(AC97_EA_PRJ | AC97_EA_PRI | AC97_EA_PRK);
645 state->card->ac97_status |= SURR_ON | CENTER_LFE_ON;
646 break;
647 default:
648 break;
649 }
650 i810_ac97_set(codec, AC97_EXTENDED_STATUS, aud_reg);
651
652 }
653
654
655 /* set playback sample rate */
i810_set_dac_rate(struct i810_state * state,unsigned int rate)656 static unsigned int i810_set_dac_rate(struct i810_state * state, unsigned int rate)
657 {
658 struct dmabuf *dmabuf = &state->dmabuf;
659 u32 new_rate;
660 struct ac97_codec *codec=state->card->ac97_codec[0];
661
662 if(!(state->card->ac97_features&0x0001))
663 {
664 dmabuf->rate = clocking;
665 #ifdef DEBUG
666 printk("Asked for %d Hz, but ac97_features says we only do %dHz. Sorry!\n",
667 rate,clocking);
668 #endif
669 return clocking;
670 }
671
672 if (rate > 48000)
673 rate = 48000;
674 if (rate < 8000)
675 rate = 8000;
676 dmabuf->rate = rate;
677
678 /*
679 * Adjust for misclocked crap
680 */
681 rate = ( rate * clocking)/48000;
682 if(strict_clocking && rate < 8000) {
683 rate = 8000;
684 dmabuf->rate = (rate * 48000)/clocking;
685 }
686
687 new_rate=ac97_set_dac_rate(codec, rate);
688 if(new_rate != rate) {
689 dmabuf->rate = (new_rate * 48000)/clocking;
690 }
691 #ifdef DEBUG
692 printk("i810_audio: called i810_set_dac_rate : asked for %d, got %d\n", rate, dmabuf->rate);
693 #endif
694 rate = new_rate;
695 return dmabuf->rate;
696 }
697
698 /* set recording sample rate */
i810_set_adc_rate(struct i810_state * state,unsigned int rate)699 static unsigned int i810_set_adc_rate(struct i810_state * state, unsigned int rate)
700 {
701 struct dmabuf *dmabuf = &state->dmabuf;
702 u32 new_rate;
703 struct ac97_codec *codec=state->card->ac97_codec[0];
704
705 if(!(state->card->ac97_features&0x0001))
706 {
707 dmabuf->rate = clocking;
708 return clocking;
709 }
710
711 if (rate > 48000)
712 rate = 48000;
713 if (rate < 8000)
714 rate = 8000;
715 dmabuf->rate = rate;
716
717 /*
718 * Adjust for misclocked crap
719 */
720
721 rate = ( rate * clocking)/48000;
722 if(strict_clocking && rate < 8000) {
723 rate = 8000;
724 dmabuf->rate = (rate * 48000)/clocking;
725 }
726
727 new_rate = ac97_set_adc_rate(codec, rate);
728
729 if(new_rate != rate) {
730 dmabuf->rate = (new_rate * 48000)/clocking;
731 rate = new_rate;
732 }
733 #ifdef DEBUG
734 printk("i810_audio: called i810_set_adc_rate : rate = %d/%d\n", dmabuf->rate, rate);
735 #endif
736 return dmabuf->rate;
737 }
738
739 /* get current playback/recording dma buffer pointer (byte offset from LBA),
740 called with spinlock held! */
741
i810_get_dma_addr(struct i810_state * state,int rec)742 static inline unsigned i810_get_dma_addr(struct i810_state *state, int rec)
743 {
744 struct dmabuf *dmabuf = &state->dmabuf;
745 unsigned int civ, offset, port, port_picb, bytes = 2;
746
747 if (!dmabuf->enable)
748 return 0;
749
750 if (rec)
751 port = dmabuf->read_channel->port;
752 else
753 port = dmabuf->write_channel->port;
754
755 if(state->card->pci_id == PCI_DEVICE_ID_SI_7012) {
756 port_picb = port + OFF_SR;
757 bytes = 1;
758 } else
759 port_picb = port + OFF_PICB;
760
761 do {
762 civ = GET_CIV(state->card, port);
763 offset = I810_IOREADW(state->card, port_picb);
764 /* Must have a delay here! */
765 if(offset == 0)
766 udelay(1);
767 /* Reread both registers and make sure that that total
768 * offset from the first reading to the second is 0.
769 * There is an issue with SiS hardware where it will count
770 * picb down to 0, then update civ to the next value,
771 * then set the new picb to fragsize bytes. We can catch
772 * it between the civ update and the picb update, making
773 * it look as though we are 1 fragsize ahead of where we
774 * are. The next to we get the address though, it will
775 * be back in the right place, and we will suddenly think
776 * we just went forward dmasize - fragsize bytes, causing
777 * totally stupid *huge* dma overrun messages. We are
778 * assuming that the 1us delay is more than long enough
779 * that we won't have to worry about the chip still being
780 * out of sync with reality ;-)
781 */
782 } while (civ != GET_CIV(state->card, port) || offset != I810_IOREADW(state->card, port_picb));
783
784 return (((civ + 1) * dmabuf->fragsize - (bytes * offset))
785 % dmabuf->dmasize);
786 }
787
788 /* Stop recording (lock held) */
__stop_adc(struct i810_state * state)789 static inline void __stop_adc(struct i810_state *state)
790 {
791 struct dmabuf *dmabuf = &state->dmabuf;
792 struct i810_card *card = state->card;
793
794 dmabuf->enable &= ~ADC_RUNNING;
795 I810_IOWRITEB(0, card, PI_CR);
796 // wait for the card to acknowledge shutdown
797 while( I810_IOREADB(card, PI_CR) != 0 ) ;
798 // now clear any latent interrupt bits (like the halt bit)
799 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
800 I810_IOWRITEB( I810_IOREADB(card, PI_PICB), card, PI_PICB );
801 else
802 I810_IOWRITEB( I810_IOREADB(card, PI_SR), card, PI_SR );
803 I810_IOWRITEL( I810_IOREADL(card, GLOB_STA) & INT_PI, card, GLOB_STA);
804 }
805
stop_adc(struct i810_state * state)806 static void stop_adc(struct i810_state *state)
807 {
808 struct i810_card *card = state->card;
809 unsigned long flags;
810
811 spin_lock_irqsave(&card->lock, flags);
812 __stop_adc(state);
813 spin_unlock_irqrestore(&card->lock, flags);
814 }
815
__start_adc(struct i810_state * state)816 static inline void __start_adc(struct i810_state *state)
817 {
818 struct dmabuf *dmabuf = &state->dmabuf;
819
820 if (dmabuf->count < dmabuf->dmasize && dmabuf->ready && !dmabuf->enable &&
821 (dmabuf->trigger & PCM_ENABLE_INPUT)) {
822 dmabuf->enable |= ADC_RUNNING;
823 // Interrupt enable, LVI enable, DMA enable
824 I810_IOWRITEB(0x10 | 0x04 | 0x01, state->card, PI_CR);
825 }
826 }
827
start_adc(struct i810_state * state)828 static void start_adc(struct i810_state *state)
829 {
830 struct i810_card *card = state->card;
831 unsigned long flags;
832
833 spin_lock_irqsave(&card->lock, flags);
834 __start_adc(state);
835 spin_unlock_irqrestore(&card->lock, flags);
836 }
837
838 /* stop playback (lock held) */
__stop_dac(struct i810_state * state)839 static inline void __stop_dac(struct i810_state *state)
840 {
841 struct dmabuf *dmabuf = &state->dmabuf;
842 struct i810_card *card = state->card;
843
844 dmabuf->enable &= ~DAC_RUNNING;
845 I810_IOWRITEB(0, card, PO_CR);
846 // wait for the card to acknowledge shutdown
847 while( I810_IOREADB(card, PO_CR) != 0 ) ;
848 // now clear any latent interrupt bits (like the halt bit)
849 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
850 I810_IOWRITEB( I810_IOREADB(card, PO_PICB), card, PO_PICB );
851 else
852 I810_IOWRITEB( I810_IOREADB(card, PO_SR), card, PO_SR );
853 I810_IOWRITEL( I810_IOREADL(card, GLOB_STA) & INT_PO, card, GLOB_STA);
854 }
855
stop_dac(struct i810_state * state)856 static void stop_dac(struct i810_state *state)
857 {
858 struct i810_card *card = state->card;
859 unsigned long flags;
860
861 spin_lock_irqsave(&card->lock, flags);
862 __stop_dac(state);
863 spin_unlock_irqrestore(&card->lock, flags);
864 }
865
__start_dac(struct i810_state * state)866 static inline void __start_dac(struct i810_state *state)
867 {
868 struct dmabuf *dmabuf = &state->dmabuf;
869
870 if (dmabuf->count > 0 && dmabuf->ready && !dmabuf->enable &&
871 (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
872 dmabuf->enable |= DAC_RUNNING;
873 // Interrupt enable, LVI enable, DMA enable
874 I810_IOWRITEB(0x10 | 0x04 | 0x01, state->card, PO_CR);
875 }
876 }
start_dac(struct i810_state * state)877 static void start_dac(struct i810_state *state)
878 {
879 struct i810_card *card = state->card;
880 unsigned long flags;
881
882 spin_lock_irqsave(&card->lock, flags);
883 __start_dac(state);
884 spin_unlock_irqrestore(&card->lock, flags);
885 }
886
887 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
888 #define DMABUF_MINORDER 1
889
890 /* allocate DMA buffer, playback and recording buffer should be allocated separately */
alloc_dmabuf(struct i810_state * state)891 static int alloc_dmabuf(struct i810_state *state)
892 {
893 struct dmabuf *dmabuf = &state->dmabuf;
894 void *rawbuf= NULL;
895 int order, size;
896 struct page *page, *pend;
897
898 /* If we don't have any oss frag params, then use our default ones */
899 if(dmabuf->ossmaxfrags == 0)
900 dmabuf->ossmaxfrags = 4;
901 if(dmabuf->ossfragsize == 0)
902 dmabuf->ossfragsize = (PAGE_SIZE<<DMABUF_DEFAULTORDER)/dmabuf->ossmaxfrags;
903 size = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
904
905 if(dmabuf->rawbuf && (PAGE_SIZE << dmabuf->buforder) == size)
906 return 0;
907 /* alloc enough to satisfy the oss params */
908 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--) {
909 if ( (PAGE_SIZE<<order) > size )
910 continue;
911 if ((rawbuf = pci_alloc_consistent(state->card->pci_dev,
912 PAGE_SIZE << order,
913 &dmabuf->dma_handle)))
914 break;
915 }
916 if (!rawbuf)
917 return -ENOMEM;
918
919
920 #ifdef DEBUG
921 printk("i810_audio: allocated %ld (order = %d) bytes at %p\n",
922 PAGE_SIZE << order, order, rawbuf);
923 #endif
924
925 dmabuf->ready = dmabuf->mapped = 0;
926 dmabuf->rawbuf = rawbuf;
927 dmabuf->buforder = order;
928
929 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
930 pend = virt_to_page(rawbuf + (PAGE_SIZE << order) - 1);
931 for (page = virt_to_page(rawbuf); page <= pend; page++)
932 SetPageReserved(page);
933
934 return 0;
935 }
936
937 /* free DMA buffer */
dealloc_dmabuf(struct i810_state * state)938 static void dealloc_dmabuf(struct i810_state *state)
939 {
940 struct dmabuf *dmabuf = &state->dmabuf;
941 struct page *page, *pend;
942
943 if (dmabuf->rawbuf) {
944 /* undo marking the pages as reserved */
945 pend = virt_to_page(dmabuf->rawbuf + (PAGE_SIZE << dmabuf->buforder) - 1);
946 for (page = virt_to_page(dmabuf->rawbuf); page <= pend; page++)
947 ClearPageReserved(page);
948 pci_free_consistent(state->card->pci_dev, PAGE_SIZE << dmabuf->buforder,
949 dmabuf->rawbuf, dmabuf->dma_handle);
950 }
951 dmabuf->rawbuf = NULL;
952 dmabuf->mapped = dmabuf->ready = 0;
953 }
954
prog_dmabuf(struct i810_state * state,unsigned rec)955 static int prog_dmabuf(struct i810_state *state, unsigned rec)
956 {
957 struct dmabuf *dmabuf = &state->dmabuf;
958 struct i810_channel *c;
959 struct sg_item *sg;
960 unsigned long flags;
961 int ret;
962 unsigned fragint;
963 int i;
964
965 spin_lock_irqsave(&state->card->lock, flags);
966 if(dmabuf->enable & DAC_RUNNING)
967 __stop_dac(state);
968 if(dmabuf->enable & ADC_RUNNING)
969 __stop_adc(state);
970 dmabuf->total_bytes = 0;
971 dmabuf->count = dmabuf->error = 0;
972 dmabuf->swptr = dmabuf->hwptr = 0;
973 spin_unlock_irqrestore(&state->card->lock, flags);
974
975 /* allocate DMA buffer, let alloc_dmabuf determine if we are already
976 * allocated well enough or if we should replace the current buffer
977 * (assuming one is already allocated, if it isn't, then allocate it).
978 */
979 if ((ret = alloc_dmabuf(state)))
980 return ret;
981
982 /* FIXME: figure out all this OSS fragment stuff */
983 /* I did, it now does what it should according to the OSS API. DL */
984 /* We may not have realloced our dmabuf, but the fragment size to
985 * fragment number ratio may have changed, so go ahead and reprogram
986 * things
987 */
988 dmabuf->dmasize = PAGE_SIZE << dmabuf->buforder;
989 dmabuf->numfrag = SG_LEN;
990 dmabuf->fragsize = dmabuf->dmasize/dmabuf->numfrag;
991 dmabuf->fragsamples = dmabuf->fragsize >> 1;
992 dmabuf->fragshift = ffs(dmabuf->fragsize) - 1;
993 dmabuf->userfragsize = dmabuf->ossfragsize;
994 dmabuf->userfrags = dmabuf->dmasize/dmabuf->ossfragsize;
995
996 memset(dmabuf->rawbuf, 0, dmabuf->dmasize);
997
998 if(dmabuf->ossmaxfrags == 4) {
999 fragint = 8;
1000 } else if (dmabuf->ossmaxfrags == 8) {
1001 fragint = 4;
1002 } else if (dmabuf->ossmaxfrags == 16) {
1003 fragint = 2;
1004 } else {
1005 fragint = 1;
1006 }
1007 /*
1008 * Now set up the ring
1009 */
1010 if(dmabuf->read_channel)
1011 c = dmabuf->read_channel;
1012 else
1013 c = dmabuf->write_channel;
1014 while(c != NULL) {
1015 sg=&c->sg[0];
1016 /*
1017 * Load up 32 sg entries and take an interrupt at half
1018 * way (we might want more interrupts later..)
1019 */
1020
1021 for(i=0;i<dmabuf->numfrag;i++)
1022 {
1023 sg->busaddr=(u32)dmabuf->dma_handle+dmabuf->fragsize*i;
1024 // the card will always be doing 16bit stereo
1025 sg->control=dmabuf->fragsamples;
1026 if(state->card->pci_id == PCI_DEVICE_ID_SI_7012)
1027 sg->control <<= 1;
1028 sg->control|=CON_BUFPAD;
1029 // set us up to get IOC interrupts as often as needed to
1030 // satisfy numfrag requirements, no more
1031 if( ((i+1) % fragint) == 0) {
1032 sg->control|=CON_IOC;
1033 }
1034 sg++;
1035 }
1036 spin_lock_irqsave(&state->card->lock, flags);
1037 I810_IOWRITEB(2, state->card, c->port+OFF_CR); /* reset DMA machine */
1038 while( I810_IOREADB(state->card, c->port+OFF_CR) & 0x02 ) ;
1039 I810_IOWRITEL((u32)state->card->chandma +
1040 c->num*sizeof(struct i810_channel),
1041 state->card, c->port+OFF_BDBAR);
1042 CIV_TO_LVI(state->card, c->port, 0);
1043
1044 spin_unlock_irqrestore(&state->card->lock, flags);
1045
1046 if(c != dmabuf->write_channel)
1047 c = dmabuf->write_channel;
1048 else
1049 c = NULL;
1050 }
1051
1052 /* set the ready flag for the dma buffer */
1053 dmabuf->ready = 1;
1054
1055 #ifdef DEBUG
1056 printk("i810_audio: prog_dmabuf, sample rate = %d, format = %d,\n\tnumfrag = %d, "
1057 "fragsize = %d dmasize = %d\n",
1058 dmabuf->rate, dmabuf->fmt, dmabuf->numfrag,
1059 dmabuf->fragsize, dmabuf->dmasize);
1060 #endif
1061
1062 return 0;
1063 }
1064
__i810_update_lvi(struct i810_state * state,int rec)1065 static void __i810_update_lvi(struct i810_state *state, int rec)
1066 {
1067 struct dmabuf *dmabuf = &state->dmabuf;
1068 int x, port;
1069 int trigger;
1070 int count, fragsize;
1071 void (*start)(struct i810_state *);
1072
1073 count = dmabuf->count;
1074 if (rec) {
1075 port = dmabuf->read_channel->port;
1076 trigger = PCM_ENABLE_INPUT;
1077 start = __start_adc;
1078 count = dmabuf->dmasize - count;
1079 } else {
1080 port = dmabuf->write_channel->port;
1081 trigger = PCM_ENABLE_OUTPUT;
1082 start = __start_dac;
1083 }
1084
1085 /* Do not process partial fragments. */
1086 fragsize = dmabuf->fragsize;
1087 if (count < fragsize)
1088 return;
1089
1090 /* if we are currently stopped, then our CIV is actually set to our
1091 * *last* sg segment and we are ready to wrap to the next. However,
1092 * if we set our LVI to the last sg segment, then it won't wrap to
1093 * the next sg segment, it won't even get a start. So, instead, when
1094 * we are stopped, we set both the LVI value and also we increment
1095 * the CIV value to the next sg segment to be played so that when
1096 * we call start, things will operate properly. Since the CIV can't
1097 * be written to directly for this purpose, we set the LVI to CIV + 1
1098 * temporarily. Once the engine has started we set the LVI to its
1099 * final value.
1100 */
1101 if (!dmabuf->enable && dmabuf->ready) {
1102 if (!(dmabuf->trigger & trigger))
1103 return;
1104
1105 CIV_TO_LVI(state->card, port, 1);
1106
1107 start(state);
1108 while (!(I810_IOREADB(state->card, port + OFF_CR) & ((1<<4) | (1<<2))))
1109 ;
1110 }
1111
1112 /* MASKP2(swptr, fragsize) - 1 is the tail of our transfer */
1113 x = MODULOP2(MASKP2(dmabuf->swptr, fragsize) - 1, dmabuf->dmasize);
1114 x >>= dmabuf->fragshift;
1115 I810_IOWRITEB(x, state->card, port + OFF_LVI);
1116 }
1117
i810_update_lvi(struct i810_state * state,int rec)1118 static void i810_update_lvi(struct i810_state *state, int rec)
1119 {
1120 struct dmabuf *dmabuf = &state->dmabuf;
1121 unsigned long flags;
1122
1123 if(!dmabuf->ready)
1124 return;
1125 spin_lock_irqsave(&state->card->lock, flags);
1126 __i810_update_lvi(state, rec);
1127 spin_unlock_irqrestore(&state->card->lock, flags);
1128 }
1129
1130 /* update buffer manangement pointers, especially, dmabuf->count and dmabuf->hwptr */
i810_update_ptr(struct i810_state * state)1131 static void i810_update_ptr(struct i810_state *state)
1132 {
1133 struct dmabuf *dmabuf = &state->dmabuf;
1134 unsigned hwptr;
1135 unsigned fragmask, dmamask;
1136 int diff;
1137
1138 fragmask = MASKP2(~0, dmabuf->fragsize);
1139 dmamask = MODULOP2(~0, dmabuf->dmasize);
1140
1141 /* error handling and process wake up for ADC */
1142 if (dmabuf->enable == ADC_RUNNING) {
1143 /* update hardware pointer */
1144 hwptr = i810_get_dma_addr(state, 1) & fragmask;
1145 diff = (hwptr - dmabuf->hwptr) & dmamask;
1146 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1147 printk("ADC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1148 #endif
1149 dmabuf->hwptr = hwptr;
1150 dmabuf->total_bytes += diff;
1151 dmabuf->count += diff;
1152 if (dmabuf->count > dmabuf->dmasize) {
1153 /* buffer underrun or buffer overrun */
1154 /* this is normal for the end of a read */
1155 /* only give an error if we went past the */
1156 /* last valid sg entry */
1157 if (GET_CIV(state->card, PI_BASE) !=
1158 GET_LVI(state->card, PI_BASE)) {
1159 printk(KERN_WARNING "i810_audio: DMA overrun on read\n");
1160 dmabuf->error++;
1161 }
1162 }
1163 if (diff)
1164 wake_up(&dmabuf->wait);
1165 }
1166 /* error handling and process wake up for DAC */
1167 if (dmabuf->enable == DAC_RUNNING) {
1168 /* update hardware pointer */
1169 hwptr = i810_get_dma_addr(state, 0) & fragmask;
1170 diff = (hwptr - dmabuf->hwptr) & dmamask;
1171 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1172 printk("DAC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1173 #endif
1174 dmabuf->hwptr = hwptr;
1175 dmabuf->total_bytes += diff;
1176 dmabuf->count -= diff;
1177 if (dmabuf->count < 0) {
1178 /* buffer underrun or buffer overrun */
1179 /* this is normal for the end of a write */
1180 /* only give an error if we went past the */
1181 /* last valid sg entry */
1182 if (GET_CIV(state->card, PO_BASE) !=
1183 GET_LVI(state->card, PO_BASE)) {
1184 printk(KERN_WARNING "i810_audio: DMA overrun on write\n");
1185 printk("i810_audio: CIV %d, LVI %d, hwptr %x, "
1186 "count %d\n",
1187 GET_CIV(state->card, PO_BASE),
1188 GET_LVI(state->card, PO_BASE),
1189 dmabuf->hwptr, dmabuf->count);
1190 dmabuf->error++;
1191 }
1192 }
1193 if (diff)
1194 wake_up(&dmabuf->wait);
1195 }
1196 }
1197
i810_get_free_write_space(struct i810_state * state)1198 static inline int i810_get_free_write_space(struct i810_state *state)
1199 {
1200 struct dmabuf *dmabuf = &state->dmabuf;
1201 int free;
1202
1203 i810_update_ptr(state);
1204 // catch underruns during playback
1205 if (dmabuf->count < 0) {
1206 dmabuf->count = 0;
1207 dmabuf->swptr = dmabuf->hwptr;
1208 }
1209 free = dmabuf->dmasize - dmabuf->count;
1210 if(free < 0)
1211 return(0);
1212 return(free);
1213 }
1214
i810_get_available_read_data(struct i810_state * state)1215 static inline int i810_get_available_read_data(struct i810_state *state)
1216 {
1217 struct dmabuf *dmabuf = &state->dmabuf;
1218 int avail;
1219
1220 i810_update_ptr(state);
1221 // catch overruns during record
1222 if (dmabuf->count > dmabuf->dmasize) {
1223 dmabuf->count = dmabuf->dmasize;
1224 dmabuf->swptr = dmabuf->hwptr;
1225 }
1226 avail = dmabuf->count;
1227 if(avail < 0)
1228 return(0);
1229 return(avail);
1230 }
1231
fill_partial_frag(struct dmabuf * dmabuf)1232 static inline void fill_partial_frag(struct dmabuf *dmabuf)
1233 {
1234 unsigned fragsize;
1235 unsigned swptr, len;
1236
1237 fragsize = dmabuf->fragsize;
1238 swptr = dmabuf->swptr;
1239 len = fragsize - MODULOP2(dmabuf->swptr, fragsize);
1240 if (len == fragsize)
1241 return;
1242
1243 memset(dmabuf->rawbuf + swptr, '\0', len);
1244 dmabuf->swptr = MODULOP2(swptr + len, dmabuf->dmasize);
1245 dmabuf->count += len;
1246 }
1247
drain_dac(struct i810_state * state,int signals_allowed)1248 static int drain_dac(struct i810_state *state, int signals_allowed)
1249 {
1250 DECLARE_WAITQUEUE(wait, current);
1251 struct dmabuf *dmabuf = &state->dmabuf;
1252 unsigned long flags;
1253 unsigned long tmo;
1254 int count;
1255
1256 if (!dmabuf->ready)
1257 return 0;
1258 if(dmabuf->mapped) {
1259 stop_dac(state);
1260 return 0;
1261 }
1262
1263 spin_lock_irqsave(&state->card->lock, flags);
1264
1265 fill_partial_frag(dmabuf);
1266
1267 /*
1268 * This will make sure that our LVI is correct, that our
1269 * pointer is updated, and that the DAC is running. We
1270 * have to force the setting of dmabuf->trigger to avoid
1271 * any possible deadlocks.
1272 */
1273 dmabuf->trigger = PCM_ENABLE_OUTPUT;
1274 __i810_update_lvi(state, 0);
1275
1276 spin_unlock_irqrestore(&state->card->lock, flags);
1277
1278 add_wait_queue(&dmabuf->wait, &wait);
1279 for (;;) {
1280
1281 spin_lock_irqsave(&state->card->lock, flags);
1282 i810_update_ptr(state);
1283 count = dmabuf->count;
1284
1285 /* It seems that we have to set the current state to
1286 * TASK_INTERRUPTIBLE every time to make the process
1287 * really go to sleep. This also has to be *after* the
1288 * update_ptr() call because update_ptr is likely to
1289 * do a wake_up() which will unset this before we ever
1290 * try to sleep, resuling in a tight loop in this code
1291 * instead of actually sleeping and waiting for an
1292 * interrupt to wake us up!
1293 */
1294 __set_current_state(signals_allowed ?
1295 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1296 spin_unlock_irqrestore(&state->card->lock, flags);
1297
1298 if (count <= 0)
1299 break;
1300
1301 if (signal_pending(current) && signals_allowed) {
1302 break;
1303 }
1304
1305 /*
1306 * set the timeout to significantly longer than it *should*
1307 * take for the DAC to drain the DMA buffer
1308 */
1309 tmo = (count * HZ) / (dmabuf->rate);
1310 if (!schedule_timeout(tmo >= 2 ? tmo : 2)){
1311 printk(KERN_ERR "i810_audio: drain_dac, dma timeout?\n");
1312 count = 0;
1313 break;
1314 }
1315 }
1316 set_current_state(TASK_RUNNING);
1317 remove_wait_queue(&dmabuf->wait, &wait);
1318 if(count > 0 && signal_pending(current) && signals_allowed)
1319 return -ERESTARTSYS;
1320 stop_dac(state);
1321 return 0;
1322 }
1323
i810_channel_interrupt(struct i810_card * card)1324 static void i810_channel_interrupt(struct i810_card *card)
1325 {
1326 int i, count;
1327
1328 #ifdef DEBUG_INTERRUPTS
1329 printk("CHANNEL ");
1330 #endif
1331 for(i=0;i<NR_HW_CH;i++)
1332 {
1333 struct i810_state *state = card->states[i];
1334 struct i810_channel *c;
1335 struct dmabuf *dmabuf;
1336 unsigned long port;
1337 u16 status;
1338
1339 if(!state)
1340 continue;
1341 if(!state->dmabuf.ready)
1342 continue;
1343 dmabuf = &state->dmabuf;
1344 if(dmabuf->enable & DAC_RUNNING) {
1345 c=dmabuf->write_channel;
1346 } else if(dmabuf->enable & ADC_RUNNING) {
1347 c=dmabuf->read_channel;
1348 } else /* This can occur going from R/W to close */
1349 continue;
1350
1351 port = c->port;
1352
1353 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1354 status = I810_IOREADW(card, port + OFF_PICB);
1355 else
1356 status = I810_IOREADW(card, port + OFF_SR);
1357
1358 #ifdef DEBUG_INTERRUPTS
1359 printk("NUM %d PORT %X IRQ ( ST%d ", c->num, c->port, status);
1360 #endif
1361 if(status & DMA_INT_COMPLETE)
1362 {
1363 /* only wake_up() waiters if this interrupt signals
1364 * us being beyond a userfragsize of data open or
1365 * available, and i810_update_ptr() does that for
1366 * us
1367 */
1368 i810_update_ptr(state);
1369 #ifdef DEBUG_INTERRUPTS
1370 printk("COMP %d ", dmabuf->hwptr /
1371 dmabuf->fragsize);
1372 #endif
1373 }
1374 if(status & (DMA_INT_LVI | DMA_INT_DCH))
1375 {
1376 /* wake_up() unconditionally on LVI and DCH */
1377 i810_update_ptr(state);
1378 wake_up(&dmabuf->wait);
1379 #ifdef DEBUG_INTERRUPTS
1380 if(status & DMA_INT_LVI)
1381 printk("LVI ");
1382 if(status & DMA_INT_DCH)
1383 printk("DCH -");
1384 #endif
1385 count = dmabuf->count;
1386 if(dmabuf->enable & ADC_RUNNING)
1387 count = dmabuf->dmasize - count;
1388 if (count >= (int)dmabuf->fragsize) {
1389 I810_IOWRITEB(I810_IOREADB(card, port+OFF_CR) | 1, card, port+OFF_CR);
1390 #ifdef DEBUG_INTERRUPTS
1391 printk(" CONTINUE ");
1392 #endif
1393 } else {
1394 if (dmabuf->enable & DAC_RUNNING)
1395 __stop_dac(state);
1396 if (dmabuf->enable & ADC_RUNNING)
1397 __stop_adc(state);
1398 dmabuf->enable = 0;
1399 #ifdef DEBUG_INTERRUPTS
1400 printk(" STOP ");
1401 #endif
1402 }
1403 }
1404 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1405 I810_IOWRITEW(status & DMA_INT_MASK, card, port + OFF_PICB);
1406 else
1407 I810_IOWRITEW(status & DMA_INT_MASK, card, port + OFF_SR);
1408 }
1409 #ifdef DEBUG_INTERRUPTS
1410 printk(")\n");
1411 #endif
1412 }
1413
i810_interrupt(int irq,void * dev_id,struct pt_regs * regs)1414 static irqreturn_t i810_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1415 {
1416 struct i810_card *card = (struct i810_card *)dev_id;
1417 u32 status;
1418
1419 spin_lock(&card->lock);
1420
1421 status = I810_IOREADL(card, GLOB_STA);
1422
1423 if(!(status & INT_MASK))
1424 {
1425 spin_unlock(&card->lock);
1426 return IRQ_NONE; /* not for us */
1427 }
1428
1429 if(status & (INT_PO|INT_PI|INT_MC))
1430 i810_channel_interrupt(card);
1431
1432 /* clear 'em */
1433 I810_IOWRITEL(status & INT_MASK, card, GLOB_STA);
1434 spin_unlock(&card->lock);
1435 return IRQ_HANDLED;
1436 }
1437
1438 /* in this loop, dmabuf.count signifies the amount of data that is
1439 waiting to be copied to the user's buffer. It is filled by the dma
1440 machine and drained by this loop. */
1441
i810_read(struct file * file,char * buffer,size_t count,loff_t * ppos)1442 static ssize_t i810_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1443 {
1444 struct i810_state *state = (struct i810_state *)file->private_data;
1445 struct i810_card *card=state ? state->card : 0;
1446 struct dmabuf *dmabuf = &state->dmabuf;
1447 ssize_t ret;
1448 unsigned long flags;
1449 unsigned int swptr;
1450 int cnt;
1451 int pending;
1452 DECLARE_WAITQUEUE(waita, current);
1453
1454 #ifdef DEBUG2
1455 printk("i810_audio: i810_read called, count = %d\n", count);
1456 #endif
1457
1458 if (ppos != &file->f_pos)
1459 return -ESPIPE;
1460 if (dmabuf->mapped)
1461 return -ENXIO;
1462 if (dmabuf->enable & DAC_RUNNING)
1463 return -ENODEV;
1464 if (!dmabuf->read_channel) {
1465 dmabuf->ready = 0;
1466 dmabuf->read_channel = card->alloc_rec_pcm_channel(card);
1467 if (!dmabuf->read_channel) {
1468 return -EBUSY;
1469 }
1470 }
1471 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
1472 return ret;
1473 if (!access_ok(VERIFY_WRITE, buffer, count))
1474 return -EFAULT;
1475 ret = 0;
1476
1477 pending = 0;
1478
1479 add_wait_queue(&dmabuf->wait, &waita);
1480 while (count > 0) {
1481 set_current_state(TASK_INTERRUPTIBLE);
1482 spin_lock_irqsave(&card->lock, flags);
1483 if (PM_SUSPENDED(card)) {
1484 spin_unlock_irqrestore(&card->lock, flags);
1485 schedule();
1486 if (signal_pending(current)) {
1487 if (!ret) ret = -EAGAIN;
1488 break;
1489 }
1490 continue;
1491 }
1492 cnt = i810_get_available_read_data(state);
1493 swptr = dmabuf->swptr;
1494 // this is to make the copy_to_user simpler below
1495 if(cnt > (dmabuf->dmasize - swptr))
1496 cnt = dmabuf->dmasize - swptr;
1497 spin_unlock_irqrestore(&card->lock, flags);
1498
1499 if (cnt > count)
1500 cnt = count;
1501 if (cnt <= 0) {
1502 unsigned long tmo;
1503 /*
1504 * Don't let us deadlock. The ADC won't start if
1505 * dmabuf->trigger isn't set. A call to SETTRIGGER
1506 * could have turned it off after we set it to on
1507 * previously.
1508 */
1509 dmabuf->trigger = PCM_ENABLE_INPUT;
1510 /*
1511 * This does three things. Updates LVI to be correct,
1512 * makes sure the ADC is running, and updates the
1513 * hwptr.
1514 */
1515 i810_update_lvi(state,1);
1516 if (file->f_flags & O_NONBLOCK) {
1517 if (!ret) ret = -EAGAIN;
1518 goto done;
1519 }
1520 /* Set the timeout to how long it would take to fill
1521 * two of our buffers. If we haven't been woke up
1522 * by then, then we know something is wrong.
1523 */
1524 tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1525 /* There are two situations when sleep_on_timeout returns, one is when
1526 the interrupt is serviced correctly and the process is waked up by
1527 ISR ON TIME. Another is when timeout is expired, which means that
1528 either interrupt is NOT serviced correctly (pending interrupt) or it
1529 is TOO LATE for the process to be scheduled to run (scheduler latency)
1530 which results in a (potential) buffer overrun. And worse, there is
1531 NOTHING we can do to prevent it. */
1532 if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1533 #ifdef DEBUG
1534 printk(KERN_ERR "i810_audio: recording schedule timeout, "
1535 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1536 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1537 dmabuf->hwptr, dmabuf->swptr);
1538 #endif
1539 /* a buffer overrun, we delay the recovery until next time the
1540 while loop begin and we REALLY have space to record */
1541 }
1542 if (signal_pending(current)) {
1543 ret = ret ? ret : -ERESTARTSYS;
1544 goto done;
1545 }
1546 continue;
1547 }
1548
1549 if (copy_to_user(buffer, dmabuf->rawbuf + swptr, cnt)) {
1550 if (!ret) ret = -EFAULT;
1551 goto done;
1552 }
1553
1554 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1555
1556 spin_lock_irqsave(&card->lock, flags);
1557
1558 if (PM_SUSPENDED(card)) {
1559 spin_unlock_irqrestore(&card->lock, flags);
1560 continue;
1561 }
1562 dmabuf->swptr = swptr;
1563 pending = dmabuf->count -= cnt;
1564 spin_unlock_irqrestore(&card->lock, flags);
1565
1566 count -= cnt;
1567 buffer += cnt;
1568 ret += cnt;
1569 }
1570 done:
1571 pending = dmabuf->dmasize - pending;
1572 if (dmabuf->enable || pending >= dmabuf->userfragsize)
1573 i810_update_lvi(state, 1);
1574 set_current_state(TASK_RUNNING);
1575 remove_wait_queue(&dmabuf->wait, &waita);
1576
1577 return ret;
1578 }
1579
1580 /* in this loop, dmabuf.count signifies the amount of data that is waiting to be dma to
1581 the soundcard. it is drained by the dma machine and filled by this loop. */
i810_write(struct file * file,const char * buffer,size_t count,loff_t * ppos)1582 static ssize_t i810_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1583 {
1584 struct i810_state *state = (struct i810_state *)file->private_data;
1585 struct i810_card *card=state ? state->card : 0;
1586 struct dmabuf *dmabuf = &state->dmabuf;
1587 ssize_t ret;
1588 unsigned long flags;
1589 unsigned int swptr = 0;
1590 int pending;
1591 int cnt;
1592 DECLARE_WAITQUEUE(waita, current);
1593
1594 #ifdef DEBUG2
1595 printk("i810_audio: i810_write called, count = %d\n", count);
1596 #endif
1597
1598 if (ppos != &file->f_pos)
1599 return -ESPIPE;
1600 if (dmabuf->mapped)
1601 return -ENXIO;
1602 if (dmabuf->enable & ADC_RUNNING)
1603 return -ENODEV;
1604 if (!dmabuf->write_channel) {
1605 dmabuf->ready = 0;
1606 dmabuf->write_channel = card->alloc_pcm_channel(card);
1607 if(!dmabuf->write_channel)
1608 return -EBUSY;
1609 }
1610 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
1611 return ret;
1612 if (!access_ok(VERIFY_READ, buffer, count))
1613 return -EFAULT;
1614 ret = 0;
1615
1616 pending = 0;
1617
1618 add_wait_queue(&dmabuf->wait, &waita);
1619 while (count > 0) {
1620 set_current_state(TASK_INTERRUPTIBLE);
1621 spin_lock_irqsave(&state->card->lock, flags);
1622 if (PM_SUSPENDED(card)) {
1623 spin_unlock_irqrestore(&card->lock, flags);
1624 schedule();
1625 if (signal_pending(current)) {
1626 if (!ret) ret = -EAGAIN;
1627 break;
1628 }
1629 continue;
1630 }
1631
1632 cnt = i810_get_free_write_space(state);
1633 swptr = dmabuf->swptr;
1634 /* Bound the maximum size to how much we can copy to the
1635 * dma buffer before we hit the end. If we have more to
1636 * copy then it will get done in a second pass of this
1637 * loop starting from the beginning of the buffer.
1638 */
1639 if(cnt > (dmabuf->dmasize - swptr))
1640 cnt = dmabuf->dmasize - swptr;
1641 spin_unlock_irqrestore(&state->card->lock, flags);
1642
1643 #ifdef DEBUG2
1644 printk(KERN_INFO "i810_audio: i810_write: %d bytes available space\n", cnt);
1645 #endif
1646 if (cnt > count)
1647 cnt = count;
1648 if (cnt <= 0) {
1649 unsigned long tmo;
1650 // There is data waiting to be played
1651 /*
1652 * Force the trigger setting since we would
1653 * deadlock with it set any other way
1654 */
1655 dmabuf->trigger = PCM_ENABLE_OUTPUT;
1656 i810_update_lvi(state,0);
1657 if (file->f_flags & O_NONBLOCK) {
1658 if (!ret) ret = -EAGAIN;
1659 goto ret;
1660 }
1661 /* Not strictly correct but works */
1662 tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1663 /* There are two situations when sleep_on_timeout returns, one is when
1664 the interrupt is serviced correctly and the process is waked up by
1665 ISR ON TIME. Another is when timeout is expired, which means that
1666 either interrupt is NOT serviced correctly (pending interrupt) or it
1667 is TOO LATE for the process to be scheduled to run (scheduler latency)
1668 which results in a (potential) buffer underrun. And worse, there is
1669 NOTHING we can do to prevent it. */
1670 if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1671 #ifdef DEBUG
1672 printk(KERN_ERR "i810_audio: playback schedule timeout, "
1673 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1674 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1675 dmabuf->hwptr, dmabuf->swptr);
1676 #endif
1677 /* a buffer underrun, we delay the recovery until next time the
1678 while loop begin and we REALLY have data to play */
1679 //return ret;
1680 }
1681 if (signal_pending(current)) {
1682 if (!ret) ret = -ERESTARTSYS;
1683 goto ret;
1684 }
1685 continue;
1686 }
1687 if (copy_from_user(dmabuf->rawbuf+swptr,buffer,cnt)) {
1688 if (!ret) ret = -EFAULT;
1689 goto ret;
1690 }
1691
1692 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1693
1694 spin_lock_irqsave(&state->card->lock, flags);
1695 if (PM_SUSPENDED(card)) {
1696 spin_unlock_irqrestore(&card->lock, flags);
1697 continue;
1698 }
1699
1700 dmabuf->swptr = swptr;
1701 pending = dmabuf->count += cnt;
1702
1703 count -= cnt;
1704 buffer += cnt;
1705 ret += cnt;
1706 spin_unlock_irqrestore(&state->card->lock, flags);
1707 }
1708 ret:
1709 if (dmabuf->enable || pending >= dmabuf->userfragsize)
1710 i810_update_lvi(state, 0);
1711 set_current_state(TASK_RUNNING);
1712 remove_wait_queue(&dmabuf->wait, &waita);
1713
1714 return ret;
1715 }
1716
1717 /* No kernel lock - we have our own spinlock */
i810_poll(struct file * file,struct poll_table_struct * wait)1718 static unsigned int i810_poll(struct file *file, struct poll_table_struct *wait)
1719 {
1720 struct i810_state *state = (struct i810_state *)file->private_data;
1721 struct dmabuf *dmabuf = &state->dmabuf;
1722 unsigned long flags;
1723 unsigned int mask = 0;
1724
1725 if(!dmabuf->ready)
1726 return 0;
1727 poll_wait(file, &dmabuf->wait, wait);
1728 spin_lock_irqsave(&state->card->lock, flags);
1729 if (dmabuf->enable & ADC_RUNNING ||
1730 dmabuf->trigger & PCM_ENABLE_INPUT) {
1731 if (i810_get_available_read_data(state) >=
1732 (signed)dmabuf->userfragsize)
1733 mask |= POLLIN | POLLRDNORM;
1734 }
1735 if (dmabuf->enable & DAC_RUNNING ||
1736 dmabuf->trigger & PCM_ENABLE_OUTPUT) {
1737 if (i810_get_free_write_space(state) >=
1738 (signed)dmabuf->userfragsize)
1739 mask |= POLLOUT | POLLWRNORM;
1740 }
1741 spin_unlock_irqrestore(&state->card->lock, flags);
1742 return mask;
1743 }
1744
i810_mmap(struct file * file,struct vm_area_struct * vma)1745 static int i810_mmap(struct file *file, struct vm_area_struct *vma)
1746 {
1747 struct i810_state *state = (struct i810_state *)file->private_data;
1748 struct dmabuf *dmabuf = &state->dmabuf;
1749 int ret = -EINVAL;
1750 unsigned long size;
1751
1752 lock_kernel();
1753 if (vma->vm_flags & VM_WRITE) {
1754 if (!dmabuf->write_channel &&
1755 (dmabuf->write_channel =
1756 state->card->alloc_pcm_channel(state->card)) == NULL) {
1757 ret = -EBUSY;
1758 goto out;
1759 }
1760 }
1761 if (vma->vm_flags & VM_READ) {
1762 if (!dmabuf->read_channel &&
1763 (dmabuf->read_channel =
1764 state->card->alloc_rec_pcm_channel(state->card)) == NULL) {
1765 ret = -EBUSY;
1766 goto out;
1767 }
1768 }
1769 if ((ret = prog_dmabuf(state, 0)) != 0)
1770 goto out;
1771
1772 ret = -EINVAL;
1773 if (vma->vm_pgoff != 0)
1774 goto out;
1775 size = vma->vm_end - vma->vm_start;
1776 if (size > (PAGE_SIZE << dmabuf->buforder))
1777 goto out;
1778 ret = -EAGAIN;
1779 if (remap_page_range(vma->vm_start, virt_to_phys(dmabuf->rawbuf),
1780 size, vma->vm_page_prot))
1781 goto out;
1782 dmabuf->mapped = 1;
1783 dmabuf->trigger = 0;
1784 ret = 0;
1785 #ifdef DEBUG_MMAP
1786 printk("i810_audio: mmap'ed %ld bytes of data space\n", size);
1787 #endif
1788 out:
1789 unlock_kernel();
1790 return ret;
1791 }
1792
i810_ioctl(struct inode * inode,struct file * file,unsigned int cmd,unsigned long arg)1793 static int i810_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1794 {
1795 struct i810_state *state = (struct i810_state *)file->private_data;
1796 struct i810_channel *c = NULL;
1797 struct dmabuf *dmabuf = &state->dmabuf;
1798 unsigned long flags;
1799 audio_buf_info abinfo;
1800 count_info cinfo;
1801 unsigned int i_glob_cnt;
1802 int val = 0, ret;
1803 struct ac97_codec *codec = state->card->ac97_codec[0];
1804
1805 #ifdef DEBUG
1806 printk("i810_audio: i810_ioctl, arg=0x%x, cmd=", arg ? *(int *)arg : 0);
1807 #endif
1808
1809 switch (cmd)
1810 {
1811 case OSS_GETVERSION:
1812 #ifdef DEBUG
1813 printk("OSS_GETVERSION\n");
1814 #endif
1815 return put_user(SOUND_VERSION, (int *)arg);
1816
1817 case SNDCTL_DSP_RESET:
1818 #ifdef DEBUG
1819 printk("SNDCTL_DSP_RESET\n");
1820 #endif
1821 spin_lock_irqsave(&state->card->lock, flags);
1822 if (dmabuf->enable == DAC_RUNNING) {
1823 c = dmabuf->write_channel;
1824 __stop_dac(state);
1825 }
1826 if (dmabuf->enable == ADC_RUNNING) {
1827 c = dmabuf->read_channel;
1828 __stop_adc(state);
1829 }
1830 if (c != NULL) {
1831 I810_IOWRITEB(2, state->card, c->port+OFF_CR); /* reset DMA machine */
1832 while ( I810_IOREADB(state->card, c->port+OFF_CR) & 2 )
1833 cpu_relax();
1834 I810_IOWRITEL((u32)state->card->chandma +
1835 c->num*sizeof(struct i810_channel),
1836 state->card, c->port+OFF_BDBAR);
1837 CIV_TO_LVI(state->card, c->port, 0);
1838 }
1839
1840 spin_unlock_irqrestore(&state->card->lock, flags);
1841 synchronize_irq();
1842 dmabuf->ready = 0;
1843 dmabuf->swptr = dmabuf->hwptr = 0;
1844 dmabuf->count = dmabuf->total_bytes = 0;
1845 return 0;
1846
1847 case SNDCTL_DSP_SYNC:
1848 #ifdef DEBUG
1849 printk("SNDCTL_DSP_SYNC\n");
1850 #endif
1851 if (dmabuf->enable != DAC_RUNNING || file->f_flags & O_NONBLOCK)
1852 return 0;
1853 if((val = drain_dac(state, 1)))
1854 return val;
1855 dmabuf->total_bytes = 0;
1856 return 0;
1857
1858 case SNDCTL_DSP_SPEED: /* set smaple rate */
1859 #ifdef DEBUG
1860 printk("SNDCTL_DSP_SPEED\n");
1861 #endif
1862 if (get_user(val, (int *)arg))
1863 return -EFAULT;
1864 if (val >= 0) {
1865 if (file->f_mode & FMODE_WRITE) {
1866 if ( (state->card->ac97_status & SPDIF_ON) ) { /* S/PDIF Enabled */
1867 /* AD1886 only supports 48000, need to check that */
1868 if ( i810_valid_spdif_rate ( codec, val ) ) {
1869 /* Set DAC rate */
1870 i810_set_spdif_output ( state, -1, 0 );
1871 stop_dac(state);
1872 dmabuf->ready = 0;
1873 spin_lock_irqsave(&state->card->lock, flags);
1874 i810_set_dac_rate(state, val);
1875 spin_unlock_irqrestore(&state->card->lock, flags);
1876 /* Set S/PDIF transmitter rate. */
1877 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, val );
1878 if ( ! (state->card->ac97_status & SPDIF_ON) ) {
1879 val = dmabuf->rate;
1880 }
1881 } else { /* Not a valid rate for S/PDIF, ignore it */
1882 val = dmabuf->rate;
1883 }
1884 } else {
1885 stop_dac(state);
1886 dmabuf->ready = 0;
1887 spin_lock_irqsave(&state->card->lock, flags);
1888 i810_set_dac_rate(state, val);
1889 spin_unlock_irqrestore(&state->card->lock, flags);
1890 }
1891 }
1892 if (file->f_mode & FMODE_READ) {
1893 stop_adc(state);
1894 dmabuf->ready = 0;
1895 spin_lock_irqsave(&state->card->lock, flags);
1896 i810_set_adc_rate(state, val);
1897 spin_unlock_irqrestore(&state->card->lock, flags);
1898 }
1899 }
1900 return put_user(dmabuf->rate, (int *)arg);
1901
1902 case SNDCTL_DSP_STEREO: /* set stereo or mono channel */
1903 #ifdef DEBUG
1904 printk("SNDCTL_DSP_STEREO\n");
1905 #endif
1906 if (dmabuf->enable & DAC_RUNNING) {
1907 stop_dac(state);
1908 }
1909 if (dmabuf->enable & ADC_RUNNING) {
1910 stop_adc(state);
1911 }
1912 return put_user(1, (int *)arg);
1913
1914 case SNDCTL_DSP_GETBLKSIZE:
1915 if (file->f_mode & FMODE_WRITE) {
1916 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)))
1917 return val;
1918 }
1919 if (file->f_mode & FMODE_READ) {
1920 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)))
1921 return val;
1922 }
1923 #ifdef DEBUG
1924 printk("SNDCTL_DSP_GETBLKSIZE %d\n", dmabuf->userfragsize);
1925 #endif
1926 return put_user(dmabuf->userfragsize, (int *)arg);
1927
1928 case SNDCTL_DSP_GETFMTS: /* Returns a mask of supported sample format*/
1929 #ifdef DEBUG
1930 printk("SNDCTL_DSP_GETFMTS\n");
1931 #endif
1932 return put_user(AFMT_S16_LE, (int *)arg);
1933
1934 case SNDCTL_DSP_SETFMT: /* Select sample format */
1935 #ifdef DEBUG
1936 printk("SNDCTL_DSP_SETFMT\n");
1937 #endif
1938 return put_user(AFMT_S16_LE, (int *)arg);
1939
1940 case SNDCTL_DSP_CHANNELS:
1941 #ifdef DEBUG
1942 printk("SNDCTL_DSP_CHANNELS\n");
1943 #endif
1944 if (get_user(val, (int *)arg))
1945 return -EFAULT;
1946
1947 if (val > 0) {
1948 if (dmabuf->enable & DAC_RUNNING) {
1949 stop_dac(state);
1950 }
1951 if (dmabuf->enable & ADC_RUNNING) {
1952 stop_adc(state);
1953 }
1954 } else {
1955 return put_user(state->card->channels, (int *)arg);
1956 }
1957
1958 /* ICH and ICH0 only support 2 channels */
1959 if ( state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AA_5
1960 || state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AB_5)
1961 return put_user(2, (int *)arg);
1962
1963 /* Multi-channel support was added with ICH2. Bits in */
1964 /* Global Status and Global Control register are now */
1965 /* used to indicate this. */
1966
1967 i_glob_cnt = I810_IOREADL(state->card, GLOB_CNT);
1968
1969 /* Current # of channels enabled */
1970 if ( i_glob_cnt & 0x0100000 )
1971 ret = 4;
1972 else if ( i_glob_cnt & 0x0200000 )
1973 ret = 6;
1974 else
1975 ret = 2;
1976
1977 switch ( val ) {
1978 case 2: /* 2 channels is always supported */
1979 I810_IOWRITEL(i_glob_cnt & 0xffcfffff,
1980 state->card, GLOB_CNT);
1981 /* Do we need to change mixer settings???? */
1982 break;
1983 case 4: /* Supported on some chipsets, better check first */
1984 if ( state->card->channels >= 4 ) {
1985 I810_IOWRITEL((i_glob_cnt & 0xffcfffff) | 0x100000,
1986 state->card, GLOB_CNT);
1987 /* Do we need to change mixer settings??? */
1988 } else {
1989 val = ret;
1990 }
1991 break;
1992 case 6: /* Supported on some chipsets, better check first */
1993 if ( state->card->channels >= 6 ) {
1994 I810_IOWRITEL((i_glob_cnt & 0xffcfffff) | 0x200000,
1995 state->card, GLOB_CNT);
1996 /* Do we need to change mixer settings??? */
1997 } else {
1998 val = ret;
1999 }
2000 break;
2001 default: /* nothing else is ever supported by the chipset */
2002 val = ret;
2003 break;
2004 }
2005
2006 return put_user(val, (int *)arg);
2007
2008 case SNDCTL_DSP_POST: /* the user has sent all data and is notifying us */
2009 /* we update the swptr to the end of the last sg segment then return */
2010 #ifdef DEBUG
2011 printk("SNDCTL_DSP_POST\n");
2012 #endif
2013 if(!dmabuf->ready || (dmabuf->enable != DAC_RUNNING))
2014 return 0;
2015 if((dmabuf->swptr % dmabuf->fragsize) != 0) {
2016 val = dmabuf->fragsize - (dmabuf->swptr % dmabuf->fragsize);
2017 dmabuf->swptr += val;
2018 dmabuf->count += val;
2019 }
2020 return 0;
2021
2022 case SNDCTL_DSP_SUBDIVIDE:
2023 if (dmabuf->subdivision)
2024 return -EINVAL;
2025 if (get_user(val, (int *)arg))
2026 return -EFAULT;
2027 if (val != 1 && val != 2 && val != 4)
2028 return -EINVAL;
2029 #ifdef DEBUG
2030 printk("SNDCTL_DSP_SUBDIVIDE %d\n", val);
2031 #endif
2032 dmabuf->subdivision = val;
2033 dmabuf->ready = 0;
2034 return 0;
2035
2036 case SNDCTL_DSP_SETFRAGMENT:
2037 if (get_user(val, (int *)arg))
2038 return -EFAULT;
2039
2040 dmabuf->ossfragsize = 1<<(val & 0xffff);
2041 dmabuf->ossmaxfrags = (val >> 16) & 0xffff;
2042 if (!dmabuf->ossfragsize || !dmabuf->ossmaxfrags)
2043 return -EINVAL;
2044 /*
2045 * Bound the frag size into our allowed range of 256 - 4096
2046 */
2047 if (dmabuf->ossfragsize < 256)
2048 dmabuf->ossfragsize = 256;
2049 else if (dmabuf->ossfragsize > 4096)
2050 dmabuf->ossfragsize = 4096;
2051 /*
2052 * The numfrags could be something reasonable, or it could
2053 * be 0xffff meaning "Give me as much as possible". So,
2054 * we check the numfrags * fragsize doesn't exceed our
2055 * 64k buffer limit, nor is it less than our 8k minimum.
2056 * If it fails either one of these checks, then adjust the
2057 * number of fragments, not the size of them. It's OK if
2058 * our number of fragments doesn't equal 32 or anything
2059 * like our hardware based number now since we are using
2060 * a different frag count for the hardware. Before we get
2061 * into this though, bound the maxfrags to avoid overflow
2062 * issues. A reasonable bound would be 64k / 256 since our
2063 * maximum buffer size is 64k and our minimum frag size is
2064 * 256. On the other end, our minimum buffer size is 8k and
2065 * our maximum frag size is 4k, so the lower bound should
2066 * be 2.
2067 */
2068
2069 if(dmabuf->ossmaxfrags > 256)
2070 dmabuf->ossmaxfrags = 256;
2071 else if (dmabuf->ossmaxfrags < 2)
2072 dmabuf->ossmaxfrags = 2;
2073
2074 val = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
2075 while (val < 8192) {
2076 val <<= 1;
2077 dmabuf->ossmaxfrags <<= 1;
2078 }
2079 while (val > 65536) {
2080 val >>= 1;
2081 dmabuf->ossmaxfrags >>= 1;
2082 }
2083 dmabuf->ready = 0;
2084 #ifdef DEBUG
2085 printk("SNDCTL_DSP_SETFRAGMENT 0x%x, %d, %d\n", val,
2086 dmabuf->ossfragsize, dmabuf->ossmaxfrags);
2087 #endif
2088
2089 return 0;
2090
2091 case SNDCTL_DSP_GETOSPACE:
2092 if (!(file->f_mode & FMODE_WRITE))
2093 return -EINVAL;
2094 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2095 return val;
2096 spin_lock_irqsave(&state->card->lock, flags);
2097 i810_update_ptr(state);
2098 abinfo.fragsize = dmabuf->userfragsize;
2099 abinfo.fragstotal = dmabuf->userfrags;
2100 if (dmabuf->mapped)
2101 abinfo.bytes = dmabuf->dmasize;
2102 else
2103 abinfo.bytes = i810_get_free_write_space(state);
2104 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2105 spin_unlock_irqrestore(&state->card->lock, flags);
2106 #if defined(DEBUG) || defined(DEBUG_MMAP)
2107 printk("SNDCTL_DSP_GETOSPACE %d, %d, %d, %d\n", abinfo.bytes,
2108 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2109 #endif
2110 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2111
2112 case SNDCTL_DSP_GETOPTR:
2113 if (!(file->f_mode & FMODE_WRITE))
2114 return -EINVAL;
2115 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2116 return val;
2117 spin_lock_irqsave(&state->card->lock, flags);
2118 val = i810_get_free_write_space(state);
2119 cinfo.bytes = dmabuf->total_bytes;
2120 cinfo.ptr = dmabuf->hwptr;
2121 cinfo.blocks = val/dmabuf->userfragsize;
2122 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
2123 dmabuf->count += val;
2124 dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2125 __i810_update_lvi(state, 0);
2126 }
2127 spin_unlock_irqrestore(&state->card->lock, flags);
2128 #if defined(DEBUG) || defined(DEBUG_MMAP)
2129 printk("SNDCTL_DSP_GETOPTR %d, %d, %d, %d\n", cinfo.bytes,
2130 cinfo.blocks, cinfo.ptr, dmabuf->count);
2131 #endif
2132 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2133
2134 case SNDCTL_DSP_GETISPACE:
2135 if (!(file->f_mode & FMODE_READ))
2136 return -EINVAL;
2137 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)) != 0)
2138 return val;
2139 spin_lock_irqsave(&state->card->lock, flags);
2140 abinfo.bytes = i810_get_available_read_data(state);
2141 abinfo.fragsize = dmabuf->userfragsize;
2142 abinfo.fragstotal = dmabuf->userfrags;
2143 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2144 spin_unlock_irqrestore(&state->card->lock, flags);
2145 #if defined(DEBUG) || defined(DEBUG_MMAP)
2146 printk("SNDCTL_DSP_GETISPACE %d, %d, %d, %d\n", abinfo.bytes,
2147 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2148 #endif
2149 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2150
2151 case SNDCTL_DSP_GETIPTR:
2152 if (!(file->f_mode & FMODE_READ))
2153 return -EINVAL;
2154 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2155 return val;
2156 spin_lock_irqsave(&state->card->lock, flags);
2157 val = i810_get_available_read_data(state);
2158 cinfo.bytes = dmabuf->total_bytes;
2159 cinfo.blocks = val/dmabuf->userfragsize;
2160 cinfo.ptr = dmabuf->hwptr;
2161 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_INPUT)) {
2162 dmabuf->count -= val;
2163 dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2164 __i810_update_lvi(state, 1);
2165 }
2166 spin_unlock_irqrestore(&state->card->lock, flags);
2167 #if defined(DEBUG) || defined(DEBUG_MMAP)
2168 printk("SNDCTL_DSP_GETIPTR %d, %d, %d, %d\n", cinfo.bytes,
2169 cinfo.blocks, cinfo.ptr, dmabuf->count);
2170 #endif
2171 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2172
2173 case SNDCTL_DSP_NONBLOCK:
2174 #ifdef DEBUG
2175 printk("SNDCTL_DSP_NONBLOCK\n");
2176 #endif
2177 file->f_flags |= O_NONBLOCK;
2178 return 0;
2179
2180 case SNDCTL_DSP_GETCAPS:
2181 #ifdef DEBUG
2182 printk("SNDCTL_DSP_GETCAPS\n");
2183 #endif
2184 return put_user(DSP_CAP_REALTIME|DSP_CAP_TRIGGER|DSP_CAP_MMAP|DSP_CAP_BIND,
2185 (int *)arg);
2186
2187 case SNDCTL_DSP_GETTRIGGER:
2188 val = 0;
2189 #ifdef DEBUG
2190 printk("SNDCTL_DSP_GETTRIGGER 0x%x\n", dmabuf->trigger);
2191 #endif
2192 return put_user(dmabuf->trigger, (int *)arg);
2193
2194 case SNDCTL_DSP_SETTRIGGER:
2195 if (get_user(val, (int *)arg))
2196 return -EFAULT;
2197 #if defined(DEBUG) || defined(DEBUG_MMAP)
2198 printk("SNDCTL_DSP_SETTRIGGER 0x%x\n", val);
2199 #endif
2200 /* silently ignore invalid PCM_ENABLE_xxx bits,
2201 * like the other drivers do
2202 */
2203 if (!(file->f_mode & FMODE_READ ))
2204 val &= ~PCM_ENABLE_INPUT;
2205 if (!(file->f_mode & FMODE_WRITE ))
2206 val &= ~PCM_ENABLE_OUTPUT;
2207 if((file->f_mode & FMODE_READ) && !(val & PCM_ENABLE_INPUT) && dmabuf->enable == ADC_RUNNING) {
2208 stop_adc(state);
2209 }
2210 if((file->f_mode & FMODE_WRITE) && !(val & PCM_ENABLE_OUTPUT) && dmabuf->enable == DAC_RUNNING) {
2211 stop_dac(state);
2212 }
2213 dmabuf->trigger = val;
2214 if((val & PCM_ENABLE_OUTPUT) && !(dmabuf->enable & DAC_RUNNING)) {
2215 if (!dmabuf->write_channel) {
2216 dmabuf->ready = 0;
2217 dmabuf->write_channel = state->card->alloc_pcm_channel(state->card);
2218 if (!dmabuf->write_channel)
2219 return -EBUSY;
2220 }
2221 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
2222 return ret;
2223 if (dmabuf->mapped) {
2224 spin_lock_irqsave(&state->card->lock, flags);
2225 i810_update_ptr(state);
2226 dmabuf->count = 0;
2227 dmabuf->swptr = dmabuf->hwptr;
2228 dmabuf->count = i810_get_free_write_space(state);
2229 dmabuf->swptr = (dmabuf->swptr + dmabuf->count) % dmabuf->dmasize;
2230 spin_unlock_irqrestore(&state->card->lock, flags);
2231 }
2232 i810_update_lvi(state, 0);
2233 start_dac(state);
2234 }
2235 if((val & PCM_ENABLE_INPUT) && !(dmabuf->enable & ADC_RUNNING)) {
2236 if (!dmabuf->read_channel) {
2237 dmabuf->ready = 0;
2238 dmabuf->read_channel = state->card->alloc_rec_pcm_channel(state->card);
2239 if (!dmabuf->read_channel)
2240 return -EBUSY;
2241 }
2242 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
2243 return ret;
2244 if (dmabuf->mapped) {
2245 spin_lock_irqsave(&state->card->lock, flags);
2246 i810_update_ptr(state);
2247 dmabuf->swptr = dmabuf->hwptr;
2248 dmabuf->count = 0;
2249 spin_unlock_irqrestore(&state->card->lock, flags);
2250 }
2251 i810_update_lvi(state, 1);
2252 start_adc(state);
2253 }
2254 return 0;
2255
2256 case SNDCTL_DSP_SETDUPLEX:
2257 #ifdef DEBUG
2258 printk("SNDCTL_DSP_SETDUPLEX\n");
2259 #endif
2260 return -EINVAL;
2261
2262 case SNDCTL_DSP_GETODELAY:
2263 if (!(file->f_mode & FMODE_WRITE))
2264 return -EINVAL;
2265 spin_lock_irqsave(&state->card->lock, flags);
2266 i810_update_ptr(state);
2267 val = dmabuf->count;
2268 spin_unlock_irqrestore(&state->card->lock, flags);
2269 #ifdef DEBUG
2270 printk("SNDCTL_DSP_GETODELAY %d\n", dmabuf->count);
2271 #endif
2272 return put_user(val, (int *)arg);
2273
2274 case SOUND_PCM_READ_RATE:
2275 #ifdef DEBUG
2276 printk("SOUND_PCM_READ_RATE %d\n", dmabuf->rate);
2277 #endif
2278 return put_user(dmabuf->rate, (int *)arg);
2279
2280 case SOUND_PCM_READ_CHANNELS:
2281 #ifdef DEBUG
2282 printk("SOUND_PCM_READ_CHANNELS\n");
2283 #endif
2284 return put_user(2, (int *)arg);
2285
2286 case SOUND_PCM_READ_BITS:
2287 #ifdef DEBUG
2288 printk("SOUND_PCM_READ_BITS\n");
2289 #endif
2290 return put_user(AFMT_S16_LE, (int *)arg);
2291
2292 case SNDCTL_DSP_SETSPDIF: /* Set S/PDIF Control register */
2293 #ifdef DEBUG
2294 printk("SNDCTL_DSP_SETSPDIF\n");
2295 #endif
2296 if (get_user(val, (int *)arg))
2297 return -EFAULT;
2298
2299 /* Check to make sure the codec supports S/PDIF transmitter */
2300
2301 if((state->card->ac97_features & 4)) {
2302 /* mask out the transmitter speed bits so the user can't set them */
2303 val &= ~0x3000;
2304
2305 /* Add the current transmitter speed bits to the passed value */
2306 ret = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2307 val |= (ret & 0x3000);
2308
2309 i810_ac97_set(codec, AC97_SPDIF_CONTROL, val);
2310 if(i810_ac97_get(codec, AC97_SPDIF_CONTROL) != val ) {
2311 printk(KERN_ERR "i810_audio: Unable to set S/PDIF configuration to 0x%04x.\n", val);
2312 return -EFAULT;
2313 }
2314 }
2315 #ifdef DEBUG
2316 else
2317 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2318 #endif
2319 return put_user(val, (int *)arg);
2320
2321 case SNDCTL_DSP_GETSPDIF: /* Get S/PDIF Control register */
2322 #ifdef DEBUG
2323 printk("SNDCTL_DSP_GETSPDIF\n");
2324 #endif
2325 if (get_user(val, (int *)arg))
2326 return -EFAULT;
2327
2328 /* Check to make sure the codec supports S/PDIF transmitter */
2329
2330 if(!(state->card->ac97_features & 4)) {
2331 #ifdef DEBUG
2332 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2333 #endif
2334 val = 0;
2335 } else {
2336 val = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2337 }
2338 //return put_user((val & 0xcfff), (int *)arg);
2339 return put_user(val, (int *)arg);
2340
2341 case SNDCTL_DSP_GETCHANNELMASK:
2342 #ifdef DEBUG
2343 printk("SNDCTL_DSP_GETCHANNELMASK\n");
2344 #endif
2345 if (get_user(val, (int *)arg))
2346 return -EFAULT;
2347
2348 /* Based on AC'97 DAC support, not ICH hardware */
2349 val = DSP_BIND_FRONT;
2350 if ( state->card->ac97_features & 0x0004 )
2351 val |= DSP_BIND_SPDIF;
2352
2353 if ( state->card->ac97_features & 0x0080 )
2354 val |= DSP_BIND_SURR;
2355 if ( state->card->ac97_features & 0x0140 )
2356 val |= DSP_BIND_CENTER_LFE;
2357
2358 return put_user(val, (int *)arg);
2359
2360 case SNDCTL_DSP_BIND_CHANNEL:
2361 #ifdef DEBUG
2362 printk("SNDCTL_DSP_BIND_CHANNEL\n");
2363 #endif
2364 if (get_user(val, (int *)arg))
2365 return -EFAULT;
2366 if ( val == DSP_BIND_QUERY ) {
2367 val = DSP_BIND_FRONT; /* Always report this as being enabled */
2368 if ( state->card->ac97_status & SPDIF_ON )
2369 val |= DSP_BIND_SPDIF;
2370 else {
2371 if ( state->card->ac97_status & SURR_ON )
2372 val |= DSP_BIND_SURR;
2373 if ( state->card->ac97_status & CENTER_LFE_ON )
2374 val |= DSP_BIND_CENTER_LFE;
2375 }
2376 } else { /* Not a query, set it */
2377 if (!(file->f_mode & FMODE_WRITE))
2378 return -EINVAL;
2379 if ( dmabuf->enable == DAC_RUNNING ) {
2380 stop_dac(state);
2381 }
2382 if ( val & DSP_BIND_SPDIF ) { /* Turn on SPDIF */
2383 /* Ok, this should probably define what slots
2384 * to use. For now, we'll only set it to the
2385 * defaults:
2386 *
2387 * non multichannel codec maps to slots 3&4
2388 * 2 channel codec maps to slots 7&8
2389 * 4 channel codec maps to slots 6&9
2390 * 6 channel codec maps to slots 10&11
2391 *
2392 * there should be some way for the app to
2393 * select the slot assignment.
2394 */
2395
2396 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, dmabuf->rate );
2397 if ( !(state->card->ac97_status & SPDIF_ON) )
2398 val &= ~DSP_BIND_SPDIF;
2399 } else {
2400 int mask;
2401 int channels;
2402
2403 /* Turn off S/PDIF if it was on */
2404 if ( state->card->ac97_status & SPDIF_ON )
2405 i810_set_spdif_output ( state, -1, 0 );
2406
2407 mask = val & (DSP_BIND_FRONT | DSP_BIND_SURR | DSP_BIND_CENTER_LFE);
2408 switch (mask) {
2409 case DSP_BIND_FRONT:
2410 channels = 2;
2411 break;
2412 case DSP_BIND_FRONT|DSP_BIND_SURR:
2413 channels = 4;
2414 break;
2415 case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE:
2416 channels = 6;
2417 break;
2418 default:
2419 val = DSP_BIND_FRONT;
2420 channels = 2;
2421 break;
2422 }
2423 i810_set_dac_channels ( state, channels );
2424
2425 /* check that they really got turned on */
2426 if (!(state->card->ac97_status & SURR_ON))
2427 val &= ~DSP_BIND_SURR;
2428 if (!(state->card->ac97_status & CENTER_LFE_ON))
2429 val &= ~DSP_BIND_CENTER_LFE;
2430 }
2431 }
2432 return put_user(val, (int *)arg);
2433
2434 case SNDCTL_DSP_MAPINBUF:
2435 case SNDCTL_DSP_MAPOUTBUF:
2436 case SNDCTL_DSP_SETSYNCRO:
2437 case SOUND_PCM_WRITE_FILTER:
2438 case SOUND_PCM_READ_FILTER:
2439 #ifdef DEBUG
2440 printk("SNDCTL_* -EINVAL\n");
2441 #endif
2442 return -EINVAL;
2443 }
2444 return -EINVAL;
2445 }
2446
i810_open(struct inode * inode,struct file * file)2447 static int i810_open(struct inode *inode, struct file *file)
2448 {
2449 int i = 0;
2450 struct i810_card *card = devs;
2451 struct i810_state *state = NULL;
2452 struct dmabuf *dmabuf = NULL;
2453
2454 /* find an avaiable virtual channel (instance of /dev/dsp) */
2455 while (card != NULL) {
2456 /*
2457 * If we are initializing and then fail, card could go
2458 * away unuexpectedly while we are in the for() loop.
2459 * So, check for card on each iteration before we check
2460 * for card->initializing to avoid a possible oops.
2461 * This usually only matters for times when the driver is
2462 * autoloaded by kmod.
2463 */
2464 for (i = 0; i < 50 && card && card->initializing; i++) {
2465 set_current_state(TASK_UNINTERRUPTIBLE);
2466 schedule_timeout(HZ/20);
2467 }
2468 for (i = 0; i < NR_HW_CH && card && !card->initializing; i++) {
2469 if (card->states[i] == NULL) {
2470 state = card->states[i] = (struct i810_state *)
2471 kmalloc(sizeof(struct i810_state), GFP_KERNEL);
2472 if (state == NULL)
2473 return -ENOMEM;
2474 memset(state, 0, sizeof(struct i810_state));
2475 dmabuf = &state->dmabuf;
2476 goto found_virt;
2477 }
2478 }
2479 card = card->next;
2480 }
2481 /* no more virtual channel avaiable */
2482 if (!state)
2483 return -ENODEV;
2484
2485 found_virt:
2486 /* initialize the virtual channel */
2487 state->virt = i;
2488 state->card = card;
2489 state->magic = I810_STATE_MAGIC;
2490 init_waitqueue_head(&dmabuf->wait);
2491 init_MUTEX(&state->open_sem);
2492 file->private_data = state;
2493 dmabuf->trigger = 0;
2494
2495 /* allocate hardware channels */
2496 if(file->f_mode & FMODE_READ) {
2497 if((dmabuf->read_channel = card->alloc_rec_pcm_channel(card)) == NULL) {
2498 kfree (card->states[i]);
2499 card->states[i] = NULL;
2500 return -EBUSY;
2501 }
2502 dmabuf->trigger |= PCM_ENABLE_INPUT;
2503 i810_set_adc_rate(state, 8000);
2504 }
2505 if(file->f_mode & FMODE_WRITE) {
2506 if((dmabuf->write_channel = card->alloc_pcm_channel(card)) == NULL) {
2507 /* make sure we free the record channel allocated above */
2508 if(file->f_mode & FMODE_READ)
2509 card->free_pcm_channel(card,dmabuf->read_channel->num);
2510 kfree (card->states[i]);
2511 card->states[i] = NULL;
2512 return -EBUSY;
2513 }
2514 /* Initialize to 8kHz? What if we don't support 8kHz? */
2515 /* Let's change this to check for S/PDIF stuff */
2516
2517 dmabuf->trigger |= PCM_ENABLE_OUTPUT;
2518 if ( spdif_locked ) {
2519 i810_set_dac_rate(state, spdif_locked);
2520 i810_set_spdif_output(state, AC97_EA_SPSA_3_4, spdif_locked);
2521 } else {
2522 i810_set_dac_rate(state, 8000);
2523 /* Put the ACLink in 2 channel mode by default */
2524 i = I810_IOREADL(card, GLOB_CNT);
2525 I810_IOWRITEL(i & 0xffcfffff, card, GLOB_CNT);
2526 }
2527 }
2528
2529 /* set default sample format. According to OSS Programmer's Guide /dev/dsp
2530 should be default to unsigned 8-bits, mono, with sample rate 8kHz and
2531 /dev/dspW will accept 16-bits sample, but we don't support those so we
2532 set it immediately to stereo and 16bit, which is all we do support */
2533 dmabuf->fmt |= I810_FMT_16BIT | I810_FMT_STEREO;
2534 dmabuf->ossfragsize = 0;
2535 dmabuf->ossmaxfrags = 0;
2536 dmabuf->subdivision = 0;
2537
2538 state->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2539
2540 return 0;
2541 }
2542
i810_release(struct inode * inode,struct file * file)2543 static int i810_release(struct inode *inode, struct file *file)
2544 {
2545 struct i810_state *state = (struct i810_state *)file->private_data;
2546 struct i810_card *card = state->card;
2547 struct dmabuf *dmabuf = &state->dmabuf;
2548 unsigned long flags;
2549
2550 lock_kernel();
2551
2552 /* stop DMA state machine and free DMA buffers/channels */
2553 if(dmabuf->trigger & PCM_ENABLE_OUTPUT) {
2554 drain_dac(state, 0);
2555 }
2556 if(dmabuf->trigger & PCM_ENABLE_INPUT) {
2557 stop_adc(state);
2558 }
2559 spin_lock_irqsave(&card->lock, flags);
2560 dealloc_dmabuf(state);
2561 if (file->f_mode & FMODE_WRITE) {
2562 state->card->free_pcm_channel(state->card, dmabuf->write_channel->num);
2563 }
2564 if (file->f_mode & FMODE_READ) {
2565 state->card->free_pcm_channel(state->card, dmabuf->read_channel->num);
2566 }
2567
2568 state->card->states[state->virt] = NULL;
2569 kfree(state);
2570 spin_unlock_irqrestore(&card->lock, flags);
2571 unlock_kernel();
2572
2573 return 0;
2574 }
2575
2576 static /*const*/ struct file_operations i810_audio_fops = {
2577 .owner = THIS_MODULE,
2578 .llseek = no_llseek,
2579 .read = i810_read,
2580 .write = i810_write,
2581 .poll = i810_poll,
2582 .ioctl = i810_ioctl,
2583 .mmap = i810_mmap,
2584 .open = i810_open,
2585 .release = i810_release,
2586 };
2587
2588 /* Write AC97 codec registers */
2589
i810_ac97_get_mmio(struct ac97_codec * dev,u8 reg)2590 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg)
2591 {
2592 struct i810_card *card = dev->private_data;
2593 int count = 100;
2594 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2595
2596 while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2597 udelay(1);
2598
2599 #ifdef DEBUG_MMIO
2600 {
2601 u16 ans = readw(card->ac97base_mmio + reg_set);
2602 printk(KERN_DEBUG "i810_audio: ac97_get_mmio(%d) -> 0x%04X\n", ((int) reg_set) & 0xffff, (u32) ans);
2603 return ans;
2604 }
2605 #else
2606 return readw(card->ac97base_mmio + reg_set);
2607 #endif
2608 }
2609
i810_ac97_get_io(struct ac97_codec * dev,u8 reg)2610 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg)
2611 {
2612 struct i810_card *card = dev->private_data;
2613 int count = 100;
2614 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2615
2616 while(count-- && (I810_IOREADB(card, CAS) & 1))
2617 udelay(1);
2618
2619 return inw(card->ac97base + reg_set);
2620 }
2621
i810_ac97_set_mmio(struct ac97_codec * dev,u8 reg,u16 data)2622 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data)
2623 {
2624 struct i810_card *card = dev->private_data;
2625 int count = 100;
2626 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2627
2628 while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2629 udelay(1);
2630
2631 writew(data, card->ac97base_mmio + reg_set);
2632
2633 #ifdef DEBUG_MMIO
2634 printk(KERN_DEBUG "i810_audio: ac97_set_mmio(0x%04X, %d)\n", (u32) data, ((int) reg_set) & 0xffff);
2635 #endif
2636 }
2637
i810_ac97_set_io(struct ac97_codec * dev,u8 reg,u16 data)2638 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data)
2639 {
2640 struct i810_card *card = dev->private_data;
2641 int count = 100;
2642 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2643
2644 while(count-- && (I810_IOREADB(card, CAS) & 1))
2645 udelay(1);
2646
2647 outw(data, card->ac97base + reg_set);
2648 }
2649
i810_ac97_get(struct ac97_codec * dev,u8 reg)2650 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg)
2651 {
2652 struct i810_card *card = dev->private_data;
2653 u16 ret;
2654
2655 spin_lock(&card->ac97_lock);
2656 if (card->use_mmio) {
2657 ret = i810_ac97_get_mmio(dev, reg);
2658 }
2659 else {
2660 ret = i810_ac97_get_io(dev, reg);
2661 }
2662 spin_unlock(&card->ac97_lock);
2663
2664 return ret;
2665 }
2666
i810_ac97_set(struct ac97_codec * dev,u8 reg,u16 data)2667 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data)
2668 {
2669 struct i810_card *card = dev->private_data;
2670
2671 spin_lock(&card->ac97_lock);
2672 if (card->use_mmio) {
2673 i810_ac97_set_mmio(dev, reg, data);
2674 }
2675 else {
2676 i810_ac97_set_io(dev, reg, data);
2677 }
2678 spin_unlock(&card->ac97_lock);
2679 }
2680
2681
2682 /* OSS /dev/mixer file operation methods */
2683
i810_open_mixdev(struct inode * inode,struct file * file)2684 static int i810_open_mixdev(struct inode *inode, struct file *file)
2685 {
2686 int i;
2687 int minor = MINOR(inode->i_rdev);
2688 struct i810_card *card = devs;
2689
2690 for (card = devs; card != NULL; card = card->next) {
2691 /*
2692 * If we are initializing and then fail, card could go
2693 * away unuexpectedly while we are in the for() loop.
2694 * So, check for card on each iteration before we check
2695 * for card->initializing to avoid a possible oops.
2696 * This usually only matters for times when the driver is
2697 * autoloaded by kmod.
2698 */
2699 for (i = 0; i < 50 && card && card->initializing; i++) {
2700 set_current_state(TASK_UNINTERRUPTIBLE);
2701 schedule_timeout(HZ/20);
2702 }
2703 for (i = 0; i < NR_AC97 && card && !card->initializing; i++)
2704 if (card->ac97_codec[i] != NULL &&
2705 card->ac97_codec[i]->dev_mixer == minor) {
2706 file->private_data = card->ac97_codec[i];
2707 return 0;
2708 }
2709 }
2710 return -ENODEV;
2711 }
2712
i810_ioctl_mixdev(struct inode * inode,struct file * file,unsigned int cmd,unsigned long arg)2713 static int i810_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2714 unsigned long arg)
2715 {
2716 struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2717
2718 return codec->mixer_ioctl(codec, cmd, arg);
2719 }
2720
2721 static /*const*/ struct file_operations i810_mixer_fops = {
2722 .owner = THIS_MODULE,
2723 .llseek = no_llseek,
2724 .ioctl = i810_ioctl_mixdev,
2725 .open = i810_open_mixdev,
2726 };
2727
2728 /* AC97 codec initialisation. These small functions exist so we don't
2729 duplicate code between module init and apm resume */
2730
i810_ac97_exists(struct i810_card * card,int ac97_number)2731 static inline int i810_ac97_exists(struct i810_card *card, int ac97_number)
2732 {
2733 u32 reg = I810_IOREADL(card, GLOB_STA);
2734 switch (ac97_number) {
2735 case 0:
2736 return reg & (1<<8);
2737 case 1:
2738 return reg & (1<<9);
2739 case 2:
2740 return reg & (1<<28);
2741 }
2742 return 0;
2743 }
2744
i810_ac97_enable_variable_rate(struct ac97_codec * codec)2745 static inline int i810_ac97_enable_variable_rate(struct ac97_codec *codec)
2746 {
2747 i810_ac97_set(codec, AC97_EXTENDED_STATUS, 9);
2748 i810_ac97_set(codec,AC97_EXTENDED_STATUS,
2749 i810_ac97_get(codec, AC97_EXTENDED_STATUS)|0xE800);
2750
2751 return (i810_ac97_get(codec, AC97_EXTENDED_STATUS)&1);
2752 }
2753
2754
i810_ac97_probe_and_powerup(struct i810_card * card,struct ac97_codec * codec)2755 static int i810_ac97_probe_and_powerup(struct i810_card *card,struct ac97_codec *codec)
2756 {
2757 /* Returns 0 on failure */
2758 int i;
2759
2760 if (ac97_probe_codec(codec) == 0) return 0;
2761
2762 /* power it all up */
2763 i810_ac97_set(codec, AC97_POWER_CONTROL,
2764 i810_ac97_get(codec, AC97_POWER_CONTROL) & ~0x7f00);
2765
2766 /* wait for analog ready */
2767 for (i=100; i && ((i810_ac97_get(codec, AC97_POWER_CONTROL) & 0xf) != 0xf); i--)
2768 {
2769 set_current_state(TASK_UNINTERRUPTIBLE);
2770 schedule_timeout(HZ/20);
2771 }
2772 return i;
2773 }
2774
is_new_ich(u16 pci_id)2775 static int is_new_ich(u16 pci_id)
2776 {
2777 switch (pci_id) {
2778 case PCI_DEVICE_ID_INTEL_82801DB_5:
2779 case PCI_DEVICE_ID_INTEL_82801EB_5:
2780 case PCI_DEVICE_ID_INTEL_ESB_5:
2781 case PCI_DEVICE_ID_INTEL_ICH6_18:
2782 return 1;
2783 default:
2784 break;
2785 }
2786
2787 return 0;
2788 }
2789
ich_use_mmio(struct i810_card * card)2790 static inline int ich_use_mmio(struct i810_card *card)
2791 {
2792 return is_new_ich(card->pci_id) && card->use_mmio;
2793 }
2794
2795 /**
2796 * i810_ac97_power_up_bus - bring up AC97 link
2797 * @card : ICH audio device to power up
2798 *
2799 * Bring up the ACLink AC97 codec bus
2800 */
2801
i810_ac97_power_up_bus(struct i810_card * card)2802 static int i810_ac97_power_up_bus(struct i810_card *card)
2803 {
2804 u32 reg = I810_IOREADL(card, GLOB_CNT);
2805 int i;
2806 int primary_codec_id = 0;
2807
2808 if((reg&2)==0) /* Cold required */
2809 reg|=2;
2810 else
2811 reg|=4; /* Warm */
2812
2813 reg&=~8; /* ACLink on */
2814
2815 /* At this point we deassert AC_RESET # */
2816 I810_IOWRITEL(reg , card, GLOB_CNT);
2817
2818 /* We must now allow time for the Codec initialisation.
2819 600mS is the specified time */
2820
2821 for(i=0;i<10;i++)
2822 {
2823 if((I810_IOREADL(card, GLOB_CNT)&4)==0)
2824 break;
2825
2826 set_current_state(TASK_UNINTERRUPTIBLE);
2827 schedule_timeout(HZ/20);
2828 }
2829 if(i==10)
2830 {
2831 printk(KERN_ERR "i810_audio: AC'97 reset failed.\n");
2832 return 0;
2833 }
2834
2835 set_current_state(TASK_UNINTERRUPTIBLE);
2836 schedule_timeout(HZ/2);
2837
2838 /*
2839 * See if the primary codec comes ready. This must happen
2840 * before we start doing DMA stuff
2841 */
2842 /* see i810_ac97_init for the next 10 lines (jsaw) */
2843 if (card->use_mmio)
2844 readw(card->ac97base_mmio);
2845 else
2846 inw(card->ac97base);
2847 if (ich_use_mmio(card)) {
2848 primary_codec_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
2849 printk(KERN_INFO "i810_audio: Primary codec has ID %d\n",
2850 primary_codec_id);
2851 }
2852
2853 if(! i810_ac97_exists(card, primary_codec_id))
2854 {
2855 printk(KERN_INFO "i810_audio: Codec not ready.. wait.. ");
2856 set_current_state(TASK_UNINTERRUPTIBLE);
2857 schedule_timeout(HZ); /* actually 600mS by the spec */
2858
2859 if(i810_ac97_exists(card, primary_codec_id))
2860 printk("OK\n");
2861 else
2862 printk("no response.\n");
2863 }
2864 if (card->use_mmio)
2865 readw(card->ac97base_mmio);
2866 else
2867 inw(card->ac97base);
2868 return 1;
2869 }
2870
i810_ac97_init(struct i810_card * card)2871 static int __devinit i810_ac97_init(struct i810_card *card)
2872 {
2873 int num_ac97 = 0;
2874 int ac97_id;
2875 int total_channels = 0;
2876 int nr_ac97_max = card_cap[card->pci_id_internal].nr_ac97;
2877 struct ac97_codec *codec;
2878 u16 eid;
2879 u32 reg;
2880
2881 if(!i810_ac97_power_up_bus(card)) return 0;
2882
2883 /* Number of channels supported */
2884 /* What about the codec? Just because the ICH supports */
2885 /* multiple channels doesn't mean the codec does. */
2886 /* we'll have to modify this in the codec section below */
2887 /* to reflect what the codec has. */
2888 /* ICH and ICH0 only support 2 channels so don't bother */
2889 /* to check.... */
2890
2891 card->channels = 2;
2892 reg = I810_IOREADL(card, GLOB_STA);
2893 if ( reg & 0x0200000 )
2894 card->channels = 6;
2895 else if ( reg & 0x0100000 )
2896 card->channels = 4;
2897 printk(KERN_INFO "i810_audio: Audio Controller supports %d channels.\n", card->channels);
2898 printk(KERN_INFO "i810_audio: Defaulting to base 2 channel mode.\n");
2899 reg = I810_IOREADL(card, GLOB_CNT);
2900 I810_IOWRITEL(reg & 0xffcfffff, card, GLOB_CNT);
2901
2902 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++)
2903 card->ac97_codec[num_ac97] = NULL;
2904
2905 /*@FIXME I don't know, if I'm playing to safe here... (jsaw) */
2906 if ((nr_ac97_max > 2) && !card->use_mmio) nr_ac97_max = 2;
2907
2908 for (num_ac97 = 0; num_ac97 < nr_ac97_max; num_ac97++) {
2909 /* codec reset */
2910 printk(KERN_INFO "i810_audio: Resetting connection %d\n", num_ac97);
2911 if (card->use_mmio)
2912 readw(card->ac97base_mmio + 0x80*num_ac97);
2913 else
2914 inw(card->ac97base + 0x80*num_ac97);
2915
2916 /* If we have the SDATA_IN Map Register, as on ICH4, we
2917 do not loop thru all possible codec IDs but thru all
2918 possible IO channels. Bit 0:1 of SDM then holds the
2919 last codec ID spoken to.
2920 */
2921 if (ich_use_mmio(card)) {
2922 ac97_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
2923 printk(KERN_INFO "i810_audio: Connection %d with codec id %d\n",
2924 num_ac97, ac97_id);
2925 }
2926 else {
2927 ac97_id = num_ac97;
2928 }
2929
2930 /* The ICH programmer's reference says you should */
2931 /* check the ready status before probing. So we chk */
2932 /* What do we do if it's not ready? Wait and try */
2933 /* again, or abort? */
2934 if (!i810_ac97_exists(card, ac97_id)) {
2935 if(num_ac97 == 0)
2936 printk(KERN_ERR "i810_audio: Primary codec not ready.\n");
2937 }
2938
2939 if ((codec = ac97_alloc_codec()) == NULL)
2940 return -ENOMEM;
2941
2942 /* initialize some basic codec information, other fields will be filled
2943 in ac97_probe_codec */
2944 codec->private_data = card;
2945 codec->id = ac97_id;
2946 card->ac97_id_map[ac97_id] = num_ac97 * 0x80;
2947
2948 if (card->use_mmio) {
2949 codec->codec_read = i810_ac97_get_mmio;
2950 codec->codec_write = i810_ac97_set_mmio;
2951 }
2952 else {
2953 codec->codec_read = i810_ac97_get_io;
2954 codec->codec_write = i810_ac97_set_io;
2955 }
2956
2957 if(!i810_ac97_probe_and_powerup(card,codec)) {
2958 printk(KERN_ERR "i810_audio: timed out waiting for codec %d analog ready.\n", ac97_id);
2959 ac97_release_codec(codec);
2960 break; /* it didn't work */
2961 }
2962 /* Store state information about S/PDIF transmitter */
2963 card->ac97_status = 0;
2964
2965 /* Don't attempt to get eid until powerup is complete */
2966 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
2967
2968 if(eid==0xFFFF)
2969 {
2970 printk(KERN_WARNING "i810_audio: no codec attached ?\n");
2971 ac97_release_codec(codec);
2972 break;
2973 }
2974
2975 /* Check for an AC97 1.0 soft modem (ID1) */
2976
2977 if(codec->modem)
2978 {
2979 printk(KERN_WARNING "i810_audio: codec %d is a softmodem - skipping.\n", ac97_id);
2980 ac97_release_codec(codec);
2981 continue;
2982 }
2983
2984 card->ac97_features = eid;
2985
2986 /* Now check the codec for useful features to make up for
2987 the dumbness of the 810 hardware engine */
2988
2989 if(!(eid&0x0001))
2990 printk(KERN_WARNING "i810_audio: only 48Khz playback available.\n");
2991 else
2992 {
2993 if(!i810_ac97_enable_variable_rate(codec)) {
2994 printk(KERN_WARNING "i810_audio: Codec refused to allow VRA, using 48Khz only.\n");
2995 card->ac97_features&=~1;
2996 }
2997 }
2998
2999 /* Turn on the amplifier */
3000
3001 codec->codec_write(codec, AC97_POWER_CONTROL,
3002 codec->codec_read(codec, AC97_POWER_CONTROL) & ~0x8000);
3003
3004 /* Determine how many channels the codec(s) support */
3005 /* - The primary codec always supports 2 */
3006 /* - If the codec supports AMAP, surround DACs will */
3007 /* automaticlly get assigned to slots. */
3008 /* * Check for surround DACs and increment if */
3009 /* found. */
3010 /* - Else check if the codec is revision 2.2 */
3011 /* * If surround DACs exist, assign them to slots */
3012 /* and increment channel count. */
3013
3014 /* All of this only applies to ICH2 and above. ICH */
3015 /* and ICH0 only support 2 channels. ICH2 will only */
3016 /* support multiple codecs in a "split audio" config. */
3017 /* as described above. */
3018
3019 /* TODO: Remove all the debugging messages! */
3020
3021 if((eid & 0xc000) == 0) /* primary codec */
3022 total_channels += 2;
3023
3024 if(eid & 0x200) { /* GOOD, AMAP support */
3025 if (eid & 0x0080) /* L/R Surround channels */
3026 total_channels += 2;
3027 if (eid & 0x0140) /* LFE and Center channels */
3028 total_channels += 2;
3029 printk("i810_audio: AC'97 codec %d supports AMAP, total channels = %d\n", ac97_id, total_channels);
3030 } else if (eid & 0x0400) { /* this only works on 2.2 compliant codecs */
3031 eid &= 0xffcf;
3032 if((eid & 0xc000) != 0) {
3033 switch ( total_channels ) {
3034 case 2:
3035 /* Set dsa1, dsa0 to 01 */
3036 eid |= 0x0010;
3037 break;
3038 case 4:
3039 /* Set dsa1, dsa0 to 10 */
3040 eid |= 0x0020;
3041 break;
3042 case 6:
3043 /* Set dsa1, dsa0 to 11 */
3044 eid |= 0x0030;
3045 break;
3046 }
3047 total_channels += 2;
3048 }
3049 i810_ac97_set(codec, AC97_EXTENDED_ID, eid);
3050 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
3051 printk("i810_audio: AC'97 codec %d, new EID value = 0x%04x\n", ac97_id, eid);
3052 if (eid & 0x0080) /* L/R Surround channels */
3053 total_channels += 2;
3054 if (eid & 0x0140) /* LFE and Center channels */
3055 total_channels += 2;
3056 printk("i810_audio: AC'97 codec %d, DAC map configured, total channels = %d\n", ac97_id, total_channels);
3057 } else {
3058 printk("i810_audio: AC'97 codec %d Unable to map surround DAC's (or DAC's not present), total channels = %d\n", ac97_id, total_channels);
3059 }
3060
3061 if ((codec->dev_mixer = register_sound_mixer(&i810_mixer_fops, -1)) < 0) {
3062 printk(KERN_ERR "i810_audio: couldn't register mixer!\n");
3063 ac97_release_codec(codec);
3064 break;
3065 }
3066
3067 card->ac97_codec[num_ac97] = codec;
3068 }
3069
3070 /* pick the minimum of channels supported by ICHx or codec(s) */
3071 card->channels = (card->channels > total_channels)?total_channels:card->channels;
3072
3073 return num_ac97;
3074 }
3075
i810_configure_clocking(void)3076 static void __devinit i810_configure_clocking (void)
3077 {
3078 struct i810_card *card;
3079 struct i810_state *state;
3080 struct dmabuf *dmabuf;
3081 unsigned int i, offset, new_offset;
3082 unsigned long flags;
3083
3084 card = devs;
3085 /* We could try to set the clocking for multiple cards, but can you even have
3086 * more than one i810 in a machine? Besides, clocking is global, so unless
3087 * someone actually thinks more than one i810 in a machine is possible and
3088 * decides to rewrite that little bit, setting the rate for more than one card
3089 * is a waste of time.
3090 */
3091 if(card != NULL) {
3092 state = card->states[0] = (struct i810_state *)
3093 kmalloc(sizeof(struct i810_state), GFP_KERNEL);
3094 if (state == NULL)
3095 return;
3096 memset(state, 0, sizeof(struct i810_state));
3097 dmabuf = &state->dmabuf;
3098
3099 dmabuf->write_channel = card->alloc_pcm_channel(card);
3100 state->virt = 0;
3101 state->card = card;
3102 state->magic = I810_STATE_MAGIC;
3103 init_waitqueue_head(&dmabuf->wait);
3104 init_MUTEX(&state->open_sem);
3105 dmabuf->fmt = I810_FMT_STEREO | I810_FMT_16BIT;
3106 dmabuf->trigger = PCM_ENABLE_OUTPUT;
3107 i810_set_spdif_output(state, -1, 0);
3108 i810_set_dac_channels(state, 2);
3109 i810_set_dac_rate(state, 48000);
3110 if(prog_dmabuf(state, 0) != 0) {
3111 goto config_out_nodmabuf;
3112 }
3113 if(dmabuf->dmasize < 16384) {
3114 goto config_out;
3115 }
3116 dmabuf->count = dmabuf->dmasize;
3117 CIV_TO_LVI(card, dmabuf->write_channel->port, -1);
3118 local_irq_save(flags);
3119 start_dac(state);
3120 offset = i810_get_dma_addr(state, 0);
3121 mdelay(50);
3122 new_offset = i810_get_dma_addr(state, 0);
3123 stop_dac(state);
3124 local_irq_restore(flags);
3125 i = new_offset - offset;
3126 #ifdef DEBUG_INTERRUPTS
3127 printk("i810_audio: %d bytes in 50 milliseconds\n", i);
3128 #endif
3129 if(i == 0)
3130 goto config_out;
3131 i = i / 4 * 20;
3132 if (i > 48500 || i < 47500) {
3133 clocking = clocking * clocking / i;
3134 printk("i810_audio: setting clocking to %d\n", clocking);
3135 }
3136 config_out:
3137 dealloc_dmabuf(state);
3138 config_out_nodmabuf:
3139 state->card->free_pcm_channel(state->card,state->dmabuf.write_channel->num);
3140 kfree(state);
3141 card->states[0] = NULL;
3142 }
3143 }
3144
3145 /* install the driver, we do not allocate hardware channel nor DMA buffer now, they are defered
3146 until "ACCESS" time (in prog_dmabuf called by open/read/write/ioctl/mmap) */
3147
i810_probe(struct pci_dev * pci_dev,const struct pci_device_id * pci_id)3148 static int __devinit i810_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
3149 {
3150 struct i810_card *card;
3151
3152 if (pci_enable_device(pci_dev))
3153 return -EIO;
3154
3155 if (pci_set_dma_mask(pci_dev, I810_DMA_MASK)) {
3156 printk(KERN_ERR "i810_audio: architecture does not support"
3157 " 32bit PCI busmaster DMA\n");
3158 return -ENODEV;
3159 }
3160
3161 if ((card = kmalloc(sizeof(struct i810_card), GFP_KERNEL)) == NULL) {
3162 printk(KERN_ERR "i810_audio: out of memory\n");
3163 return -ENOMEM;
3164 }
3165 memset(card, 0, sizeof(*card));
3166
3167 card->initializing = 1;
3168 card->pci_dev = pci_dev;
3169 card->pci_id = pci_id->device;
3170 card->ac97base = pci_resource_start (pci_dev, 0);
3171 card->iobase = pci_resource_start (pci_dev, 1);
3172
3173 if (!(card->ac97base) || !(card->iobase)) {
3174 card->ac97base = 0;
3175 card->iobase = 0;
3176 }
3177
3178 /* if chipset could have mmio capability, check it */
3179 if (card_cap[pci_id->driver_data].flags & CAP_MMIO) {
3180 card->ac97base_mmio_phys = pci_resource_start (pci_dev, 2);
3181 card->iobase_mmio_phys = pci_resource_start (pci_dev, 3);
3182
3183 if ((card->ac97base_mmio_phys) && (card->iobase_mmio_phys)) {
3184 card->use_mmio = 1;
3185 }
3186 else {
3187 card->ac97base_mmio_phys = 0;
3188 card->iobase_mmio_phys = 0;
3189 }
3190 }
3191
3192 if (!(card->use_mmio) && (!(card->iobase) || !(card->ac97base))) {
3193 printk(KERN_ERR "i810_audio: No I/O resources available.\n");
3194 goto out_mem;
3195 }
3196
3197 card->irq = pci_dev->irq;
3198 card->next = devs;
3199 card->magic = I810_CARD_MAGIC;
3200 #ifdef CONFIG_PM
3201 card->pm_suspended=0;
3202 #endif
3203 spin_lock_init(&card->lock);
3204 spin_lock_init(&card->ac97_lock);
3205 devs = card;
3206
3207 pci_set_master(pci_dev);
3208
3209 printk(KERN_INFO "i810: %s found at IO 0x%04lx and 0x%04lx, "
3210 "MEM 0x%04lx and 0x%04lx, IRQ %d\n",
3211 card_names[pci_id->driver_data],
3212 card->iobase, card->ac97base,
3213 card->ac97base_mmio_phys, card->iobase_mmio_phys,
3214 card->irq);
3215
3216 card->alloc_pcm_channel = i810_alloc_pcm_channel;
3217 card->alloc_rec_pcm_channel = i810_alloc_rec_pcm_channel;
3218 card->alloc_rec_mic_channel = i810_alloc_rec_mic_channel;
3219 card->free_pcm_channel = i810_free_pcm_channel;
3220
3221 if ((card->channel = pci_alloc_consistent(pci_dev,
3222 sizeof(struct i810_channel)*NR_HW_CH, &card->chandma)) == NULL) {
3223 printk(KERN_ERR "i810: cannot allocate channel DMA memory\n");
3224 goto out_mem;
3225 }
3226
3227 { /* We may dispose of this altogether some time soon, so... */
3228 struct i810_channel *cp = card->channel;
3229
3230 cp[0].offset = 0;
3231 cp[0].port = 0x00;
3232 cp[0].num = 0;
3233 cp[1].offset = 0;
3234 cp[1].port = 0x10;
3235 cp[1].num = 1;
3236 cp[2].offset = 0;
3237 cp[2].port = 0x20;
3238 cp[2].num = 2;
3239 }
3240
3241 /* claim our iospace and irq */
3242 if (!request_region(card->iobase, 64, card_names[pci_id->driver_data])) {
3243 printk(KERN_ERR "i810_audio: unable to allocate region %lx\n", card->iobase);
3244 goto out_region1;
3245 }
3246 if (!request_region(card->ac97base, 256, card_names[pci_id->driver_data])) {
3247 printk(KERN_ERR "i810_audio: unable to allocate region %lx\n", card->ac97base);
3248 goto out_region2;
3249 }
3250
3251 if (request_irq(card->irq, &i810_interrupt, SA_SHIRQ,
3252 card_names[pci_id->driver_data], card)) {
3253 printk(KERN_ERR "i810_audio: unable to allocate irq %d\n", card->irq);
3254 goto out_pio;
3255 }
3256
3257 if (card->use_mmio) {
3258 if (request_mem_region(card->ac97base_mmio_phys, 512, "ich_audio MMBAR")) {
3259 if ((card->ac97base_mmio = ioremap(card->ac97base_mmio_phys, 512))) { /*@FIXME can ioremap fail? don't know (jsaw) */
3260 if (request_mem_region(card->iobase_mmio_phys, 256, "ich_audio MBBAR")) {
3261 if ((card->iobase_mmio = ioremap(card->iobase_mmio_phys, 256))) {
3262 printk(KERN_INFO "i810: %s mmio at 0x%04lx and 0x%04lx\n",
3263 card_names[pci_id->driver_data],
3264 (unsigned long) card->ac97base_mmio,
3265 (unsigned long) card->iobase_mmio);
3266 }
3267 else {
3268 iounmap(card->ac97base_mmio);
3269 release_mem_region(card->ac97base_mmio_phys, 512);
3270 release_mem_region(card->iobase_mmio_phys, 512);
3271 card->use_mmio = 0;
3272 }
3273 }
3274 else {
3275 iounmap(card->ac97base_mmio);
3276 release_mem_region(card->ac97base_mmio_phys, 512);
3277 card->use_mmio = 0;
3278 }
3279 }
3280 }
3281 else {
3282 card->use_mmio = 0;
3283 }
3284 }
3285
3286 /* initialize AC97 codec and register /dev/mixer */
3287 if (i810_ac97_init(card) <= 0) {
3288 free_irq(card->irq, card);
3289 goto out_iospace;
3290 }
3291 pci_set_drvdata(pci_dev, card);
3292
3293 if(clocking == 0) {
3294 clocking = 48000;
3295 i810_configure_clocking();
3296 }
3297
3298 /* register /dev/dsp */
3299 if ((card->dev_audio = register_sound_dsp(&i810_audio_fops, -1)) < 0) {
3300 int i;
3301 printk(KERN_ERR "i810_audio: couldn't register DSP device!\n");
3302 free_irq(card->irq, card);
3303 for (i = 0; i < NR_AC97; i++)
3304 if (card->ac97_codec[i] != NULL) {
3305 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3306 ac97_release_codec(card->ac97_codec[i]);
3307 }
3308 goto out_iospace;
3309 }
3310
3311 card->initializing = 0;
3312 return 0;
3313
3314 out_iospace:
3315 if (card->use_mmio) {
3316 iounmap(card->ac97base_mmio);
3317 iounmap(card->iobase_mmio);
3318 release_mem_region(card->ac97base_mmio_phys, 512);
3319 release_mem_region(card->iobase_mmio_phys, 256);
3320 }
3321 out_pio:
3322 release_region(card->ac97base, 256);
3323 out_region2:
3324 release_region(card->iobase, 64);
3325 out_region1:
3326 pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3327 card->channel, card->chandma);
3328 out_mem:
3329 kfree(card);
3330 return -ENODEV;
3331 }
3332
i810_remove(struct pci_dev * pci_dev)3333 static void __devexit i810_remove(struct pci_dev *pci_dev)
3334 {
3335 int i;
3336 struct i810_card *card = pci_get_drvdata(pci_dev);
3337 /* free hardware resources */
3338 free_irq(card->irq, devs);
3339 release_region(card->iobase, 64);
3340 release_region(card->ac97base, 256);
3341 pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3342 card->channel, card->chandma);
3343 if (card->use_mmio) {
3344 iounmap(card->ac97base_mmio);
3345 iounmap(card->iobase_mmio);
3346 release_mem_region(card->ac97base_mmio_phys, 512);
3347 release_mem_region(card->iobase_mmio_phys, 256);
3348 }
3349
3350 /* unregister audio devices */
3351 for (i = 0; i < NR_AC97; i++)
3352 if (card->ac97_codec[i] != NULL) {
3353 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3354 ac97_release_codec(card->ac97_codec[i]);
3355 card->ac97_codec[i] = NULL;
3356 }
3357 unregister_sound_dsp(card->dev_audio);
3358 kfree(card);
3359 }
3360
3361 #ifdef CONFIG_PM
i810_pm_suspend(struct pci_dev * dev,u32 pm_state)3362 static int i810_pm_suspend(struct pci_dev *dev, u32 pm_state)
3363 {
3364 struct i810_card *card = pci_get_drvdata(dev);
3365 struct i810_state *state;
3366 unsigned long flags;
3367 struct dmabuf *dmabuf;
3368 int i,num_ac97;
3369 #ifdef DEBUG
3370 printk("i810_audio: i810_pm_suspend called\n");
3371 #endif
3372 if(!card) return 0;
3373 spin_lock_irqsave(&card->lock, flags);
3374 card->pm_suspended=1;
3375 for(i=0;i<NR_HW_CH;i++) {
3376 state = card->states[i];
3377 if(!state) continue;
3378 /* this happens only if there are open files */
3379 dmabuf = &state->dmabuf;
3380 if(dmabuf->enable & DAC_RUNNING ||
3381 (dmabuf->count && (dmabuf->trigger & PCM_ENABLE_OUTPUT))) {
3382 state->pm_saved_dac_rate=dmabuf->rate;
3383 stop_dac(state);
3384 } else {
3385 state->pm_saved_dac_rate=0;
3386 }
3387 if(dmabuf->enable & ADC_RUNNING) {
3388 state->pm_saved_adc_rate=dmabuf->rate;
3389 stop_adc(state);
3390 } else {
3391 state->pm_saved_adc_rate=0;
3392 }
3393 dmabuf->ready = 0;
3394 dmabuf->swptr = dmabuf->hwptr = 0;
3395 dmabuf->count = dmabuf->total_bytes = 0;
3396 }
3397
3398 spin_unlock_irqrestore(&card->lock, flags);
3399
3400 /* save mixer settings */
3401 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3402 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3403 if(!codec) continue;
3404 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3405 if((supported_mixer(codec,i)) &&
3406 (codec->read_mixer)) {
3407 card->pm_saved_mixer_settings[i][num_ac97]=
3408 codec->read_mixer(codec,i);
3409 }
3410 }
3411 }
3412 pci_save_state(dev,card->pm_save_state); /* XXX do we need this? */
3413 pci_disable_device(dev); /* disable busmastering */
3414 pci_set_power_state(dev,3); /* Zzz. */
3415
3416 return 0;
3417 }
3418
3419
i810_pm_resume(struct pci_dev * dev)3420 static int i810_pm_resume(struct pci_dev *dev)
3421 {
3422 int num_ac97,i=0;
3423 struct i810_card *card=pci_get_drvdata(dev);
3424 pci_enable_device(dev);
3425 pci_restore_state (dev,card->pm_save_state);
3426
3427 /* observation of a toshiba portege 3440ct suggests that the
3428 hardware has to be more or less completely reinitialized from
3429 scratch after an apm suspend. Works For Me. -dan */
3430
3431 i810_ac97_power_up_bus(card);
3432
3433 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3434 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3435 /* check they haven't stolen the hardware while we were
3436 away */
3437 if(!codec || !i810_ac97_exists(card,num_ac97)) {
3438 if(num_ac97) continue;
3439 else BUG();
3440 }
3441 if(!i810_ac97_probe_and_powerup(card,codec)) BUG();
3442
3443 if((card->ac97_features&0x0001)) {
3444 /* at probe time we found we could do variable
3445 rates, but APM suspend has made it forget
3446 its magical powers */
3447 if(!i810_ac97_enable_variable_rate(codec)) BUG();
3448 }
3449 /* we lost our mixer settings, so restore them */
3450 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3451 if(supported_mixer(codec,i)){
3452 int val=card->
3453 pm_saved_mixer_settings[i][num_ac97];
3454 codec->mixer_state[i]=val;
3455 codec->write_mixer(codec,i,
3456 (val & 0xff) ,
3457 ((val >> 8) & 0xff) );
3458 }
3459 }
3460 }
3461
3462 /* we need to restore the sample rate from whatever it was */
3463 for(i=0;i<NR_HW_CH;i++) {
3464 struct i810_state * state=card->states[i];
3465 if(state) {
3466 if(state->pm_saved_adc_rate)
3467 i810_set_adc_rate(state,state->pm_saved_adc_rate);
3468 if(state->pm_saved_dac_rate)
3469 i810_set_dac_rate(state,state->pm_saved_dac_rate);
3470 }
3471 }
3472
3473
3474 card->pm_suspended = 0;
3475
3476 /* any processes that were reading/writing during the suspend
3477 probably ended up here */
3478 for(i=0;i<NR_HW_CH;i++) {
3479 struct i810_state *state = card->states[i];
3480 if(state) wake_up(&state->dmabuf.wait);
3481 }
3482
3483 return 0;
3484 }
3485 #endif /* CONFIG_PM */
3486
3487 MODULE_AUTHOR("");
3488 MODULE_DESCRIPTION("Intel 810 audio support");
3489 MODULE_LICENSE("GPL");
3490 MODULE_PARM(ftsodell, "i");
3491 MODULE_PARM(clocking, "i");
3492 MODULE_PARM(strict_clocking, "i");
3493 MODULE_PARM(spdif_locked, "i");
3494
3495 #define I810_MODULE_NAME "intel810_audio"
3496
3497 static struct pci_driver i810_pci_driver = {
3498 .name = I810_MODULE_NAME,
3499 .id_table = i810_pci_tbl,
3500 .probe = i810_probe,
3501 .remove = __devexit_p(i810_remove),
3502 #ifdef CONFIG_PM
3503 .suspend = i810_pm_suspend,
3504 .resume = i810_pm_resume,
3505 #endif /* CONFIG_PM */
3506 };
3507
3508
i810_init_module(void)3509 static int __init i810_init_module (void)
3510 {
3511 printk(KERN_INFO "Intel 810 + AC97 Audio, version "
3512 DRIVER_VERSION ", " __TIME__ " " __DATE__ "\n");
3513
3514 if (!pci_register_driver(&i810_pci_driver)) {
3515 pci_unregister_driver(&i810_pci_driver);
3516 return -ENODEV;
3517 }
3518 if(ftsodell != 0) {
3519 printk("i810_audio: ftsodell is now a deprecated option.\n");
3520 }
3521 if(spdif_locked > 0 ) {
3522 if(spdif_locked == 32000 || spdif_locked == 44100 || spdif_locked == 48000) {
3523 printk("i810_audio: Enabling S/PDIF at sample rate %dHz.\n", spdif_locked);
3524 } else {
3525 printk("i810_audio: S/PDIF can only be locked to 32000, 44100, or 48000Hz.\n");
3526 spdif_locked = 0;
3527 }
3528 }
3529
3530 return 0;
3531 }
3532
i810_cleanup_module(void)3533 static void __exit i810_cleanup_module (void)
3534 {
3535 pci_unregister_driver(&i810_pci_driver);
3536 }
3537
3538 module_init(i810_init_module);
3539 module_exit(i810_cleanup_module);
3540
3541 /*
3542 Local Variables:
3543 c-basic-offset: 8
3544 End:
3545 */
3546