1 /* 2 * Freescale CLKCTRL Register Definitions 3 * 4 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 * This file is created by xml file. Don't Edit it. 21 * 22 * Xml Revision: 1.48 23 * Template revision: 26195 24 */ 25 26 #ifndef __REGS_CLKCTRL_MX28_H__ 27 #define __REGS_CLKCTRL_MX28_H__ 28 29 #define HW_CLKCTRL_PLL0CTRL0 (0x00000000) 30 #define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004) 31 #define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) 32 #define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) 33 34 #define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 35 #define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 36 #define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ 37 (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL) 38 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0 39 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 40 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 41 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 42 #define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 43 #define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 44 #define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ 45 (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL) 46 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0 47 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 48 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 49 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 50 #define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 51 #define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 52 #define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ 53 (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL) 54 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0 55 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 56 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 57 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 58 #define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 59 #define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 60 61 #define HW_CLKCTRL_PLL0CTRL1 (0x00000010) 62 63 #define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 64 #define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 65 #define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 66 #define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF 67 #define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ 68 (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT) 69 70 #define HW_CLKCTRL_PLL1CTRL0 (0x00000020) 71 #define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024) 72 #define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028) 73 #define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) 74 75 #define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 76 #define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 77 #define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 78 #define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ 79 (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL) 80 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0 81 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 82 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 83 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 84 #define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 85 #define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 86 #define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ 87 (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL) 88 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0 89 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 90 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 91 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 92 #define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 93 #define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 94 #define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ 95 (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL) 96 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0 97 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 98 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 99 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 100 #define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 101 #define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 102 103 #define HW_CLKCTRL_PLL1CTRL1 (0x00000030) 104 105 #define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 106 #define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 107 #define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 108 #define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF 109 #define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ 110 (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT) 111 112 #define HW_CLKCTRL_PLL2CTRL0 (0x00000040) 113 #define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044) 114 #define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048) 115 #define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) 116 117 #define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 118 #define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 119 #define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 120 #define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ 121 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) 122 #define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 123 #define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 124 #define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 125 #define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ 126 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) 127 #define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 128 129 #define HW_CLKCTRL_CPU (0x00000050) 130 #define HW_CLKCTRL_CPU_SET (0x00000054) 131 #define HW_CLKCTRL_CPU_CLR (0x00000058) 132 #define HW_CLKCTRL_CPU_TOG (0x0000005c) 133 134 #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 135 #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 136 #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 137 #define BP_CLKCTRL_CPU_DIV_XTAL 16 138 #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 139 #define BF_CLKCTRL_CPU_DIV_XTAL(v) \ 140 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) 141 #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 142 #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 143 #define BP_CLKCTRL_CPU_DIV_CPU 0 144 #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F 145 #define BF_CLKCTRL_CPU_DIV_CPU(v) \ 146 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) 147 148 #define HW_CLKCTRL_HBUS (0x00000060) 149 #define HW_CLKCTRL_HBUS_SET (0x00000064) 150 #define HW_CLKCTRL_HBUS_CLR (0x00000068) 151 #define HW_CLKCTRL_HBUS_TOG (0x0000006c) 152 153 #define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 154 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 155 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 156 #define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 157 #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 158 #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 159 #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 160 #define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 161 #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 162 #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 163 #define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000 164 #define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000 165 #define BP_CLKCTRL_HBUS_SLOW_DIV 16 166 #define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 167 #define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ 168 (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) 169 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 170 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 171 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 172 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 173 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 174 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 175 #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 176 #define BP_CLKCTRL_HBUS_DIV 0 177 #define BM_CLKCTRL_HBUS_DIV 0x0000001F 178 #define BF_CLKCTRL_HBUS_DIV(v) \ 179 (((v) << 0) & BM_CLKCTRL_HBUS_DIV) 180 181 #define HW_CLKCTRL_XBUS (0x00000070) 182 183 #define BM_CLKCTRL_XBUS_BUSY 0x80000000 184 #define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 185 #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 186 #define BP_CLKCTRL_XBUS_DIV 0 187 #define BM_CLKCTRL_XBUS_DIV 0x000003FF 188 #define BF_CLKCTRL_XBUS_DIV(v) \ 189 (((v) << 0) & BM_CLKCTRL_XBUS_DIV) 190 191 #define HW_CLKCTRL_XTAL (0x00000080) 192 #define HW_CLKCTRL_XTAL_SET (0x00000084) 193 #define HW_CLKCTRL_XTAL_CLR (0x00000088) 194 #define HW_CLKCTRL_XTAL_TOG (0x0000008c) 195 196 #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 197 #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 198 #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 199 #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 200 #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 201 #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 202 #define BP_CLKCTRL_XTAL_DIV_UART 0 203 #define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 204 #define BF_CLKCTRL_XTAL_DIV_UART(v) \ 205 (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) 206 207 #define HW_CLKCTRL_SSP0 (0x00000090) 208 209 #define BP_CLKCTRL_SSP0_CLKGATE 31 210 #define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 211 #define BM_CLKCTRL_SSP0_BUSY 0x20000000 212 #define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 213 #define BP_CLKCTRL_SSP0_DIV 0 214 #define BM_CLKCTRL_SSP0_DIV 0x000001FF 215 #define BF_CLKCTRL_SSP0_DIV(v) \ 216 (((v) << 0) & BM_CLKCTRL_SSP0_DIV) 217 218 #define HW_CLKCTRL_SSP1 (0x000000a0) 219 220 #define BP_CLKCTRL_SSP1_CLKGATE 31 221 #define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 222 #define BM_CLKCTRL_SSP1_BUSY 0x20000000 223 #define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 224 #define BP_CLKCTRL_SSP1_DIV 0 225 #define BM_CLKCTRL_SSP1_DIV 0x000001FF 226 #define BF_CLKCTRL_SSP1_DIV(v) \ 227 (((v) << 0) & BM_CLKCTRL_SSP1_DIV) 228 229 #define HW_CLKCTRL_SSP2 (0x000000b0) 230 231 #define BP_CLKCTRL_SSP2_CLKGATE 31 232 #define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 233 #define BM_CLKCTRL_SSP2_BUSY 0x20000000 234 #define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 235 #define BP_CLKCTRL_SSP2_DIV 0 236 #define BM_CLKCTRL_SSP2_DIV 0x000001FF 237 #define BF_CLKCTRL_SSP2_DIV(v) \ 238 (((v) << 0) & BM_CLKCTRL_SSP2_DIV) 239 240 #define HW_CLKCTRL_SSP3 (0x000000c0) 241 242 #define BP_CLKCTRL_SSP3_CLKGATE 31 243 #define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 244 #define BM_CLKCTRL_SSP3_BUSY 0x20000000 245 #define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 246 #define BP_CLKCTRL_SSP3_DIV 0 247 #define BM_CLKCTRL_SSP3_DIV 0x000001FF 248 #define BF_CLKCTRL_SSP3_DIV(v) \ 249 (((v) << 0) & BM_CLKCTRL_SSP3_DIV) 250 251 #define HW_CLKCTRL_GPMI (0x000000d0) 252 253 #define BP_CLKCTRL_GPMI_CLKGATE 31 254 #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 255 #define BM_CLKCTRL_GPMI_BUSY 0x20000000 256 #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 257 #define BP_CLKCTRL_GPMI_DIV 0 258 #define BM_CLKCTRL_GPMI_DIV 0x000003FF 259 #define BF_CLKCTRL_GPMI_DIV(v) \ 260 (((v) << 0) & BM_CLKCTRL_GPMI_DIV) 261 262 #define HW_CLKCTRL_SPDIF (0x000000e0) 263 264 #define BP_CLKCTRL_SPDIF_CLKGATE 31 265 #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 266 267 #define HW_CLKCTRL_EMI (0x000000f0) 268 269 #define BP_CLKCTRL_EMI_CLKGATE 31 270 #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 271 #define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 272 #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 273 #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 274 #define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 275 #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 276 #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 277 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 278 #define BP_CLKCTRL_EMI_DIV_XTAL 8 279 #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 280 #define BF_CLKCTRL_EMI_DIV_XTAL(v) \ 281 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) 282 #define BP_CLKCTRL_EMI_DIV_EMI 0 283 #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F 284 #define BF_CLKCTRL_EMI_DIV_EMI(v) \ 285 (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) 286 287 #define HW_CLKCTRL_SAIF0 (0x00000100) 288 289 #define BP_CLKCTRL_SAIF0_CLKGATE 31 290 #define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 291 #define BM_CLKCTRL_SAIF0_BUSY 0x20000000 292 #define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 293 #define BP_CLKCTRL_SAIF0_DIV 0 294 #define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF 295 #define BF_CLKCTRL_SAIF0_DIV(v) \ 296 (((v) << 0) & BM_CLKCTRL_SAIF0_DIV) 297 298 #define HW_CLKCTRL_SAIF1 (0x00000110) 299 300 #define BP_CLKCTRL_SAIF1_CLKGATE 31 301 #define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 302 #define BM_CLKCTRL_SAIF1_BUSY 0x20000000 303 #define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 304 #define BP_CLKCTRL_SAIF1_DIV 0 305 #define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF 306 #define BF_CLKCTRL_SAIF1_DIV(v) \ 307 (((v) << 0) & BM_CLKCTRL_SAIF1_DIV) 308 309 #define HW_CLKCTRL_DIS_LCDIF (0x00000120) 310 311 #define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31 312 #define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 313 #define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 314 #define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 315 #define BP_CLKCTRL_DIS_LCDIF_DIV 0 316 #define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF 317 #define BF_CLKCTRL_DIS_LCDIF_DIV(v) \ 318 (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV) 319 320 #define HW_CLKCTRL_ETM (0x00000130) 321 322 #define BM_CLKCTRL_ETM_CLKGATE 0x80000000 323 #define BM_CLKCTRL_ETM_BUSY 0x20000000 324 #define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 325 #define BP_CLKCTRL_ETM_DIV 0 326 #define BM_CLKCTRL_ETM_DIV 0x0000007F 327 #define BF_CLKCTRL_ETM_DIV(v) \ 328 (((v) << 0) & BM_CLKCTRL_ETM_DIV) 329 330 #define HW_CLKCTRL_ENET (0x00000140) 331 332 #define BM_CLKCTRL_ENET_SLEEP 0x80000000 333 #define BP_CLKCTRL_ENET_DISABLE 30 334 #define BM_CLKCTRL_ENET_DISABLE 0x40000000 335 #define BM_CLKCTRL_ENET_STATUS 0x20000000 336 #define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 337 #define BP_CLKCTRL_ENET_DIV_TIME 21 338 #define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 339 #define BF_CLKCTRL_ENET_DIV_TIME(v) \ 340 (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME) 341 #define BM_CLKCTRL_ENET_BUSY 0x08000000 342 #define BP_CLKCTRL_ENET_DIV 21 343 #define BM_CLKCTRL_ENET_DIV 0x07E00000 344 #define BF_CLKCTRL_ENET_DIV(v) \ 345 (((v) << 21) & BM_CLKCTRL_ENET_DIV) 346 #define BP_CLKCTRL_ENET_TIME_SEL 19 347 #define BM_CLKCTRL_ENET_TIME_SEL 0x00180000 348 #define BF_CLKCTRL_ENET_TIME_SEL(v) \ 349 (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL) 350 #define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0 351 #define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1 352 #define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2 353 #define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3 354 #define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 355 #define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 356 #define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 357 358 #define HW_CLKCTRL_HSADC (0x00000150) 359 360 #define BM_CLKCTRL_HSADC_RESETB 0x40000000 361 #define BP_CLKCTRL_HSADC_FREQDIV 28 362 #define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 363 #define BF_CLKCTRL_HSADC_FREQDIV(v) \ 364 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) 365 366 #define HW_CLKCTRL_FLEXCAN (0x00000160) 367 368 #define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30 369 #define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 370 #define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 371 #define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28 372 #define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 373 #define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 374 375 #define HW_CLKCTRL_FRAC0 (0x000001b0) 376 #define HW_CLKCTRL_FRAC0_SET (0x000001b4) 377 #define HW_CLKCTRL_FRAC0_CLR (0x000001b8) 378 #define HW_CLKCTRL_FRAC0_TOG (0x000001bc) 379 380 #define BP_CLKCTRL_FRAC0_CLKGATEIO0 31 381 #define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000 382 #define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000 383 #define BP_CLKCTRL_FRAC0_IO0FRAC 24 384 #define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000 385 #define BF_CLKCTRL_FRAC0_IO0FRAC(v) \ 386 (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC) 387 #define BP_CLKCTRL_FRAC0_CLKGATEIO1 23 388 #define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000 389 #define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000 390 #define BP_CLKCTRL_FRAC0_IO1FRAC 16 391 #define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000 392 #define BF_CLKCTRL_FRAC0_IO1FRAC(v) \ 393 (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC) 394 #define BP_CLKCTRL_FRAC0_CLKGATEEMI 15 395 #define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000 396 #define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000 397 #define BP_CLKCTRL_FRAC0_EMIFRAC 8 398 #define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00 399 #define BF_CLKCTRL_FRAC0_EMIFRAC(v) \ 400 (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC) 401 #define BP_CLKCTRL_FRAC0_CLKGATECPU 7 402 #define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080 403 #define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040 404 #define BP_CLKCTRL_FRAC0_CPUFRAC 0 405 #define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F 406 #define BF_CLKCTRL_FRAC0_CPUFRAC(v) \ 407 (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC) 408 409 #define HW_CLKCTRL_FRAC1 (0x000001c0) 410 #define HW_CLKCTRL_FRAC1_SET (0x000001c4) 411 #define HW_CLKCTRL_FRAC1_CLR (0x000001c8) 412 #define HW_CLKCTRL_FRAC1_TOG (0x000001cc) 413 414 #define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23 415 #define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 416 #define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 417 #define BP_CLKCTRL_FRAC1_GPMIFRAC 16 418 #define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000 419 #define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \ 420 (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC) 421 #define BP_CLKCTRL_FRAC1_CLKGATEHSADC 15 422 #define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000 423 #define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000 424 #define BP_CLKCTRL_FRAC1_HSADCFRAC 8 425 #define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00 426 #define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \ 427 (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC) 428 #define BP_CLKCTRL_FRAC1_CLKGATEPIX 7 429 #define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080 430 #define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040 431 #define BP_CLKCTRL_FRAC1_PIXFRAC 0 432 #define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F 433 #define BF_CLKCTRL_FRAC1_PIXFRAC(v) \ 434 (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC) 435 436 #define HW_CLKCTRL_CLKSEQ (0x000001d0) 437 #define HW_CLKCTRL_CLKSEQ_SET (0x000001d4) 438 #define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) 439 #define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) 440 441 #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 442 #define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 443 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 444 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 445 #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 446 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 447 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 448 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020 449 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010 450 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008 451 #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004 452 #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002 453 #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001 454 455 #define HW_CLKCTRL_RESET (0x000001e0) 456 457 #define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 458 #define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 459 #define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 460 #define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004 461 #define BM_CLKCTRL_RESET_CHIP 0x00000002 462 #define BM_CLKCTRL_RESET_DIG 0x00000001 463 464 #define HW_CLKCTRL_STATUS (0x000001f0) 465 466 #define BP_CLKCTRL_STATUS_CPU_LIMIT 30 467 #define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 468 #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ 469 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) 470 471 #define HW_CLKCTRL_VERSION (0x00000200) 472 473 #define BP_CLKCTRL_VERSION_MAJOR 24 474 #define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 475 #define BF_CLKCTRL_VERSION_MAJOR(v) \ 476 (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) 477 #define BP_CLKCTRL_VERSION_MINOR 16 478 #define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 479 #define BF_CLKCTRL_VERSION_MINOR(v) \ 480 (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) 481 #define BP_CLKCTRL_VERSION_STEP 0 482 #define BM_CLKCTRL_VERSION_STEP 0x0000FFFF 483 #define BF_CLKCTRL_VERSION_STEP(v) \ 484 (((v) << 0) & BM_CLKCTRL_VERSION_STEP) 485 486 #endif /* __REGS_CLKCTRL_MX28_H__ */ 487