1 /* 2 * drivers/net/big_sur_ge.h - Driver for PMC-Sierra Big Sur 3 * ethernet ports 4 * 5 * Copyright (C) 2003, 2004 PMC-Sierra Inc. 6 * Author : Manish Lachwani (lachwani@pmc-sierra.com) 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 2 11 * of the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 21 * 22 */ 23 24 #ifndef __BIG_SUR_GE_H__ 25 #define __BIG_SUR_GE_H__ 26 27 #include <linux/config.h> 28 #include <linux/version.h> 29 #include <linux/module.h> 30 #include <linux/kernel.h> 31 #include <linux/config.h> 32 #include <linux/spinlock.h> 33 #include <linux/types.h> 34 35 #define BIG_SUR_DEVICE_NAME "big sur" 36 #define BIG_SUR_DEVICE_DESC "Big Sur Ethernet 10/100 MAC" 37 38 #define BIG_SUR_GE_BASE (0x1b000000 | KSEG1) 39 40 #define BIG_SUR_GE_WRITE(ofs,data) \ 41 *(volatile u32 *)(BIG_SUR_GE_BASE+(ofs)) = data 42 43 #define BIG_SUR_GE_READ(ofs) \ 44 *(volatile u32 *)(BIG_SUR_GE_BASE+(ofs)) 45 46 #define BIG_SUR_GE_READ_REG(base_addr, reg_offset) \ 47 BIG_SUR_GE_READ(base_addr + reg_offset) 48 49 #define BIG_SUR_GE_WRITE_REG(base_addr, reg_offset, data) \ 50 BIG_SUR_GE_WRITE(base_addr + reg_offset, data) 51 52 #define BIG_SUR_GE_CONTROL_REG(base_addr, mask) \ 53 BIG_SUR_GE_WRITE(base_addr + BIG_SUR_GE_ECR_OFFSET, mask) 54 55 #define BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT 4UL 56 57 /* IPIF specific defines */ 58 #define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */ 59 #define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */ 60 #define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */ 61 #define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */ 62 #define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */ 63 #define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ 64 #define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */ 65 #define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ 66 #define XIIF_V123B_RESET_MASK 0xAUL 67 #define XIIF_V123B_ERROR_MASK 0x1UL 68 69 /* Options for the MAC */ 70 #define BIG_SUR_GE_UNICAST_OPTION 0x00000001 71 #define BIG_SUR_GE_BROADCAST_OPTION 0x00000002 72 #define BIG_SUR_GE_PROMISC_OPTION 0x00000004 73 #define BIG_SUR_GE_FDUPLEX_OPTION 0x00000008 74 #define BIG_SUR_GE_POLLED_OPTION 0x00000010 75 #define BIG_SUR_GE_LOOPBACK_OPTION 0x00000020 76 #define BIG_SUR_GE_FLOW_CONTROL_OPTION 0x00000080 77 #define BIG_SUR_GE_INSERT_PAD_OPTION 0x00000100 78 #define BIG_SUR_GE_INSERT_FCS_OPTION 0x00000200 79 #define BIG_SUR_GE_INSERT_ADDR_OPTION 0x00000400 80 #define BIG_SUR_GE_OVWRT_ADDR_OPTION 0x00000800 81 #define BIG_SUR_GE_STRIP_PAD_FCS_OPTION 0x00002000 82 #define BIG_SUR_GE_MULTICAST_OPTION 0x00000040 83 #define BIG_SUR_GE_FLOW_CONTROL_OPTION 0x00000080 84 #define BIG_SUR_GE_INSERT_PAD_OPTION 0x00000100 85 #define BIG_SUR_GE_INSERT_FCS_OPTION 0x00000200 86 #define BIG_SUR_GE_INSERT_ADDR_OPTION 0x00000400 87 #define BIG_SUR_GE_OVWRT_ADDR_OPTION 0x00000800 88 #define BIG_SUR_GE_STRIP_PAD_OPTION 0x00001000 89 #define BIG_SUR_GE_STRIP_FCS_OPTION 0x00002000 90 91 #define BIG_SUR_GE_MTU 1500 /* max size of Ethernet frame */ 92 #define BIG_SUR_GE_HDR_SIZE 14 /* size of Ethernet header */ 93 #define BIG_SUR_GE_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */ 94 #define BIG_SUR_GE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ 95 #define BIG_SUR_GE_MAX_FRAME_SIZE \ 96 (BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_SIZE + BIG_SUR_GE_TRL_SIZE) 97 98 #define BIG_SUR_GE_MAX_VLAN_FRAME_SIZE \ 99 (BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_VLAN_SIZE + BIG_SUR_GE_TRL_SIZE) 100 101 /* FIFO Specific Defines */ 102 #define BIG_SUR_GE_RESET_REG_OFFSET 0UL 103 #define BIG_SUR_GE_MODULE_INFO_REG_OFFSET 0UL 104 #define BIG_SUR_GE_COUNT_STATUS_REG_OFFSET 4UL 105 #define BIG_SUR_GE_RESET_FIFO_MASK 0x0000000A 106 #define BIG_SUR_GE_COUNT_MASK 0x0000FFFF 107 #define BIG_SUR_GE_DEADLOCK_MASK 0x20000000 108 #define BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK 0x40000000 109 #define BIG_SUR_GE_EMPTY_FULL_MASK 0x80000000 110 111 #define BIG_SUR_GE_FIFO_RESET(fifo) \ 112 BIG_SUR_GE_WRITE((fifo)->reg_base_addr + \ 113 BIG_SUR_GE_RESET_REG_OFFSET, BIG_SUR_GE_RESET_FIFO_MASK) 114 115 #define BIG_SUR_GE_GET_COUNT(fifo) \ 116 (BIG_SUR_GE_READ((fifo)->reg_base_addr + \ 117 BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & BIG_SUR_GE_COUNT_MASK) 118 119 #define BIG_SUR_GE_IS_ALMOST_EMPTY(fifo) \ 120 (BIG_SUR_GE_READ(fifo->reg_base_addr + \ 121 BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 122 BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK) 123 124 #define BIG_SUR_GE_IS_ALMOST_FULL(fifo) \ 125 (BIG_SUR_GE_READ(fifo->reg_base_addr + \ 126 BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 127 BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK) 128 129 #define BIG_SUR_GE_IS_EMPTY(fifo) \ 130 (BIG_SUR_GE_READ(fifo->reg_base_addr + \ 131 BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 132 BIG_SUR_GE_EMPTY_FULL_MASK) 133 134 #define BIG_SUR_GE_IS_FULL(fifo) \ 135 (BIG_SUR_GE_READ(fifo->reg_base_addr + \ 136 BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 137 BIG_SUR_GE_EMPTY_FULL_MASK) 138 139 #define BIG_SUR_GE_IS_DEADLOCKED(fifo) \ 140 (BIG_SUR_GE_READ((fifo)->reg_base_addr + \ 141 BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ 142 BIG_SUR_GE_DEADLOCK_MASK) 143 144 /* Device Config */ 145 typedef struct _big_sur_ge_config { 146 u16 device_id; 147 u32 base_address; 148 u32 has_counters; 149 u32 has_sg_dma; 150 u8 dma_config; 151 u32 has_mii; 152 } big_sur_ge_config; 153 154 /* Send and Receive DMA channel */ 155 typedef struct _xdma_channel_tag { 156 u32 reg_base_address; 157 u32 base_address; 158 u32 ready; 159 } xdma_channel; 160 161 /* Send and Receive Packet FIFO */ 162 typedef struct _packet_fifo { 163 u32 reg_base_addr; 164 u32 ready_status; 165 u32 data_base_address; 166 } packet_fifo; 167 168 /* Big Sur GE driver structure */ 169 typedef struct _big_sur_ge { 170 u32 base_address; 171 u32 started; 172 u32 ready; 173 u32 polled; 174 u32 dma_sg; 175 u8 dma_config; 176 u32 has_mii; 177 u32 has_mcast_hash_table; 178 /* For the FIFO and simple DMA case only */ 179 packet_fifo recv_fifo; 180 packet_fifo send_fifo; 181 xdma_channel recv_channel; 182 xdma_channel send_channel; 183 184 u8 has_dma; 185 } big_sur_ge; 186 187 /* Offset of the MAC registers from the IPIF base address */ 188 #define BIG_SUR_GE_REG_OFFSET 0x1100UL 189 190 /* 191 * Register offsets for the Ethernet MAC. Each register is 32 bits. 192 */ 193 #define BIG_SUR_GE_EMIR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x0) /* EMAC Module ID */ 194 #define BIG_SUR_GE_ECR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x4) /* MAC Control */ 195 #define BIG_SUR_GE_IFGP_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x8) /* Interframe Gap */ 196 #define BIG_SUR_GE_SAH_OFFSET (BIG_SUR_GE_REG_OFFSET + 0xC) /* Station addr, high */ 197 #define BIG_SUR_GE_SAL_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x10)/* Station addr, low */ 198 #define BIG_SUR_GE_MGTCR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x14)/* MII mgmt control */ 199 #define BIG_SUR_GE_MGTDR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x18)/* MII mgmt data */ 200 #define BIG_SUR_GE_RPLR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x1C)/* Rx packet length */ 201 #define BIG_SUR_GE_TPLR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x20)/* Tx packet length */ 202 #define BIG_SUR_GE_TSR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x24)/* Tx status */ 203 #define BIG_SUR_GE_RMFC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x28)/* Rx missed frames */ 204 #define BIG_SUR_GE_RCC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x2C)/* Rx collisions */ 205 #define BIG_SUR_GE_RFCSEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x30)/* Rx FCS errors */ 206 #define BIG_SUR_GE_RAEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x34)/* Rx alignment errors */ 207 208 /* Transmit excess deferral cnt */ 209 #define BIG_SUR_GE_TEDC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x38) 210 211 /* Interrupt Status Register */ 212 #define BIG_SUR_GE_ISR_OFFSET 0x20UL 213 214 /* Send and Receive DMA Channel */ 215 #define BIG_SUR_GE_DMA_OFFSET 0x2300UL 216 #define BIG_SUR_GE_DMA_SEND_OFFSET (BIG_SUR_GE_DMA_OFFSET + 0x0) 217 #define BIG_SUR_GE_DMA_RECV_OFFSET (BIG_SUR_GE_DMA_OFFSET + 0x40) 218 219 /* Packet FIFO */ 220 #define BIG_SUR_GE_PFIFO_OFFSET 0x2000UL 221 #define BIG_SUR_GE_PFIFO_TXREG_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x0) 222 #define BIG_SUR_GE_PFIFO_RXREG_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x10) 223 #define BIG_SUR_GE_PFIFO_TXDATA_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x100) 224 #define BIG_SUR_GE_PFIFO_RXDATA_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x200) 225 226 /* 227 * EMAC Module Identification Register (EMIR) 228 */ 229 #define BIG_SUR_GE_EMIR_VERSION_MASK 0xFFFF0000UL /* Device version */ 230 #define BIG_SUR_GE_EMIR_TYPE_MASK 0x0000FF00UL /* Device type */ 231 232 /* 233 * EMAC Control Register (ECR) 234 */ 235 #define BIG_SUR_GE_ECR_FULL_DUPLEX_MASK 0x80000000 /* Full duplex mode */ 236 #define BIG_SUR_GE_ECR_XMIT_RESET_MASK 0x40000000 /* Reset transmitter */ 237 #define BIG_SUR_GE_ECR_XMIT_ENABLE_MASK 0x20000000 /* Enable transmitter */ 238 #define BIG_SUR_GE_ECR_RECV_RESET_MASK 0x10000000 /* Reset receiver */ 239 #define BIG_SUR_GE_ECR_RECV_ENABLE_MASK 0x08000000 /* Enable receiver */ 240 #define BIG_SUR_GE_ECR_PHY_ENABLE_MASK 0x04000000 /* Enable PHY */ 241 #define BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK 0x02000000 /* Enable xmit pad insert */ 242 #define BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK 0x01000000 /* Enable xmit FCS insert */ 243 #define BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK 0x00800000 /* Enable xmit source addr insertion */ 244 #define BIG_SUR_GE_ECR_XMIT_ERROR_INSERT_MASK 0x00400000 /* Insert xmit error */ 245 #define BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK 0x00200000 /* Enable xmit source addr overwrite */ 246 #define BIG_SUR_GE_ECR_LOOPBACK_MASK 0x00100000 /* Enable internal loopback */ 247 #define BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK 0x00080000 /* Enable recv pad strip */ 248 #define BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK 0x00040000 /* Enable recv FCS strip */ 249 #define BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK 0x00080000 /* Enable recv pad/fcs strip */ 250 #define BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK 0x00020000 /* Enable unicast addr */ 251 #define BIG_SUR_GE_ECR_MULTI_ENABLE_MASK 0x00010000 /* Enable multicast addr */ 252 #define BIG_SUR_GE_ECR_BROAD_ENABLE_MASK 0x00008000 /* Enable broadcast addr */ 253 #define BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK 0x00004000 /* Enable promiscuous mode */ 254 #define BIG_SUR_GE_ECR_RECV_ALL_MASK 0x00002000 /* Receive all frames */ 255 #define BIG_SUR_GE_ECR_RESERVED2_MASK 0x00001000 /* Reserved */ 256 #define BIG_SUR_GE_ECR_MULTI_HASH_ENABLE_MASK 0x00000800 /* Enable multicast hash */ 257 #define BIG_SUR_GE_ECR_PAUSE_FRAME_MASK 0x00000400 /* Interpret pause frames */ 258 #define BIG_SUR_GE_ECR_CLEAR_HASH_MASK 0x00000200 /* Clear hash table */ 259 #define BIG_SUR_GE_ECR_ADD_HASH_ADDR_MASK 0x00000100 /* Add hash table address */ 260 261 /* 262 * Interframe Gap Register (IFGR) 263 */ 264 #define BIG_SUR_GE_IFGP_PART1_MASK 0xF8000000 /* Interframe Gap Part1 */ 265 #define BIG_SUR_GE_IFGP_PART1_SHIFT 27 266 #define BIG_SUR_GE_IFGP_PART2_MASK 0x07C00000 /* Interframe Gap Part2 */ 267 #define BIG_SUR_GE_IFGP_PART2_SHIFT 22 268 269 /* 270 * Station Address High Register (SAH) 271 */ 272 #define BIG_SUR_GE_SAH_ADDR_MASK 0x0000FFFF /* Station address high bytes */ 273 274 /* 275 * Station Address Low Register (SAL) 276 */ 277 #define BIG_SUR_GE_SAL_ADDR_MASK 0xFFFFFFFF /* Station address low bytes */ 278 279 /* 280 * MII Management Control Register (MGTCR) 281 */ 282 #define BIG_SUR_GE_MGTCR_START_MASK 0x80000000 /* Start/Busy */ 283 #define BIG_SUR_GE_MGTCR_RW_NOT_MASK 0x40000000 /* Read/Write Not (direction) */ 284 #define BIG_SUR_GE_MGTCR_PHY_ADDR_MASK 0x3E000000 /* PHY address */ 285 #define BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT 25 /* PHY address shift */ 286 #define BIG_SUR_GE_MGTCR_REG_ADDR_MASK 0x01F00000 /* Register address */ 287 #define BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT 20 /* Register addr shift */ 288 #define BIG_SUR_GE_MGTCR_MII_ENABLE_MASK 0x00080000 /* Enable MII from EMAC */ 289 #define BIG_SUR_GE_MGTCR_RD_ERROR_MASK 0x00040000 /* MII mgmt read error */ 290 291 /* 292 * MII Management Data Register (MGTDR) 293 */ 294 #define BIG_SUR_GE_MGTDR_DATA_MASK 0x0000FFFF /* MII data */ 295 296 /* 297 * Receive Packet Length Register (RPLR) 298 */ 299 #define BIG_SUR_GE_RPLR_LENGTH_MASK 0x0000FFFF /* Receive packet length */ 300 301 /* 302 * Transmit Packet Length Register (TPLR) 303 */ 304 #define BIG_SUR_GE_TPLR_LENGTH_MASK 0x0000FFFF /* Transmit packet length */ 305 306 /* 307 * Transmit Status Register (TSR) 308 */ 309 #define BIG_SUR_GE_TSR_EXCESS_DEFERRAL_MASK 0x80000000 /* Transmit excess deferral */ 310 #define BIG_SUR_GE_TSR_FIFO_UNDERRUN_MASK 0x40000000 /* Packet FIFO underrun */ 311 #define BIG_SUR_GE_TSR_ATTEMPTS_MASK 0x3E000000 /* Transmission attempts */ 312 #define BIG_SUR_GE_TSR_LATE_COLLISION_MASK 0x01000000 /* Transmit late collision */ 313 314 /* Receive Missed Frame Count (RMFC) */ 315 #define BIG_SUR_GE_RMFC_DATA_MASK 0x0000FFFF 316 317 /* Receive Collision Count (RCC) */ 318 #define BIG_SUR_GE_RCC_DATA_MASK 0x0000FFFF 319 320 /* Receive FCS Error Count (RFCSEC) */ 321 #define BIG_SUR_GE_RFCSEC_DATA_MASK 0x0000FFFF 322 323 /* Receive Alignment Error Count (RALN) */ 324 #define BIG_SUR_GE_RAEC_DATA_MASK 0x0000FFFF 325 326 /* Transmit Excess Deferral Count (TEDC) */ 327 #define BIG_SUR_GE_TEDC_DATA_MASK 0x0000FFFF 328 329 /* 330 * EMAC Interrupt Registers (Status and Enable) masks. These registers are 331 * part of the IPIF IP Interrupt registers 332 */ 333 #define BIG_SUR_GE_EIR_XMIT_DONE_MASK 0x00000001 /* Xmit complete */ 334 #define BIG_SUR_GE_EIR_RECV_DONE_MASK 0x00000002 /* Recv complete */ 335 #define BIG_SUR_GE_EIR_XMIT_ERROR_MASK 0x00000004 /* Xmit error */ 336 #define BIG_SUR_GE_EIR_RECV_ERROR_MASK 0x00000008 /* Recv error */ 337 #define BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010 /* Xmit status fifo empty */ 338 #define BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020 /* Recv length fifo empty */ 339 #define BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK 0x00000040 /* Xmit length fifo full */ 340 #define BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK 0x00000080 /* Recv length fifo overrun */ 341 #define BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK 0x00000100 /* Recv length fifo underrun */ 342 #define BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK 0x00000200 /* Xmit status fifo overrun */ 343 #define BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400 /* Transmit status fifo underrun */ 344 #define BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK 0x00000800 /* Transmit length fifo overrun */ 345 #define BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000 /* Transmit length fifo underrun */ 346 #define BIG_SUR_GE_EIR_XMIT_PAUSE_MASK 0x00002000 /* Transmit pause pkt received */ 347 #define BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK 0x00004000 /* Receive data fifo overrun */ 348 #define BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK 0x00008000 /* Receive missed frame error */ 349 #define BIG_SUR_GE_EIR_RECV_COLLISION_MASK 0x00010000 /* Receive collision error */ 350 #define BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK 0x00020000 /* Receive FCS error */ 351 #define BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK 0x00040000 /* Receive length field error */ 352 #define BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK 0x00080000 /* Receive short frame error */ 353 #define BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK 0x00100000 /* Receive long frame error */ 354 #define BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK 0x00200000 /* Receive alignment error */ 355 356 /* Enable the MAC unit */ 357 #define big_sur_ge_mac_enable(base_address) \ 358 { \ 359 u32 control; \ 360 control = BIG_SUR_GE_READ(base_address + \ 361 BIG_SUR_GE_ECR_OFFSET); \ 362 control &= ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK | \ 363 BIG_SUR_GE_ECR_RECV_RESET_MASK); \ 364 control |= (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | \ 365 BIG_SUR_GE_ECR_RECV_ENABLE_MASK); \ 366 BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ 367 } 368 369 /* Disable the MAC unit */ 370 #define big_sur_ge_mac_disable(base_address) \ 371 { \ 372 u32 control; \ 373 control = BIG_SUR_GE_READ(base_address + \ 374 BIG_SUR_GE_ECR_OFFSET); \ 375 control &= ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | \ 376 BIG_SUR_GE_ECR_RECV_ENABLE_MASK); \ 377 BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ 378 } 379 380 /* Check if the Tx is done */ 381 #define big_sur_ge_tx_done(base_address) \ 382 (BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) \ 383 & BIG_SUR_GE_EIR_XMIT_DONE_MASK) 384 385 386 /* Check if Rx FIFO is empty */ 387 #define big_sur_ge_rx_empty(base_address) \ 388 (!(BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) \ 389 & BIG_SUR_GE_EIR_RECV_DONE_MASK)) 390 391 /* Reset the MAC PHY */ 392 #define big_sur_ge_reset_phy(base_address) \ 393 { \ 394 u32 control; \ 395 control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \ 396 control &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK); \ 397 BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ 398 control |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK; \ 399 BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ 400 } 401 402 #define BIG_SUR_GE_RST_REG_OFFSET 0 /* reset register */ 403 #define BIG_SUR_GE_MI_REG_OFFSET 0 /* module information register */ 404 #define BIG_SUR_GE_DMAC_REG_OFFSET 4 /* DMA control register */ 405 #define BIG_SUR_GE_SA_REG_OFFSET 8 /* source address register */ 406 #define BIG_SUR_GE_DA_REG_OFFSET 12 /* destination address register */ 407 #define BIG_SUR_GE_LEN_REG_OFFSET 16 /* length register */ 408 #define BIG_SUR_GE_DMAS_REG_OFFSET 20 /* DMA status register */ 409 #define BIG_SUR_GE_BDA_REG_OFFSET 24 /* buffer descriptor address register */ 410 #define BIG_SUR_GE_SWCR_REG_OFFSET 28 /* software control register */ 411 #define BIG_SUR_GE_UPC_REG_OFFSET 32 /* unserviced packet count register */ 412 #define BIG_SUR_GE_PCT_REG_OFFSET 36 /* packet count threshold register */ 413 #define BIG_SUR_GE_PWB_REG_OFFSET 40 /* packet wait bound register */ 414 #define BIG_SUR_GE_IS_REG_OFFSET 44 /* interrupt status register */ 415 #define BIG_SUR_GE_IE_REG_OFFSET 48 /* interrupt enable register */ 416 417 #define BIG_SUR_GE_RESET_MASK 0x0000000A 418 419 /* Simple DMA register support */ 420 #define BIG_SUR_GE_DMACR_SOURCE_INCR_MASK 0x80000000UL /* increment source address */ 421 #define BIG_SUR_GE_DMACR_DEST_INCR_MASK 0x40000000UL /* increment dest address */ 422 #define BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK 0x20000000UL /* local source address */ 423 #define BIG_SUR_GE_DMACR_DEST_LOCAL_MASK 0x10000000UL /* local dest address */ 424 #define BIG_SUR_GE_DMACR_SG_DISABLE_MASK 0x08000000UL /* scatter gather disable */ 425 #define BIG_SUR_GE_DMASR_BUSY_MASK 0x80000000UL /* channel is busy */ 426 #define BIG_SUR_GE_DMASR_BUS_ERROR_MASK 0x40000000UL /* bus error occurred */ 427 #define BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK 0x20000000UL /* bus timeout occurred */ 428 429 /* Interrupts */ 430 #define BIG_SUR_GE_IPIF_EMAC_MASK 0x00000004UL /* MAC interrupt */ 431 #define BIG_SUR_GE_IPIF_SEND_DMA_MASK 0x00000008UL /* Send DMA interrupt */ 432 #define BIG_SUR_GE_IPIF_RECV_DMA_MASK 0x00000010UL /* Receive DMA interrupt */ 433 #define BIG_SUR_GE_IPIF_RECV_FIFO_MASK 0x00000020UL /* Receive FIFO interrupt */ 434 #define BIG_SUR_GE_IPIF_SEND_FIFO_MASK 0x00000040UL /* Send FIFO interrupt */ 435 436 #define BIG_SUR_GE_IPIF_FIFO_DFT_MASK (BIG_SUR_GE_IPIF_EMAC_MASK | \ 437 BIG_SUR_GE_IPIF_SEND_FIFO_MASK | \ 438 BIG_SUR_GE_IPIF_RECV_FIFO_MASK) 439 440 #define BIG_SUR_GE_IPIF_DMA_DEV_INTR_COUNT 7 /* Number of interrupt sources */ 441 #define BIG_SUR_GE_IPIF_FIFO_DEV_INTR_COUNT 5 /* Number of interrupt sources */ 442 #define BIG_SUR_GE_IPIF_DEVICE_INTR_COUNT 7 /* Number of interrupt sources */ 443 #define BIG_SUR_GE_IPIF_IP_INTR_COUNT 22 /* Number of MAC interrupts */ 444 445 /* A default interrupt mask for non-DMA operation (direct FIFOs) */ 446 #define BIG_SUR_GE_EIR_DFT_FIFO_MASK (BIG_SUR_GE_EIR_XMIT_DONE_MASK | \ 447 BIG_SUR_GE_EIR_RECV_DONE_MASK) 448 449 #endif 450