1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef LINUX_BCMA_REGS_H_
3 #define LINUX_BCMA_REGS_H_
4 
5 /* Some single registers are shared between many cores */
6 /* BCMA_CLKCTLST: ChipCommon (rev >= 20), PCIe, 80211 */
7 #define BCMA_CLKCTLST			0x01E0 /* Clock control and status */
8 #define  BCMA_CLKCTLST_FORCEALP		0x00000001 /* Force ALP request */
9 #define  BCMA_CLKCTLST_FORCEHT		0x00000002 /* Force HT request */
10 #define  BCMA_CLKCTLST_FORCEILP		0x00000004 /* Force ILP request */
11 #define  BCMA_CLKCTLST_HAVEALPREQ	0x00000008 /* ALP available request */
12 #define  BCMA_CLKCTLST_HAVEHTREQ	0x00000010 /* HT available request */
13 #define  BCMA_CLKCTLST_HWCROFF		0x00000020 /* Force HW clock request off */
14 #define  BCMA_CLKCTLST_HQCLKREQ		0x00000040 /* HQ Clock */
15 #define  BCMA_CLKCTLST_EXTRESREQ	0x00000700 /* Mask of external resource requests */
16 #define  BCMA_CLKCTLST_EXTRESREQ_SHIFT	8
17 #define  BCMA_CLKCTLST_HAVEALP		0x00010000 /* ALP available */
18 #define  BCMA_CLKCTLST_HAVEHT		0x00020000 /* HT available */
19 #define  BCMA_CLKCTLST_BP_ON_ALP	0x00040000 /* RO: running on ALP clock */
20 #define  BCMA_CLKCTLST_BP_ON_HT		0x00080000 /* RO: running on HT clock */
21 #define  BCMA_CLKCTLST_EXTRESST		0x07000000 /* Mask of external resource status */
22 #define  BCMA_CLKCTLST_EXTRESST_SHIFT	24
23 /* Is there any BCM4328 on BCMA bus? */
24 #define  BCMA_CLKCTLST_4328A0_HAVEHT	0x00010000 /* 4328a0 has reversed bits */
25 #define  BCMA_CLKCTLST_4328A0_HAVEALP	0x00020000 /* 4328a0 has reversed bits */
26 
27 /* Agent registers (common for every core) */
28 #define BCMA_OOB_SEL_OUT_A30		0x0100
29 #define BCMA_IOCTL			0x0408 /* IO control */
30 #define  BCMA_IOCTL_CLK			0x0001
31 #define  BCMA_IOCTL_FGC			0x0002
32 #define  BCMA_IOCTL_CORE_BITS		0x3FFC
33 #define  BCMA_IOCTL_PME_EN		0x4000
34 #define  BCMA_IOCTL_BIST_EN		0x8000
35 #define BCMA_IOST			0x0500 /* IO status */
36 #define  BCMA_IOST_CORE_BITS		0x0FFF
37 #define  BCMA_IOST_DMA64		0x1000
38 #define  BCMA_IOST_GATED_CLK		0x2000
39 #define  BCMA_IOST_BIST_ERROR		0x4000
40 #define  BCMA_IOST_BIST_DONE		0x8000
41 #define BCMA_RESET_CTL			0x0800
42 #define  BCMA_RESET_CTL_RESET		0x0001
43 #define BCMA_RESET_ST			0x0804
44 
45 #define BCMA_NS_ROM_IOST_BOOT_DEV_MASK	0x0003
46 #define BCMA_NS_ROM_IOST_BOOT_DEV_NOR	0x0000
47 #define BCMA_NS_ROM_IOST_BOOT_DEV_NAND	0x0001
48 #define BCMA_NS_ROM_IOST_BOOT_DEV_ROM	0x0002
49 
50 /* BCMA PCI config space registers. */
51 #define BCMA_PCI_PMCSR			0x44
52 #define  BCMA_PCI_PE			0x100
53 #define BCMA_PCI_BAR0_WIN		0x80	/* Backplane address space 0 */
54 #define BCMA_PCI_BAR1_WIN		0x84	/* Backplane address space 1 */
55 #define BCMA_PCI_SPROMCTL		0x88	/* SPROM control */
56 #define  BCMA_PCI_SPROMCTL_WE		0x10	/* SPROM write enable */
57 #define BCMA_PCI_BAR1_CONTROL		0x8c	/* Address space 1 burst control */
58 #define BCMA_PCI_IRQS			0x90	/* PCI interrupts */
59 #define BCMA_PCI_IRQMASK		0x94	/* PCI IRQ control and mask (pcirev >= 6 only) */
60 #define BCMA_PCI_BACKPLANE_IRQS		0x98	/* Backplane Interrupts */
61 #define BCMA_PCI_BAR0_WIN2		0xAC
62 #define BCMA_PCI_GPIO_IN		0xB0	/* GPIO Input (pcirev >= 3 only) */
63 #define BCMA_PCI_GPIO_OUT		0xB4	/* GPIO Output (pcirev >= 3 only) */
64 #define BCMA_PCI_GPIO_OUT_ENABLE	0xB8	/* GPIO Output Enable/Disable (pcirev >= 3 only) */
65 #define  BCMA_PCI_GPIO_SCS		0x10	/* PCI config space bit 4 for 4306c0 slow clock source */
66 #define  BCMA_PCI_GPIO_HWRAD		0x20	/* PCI config space GPIO 13 for hw radio disable */
67 #define  BCMA_PCI_GPIO_XTAL		0x40	/* PCI config space GPIO 14 for Xtal powerup */
68 #define  BCMA_PCI_GPIO_PLL		0x80	/* PCI config space GPIO 15 for PLL powerdown */
69 
70 #define BCMA_PCIE2_BAR0_WIN2		0x70
71 
72 /* SiliconBackplane Address Map.
73  * All regions may not exist on all chips.
74  */
75 #define BCMA_SOC_SDRAM_BASE		0x00000000U	/* Physical SDRAM */
76 #define BCMA_SOC_PCI_MEM		0x08000000U	/* Host Mode sb2pcitranslation0 (64 MB) */
77 #define BCMA_SOC_PCI_MEM_SZ		(64 * 1024 * 1024)
78 #define BCMA_SOC_PCI_CFG		0x0c000000U	/* Host Mode sb2pcitranslation1 (64 MB) */
79 #define BCMA_SOC_SDRAM_SWAPPED		0x10000000U	/* Byteswapped Physical SDRAM */
80 #define BCMA_SOC_SDRAM_R2		0x80000000U	/* Region 2 for sdram (512 MB) */
81 
82 
83 #define BCMA_SOC_PCI_DMA		0x40000000U	/* Client Mode sb2pcitranslation2 (1 GB) */
84 #define BCMA_SOC_PCI_DMA2		0x80000000U	/* Client Mode sb2pcitranslation2 (1 GB) */
85 #define BCMA_SOC_PCI_DMA_SZ		0x40000000U	/* Client Mode sb2pcitranslation2 size in bytes */
86 #define BCMA_SOC_PCIE_DMA_L32		0x00000000U	/* PCIE Client Mode sb2pcitranslation2
87 							 * (2 ZettaBytes), low 32 bits
88 							 */
89 #define BCMA_SOC_PCIE_DMA_H32		0x80000000U	/* PCIE Client Mode sb2pcitranslation2
90 							 * (2 ZettaBytes), high 32 bits
91 							 */
92 
93 #define BCMA_SOC_PCI1_MEM		0x40000000U	/* Host Mode sb2pcitranslation0 (64 MB) */
94 #define BCMA_SOC_PCI1_CFG		0x44000000U	/* Host Mode sb2pcitranslation1 (64 MB) */
95 #define BCMA_SOC_PCIE1_DMA_H32		0xc0000000U	/* PCIE Client Mode sb2pcitranslation2
96 							 * (2 ZettaBytes), high 32 bits
97 							 */
98 
99 #define BCMA_SOC_FLASH1			0x1fc00000	/* MIPS Flash Region 1 */
100 #define BCMA_SOC_FLASH1_SZ		0x00400000	/* MIPS Size of Flash Region 1 */
101 #define BCMA_SOC_FLASH2			0x1c000000	/* Flash Region 2 (region 1 shadowed here) */
102 #define BCMA_SOC_FLASH2_SZ		0x02000000	/* Size of Flash Region 2 */
103 
104 #endif /* LINUX_BCMA_REGS_H_ */
105