1 #ifndef B43legacy_H_
2 #define B43legacy_H_
3
4 #include <linux/hw_random.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/interrupt.h>
8 #include <linux/stringify.h>
9 #include <linux/netdevice.h>
10 #include <linux/pci.h>
11 #include <asm/atomic.h>
12 #include <linux/io.h>
13
14 #include <linux/ssb/ssb.h>
15 #include <linux/ssb/ssb_driver_chipcommon.h>
16
17 #include <linux/wireless.h>
18 #include <net/mac80211.h>
19
20 #include "debugfs.h"
21 #include "leds.h"
22 #include "rfkill.h"
23 #include "phy.h"
24
25
26 /* The unique identifier of the firmware that's officially supported by this
27 * driver version. */
28 #define B43legacy_SUPPORTED_FIRMWARE_ID "FW10"
29
30 #define B43legacy_IRQWAIT_MAX_RETRIES 20
31
32 /* MMIO offsets */
33 #define B43legacy_MMIO_DMA0_REASON 0x20
34 #define B43legacy_MMIO_DMA0_IRQ_MASK 0x24
35 #define B43legacy_MMIO_DMA1_REASON 0x28
36 #define B43legacy_MMIO_DMA1_IRQ_MASK 0x2C
37 #define B43legacy_MMIO_DMA2_REASON 0x30
38 #define B43legacy_MMIO_DMA2_IRQ_MASK 0x34
39 #define B43legacy_MMIO_DMA3_REASON 0x38
40 #define B43legacy_MMIO_DMA3_IRQ_MASK 0x3C
41 #define B43legacy_MMIO_DMA4_REASON 0x40
42 #define B43legacy_MMIO_DMA4_IRQ_MASK 0x44
43 #define B43legacy_MMIO_DMA5_REASON 0x48
44 #define B43legacy_MMIO_DMA5_IRQ_MASK 0x4C
45 #define B43legacy_MMIO_MACCTL 0x120 /* MAC control */
46 #define B43legacy_MMIO_MACCMD 0x124 /* MAC command */
47 #define B43legacy_MMIO_GEN_IRQ_REASON 0x128
48 #define B43legacy_MMIO_GEN_IRQ_MASK 0x12C
49 #define B43legacy_MMIO_RAM_CONTROL 0x130
50 #define B43legacy_MMIO_RAM_DATA 0x134
51 #define B43legacy_MMIO_PS_STATUS 0x140
52 #define B43legacy_MMIO_RADIO_HWENABLED_HI 0x158
53 #define B43legacy_MMIO_SHM_CONTROL 0x160
54 #define B43legacy_MMIO_SHM_DATA 0x164
55 #define B43legacy_MMIO_SHM_DATA_UNALIGNED 0x166
56 #define B43legacy_MMIO_XMITSTAT_0 0x170
57 #define B43legacy_MMIO_XMITSTAT_1 0x174
58 #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
59 #define B43legacy_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
60 #define B43legacy_MMIO_TSF_CFP_REP 0x188
61 #define B43legacy_MMIO_TSF_CFP_START 0x18C
62 /* 32-bit DMA */
63 #define B43legacy_MMIO_DMA32_BASE0 0x200
64 #define B43legacy_MMIO_DMA32_BASE1 0x220
65 #define B43legacy_MMIO_DMA32_BASE2 0x240
66 #define B43legacy_MMIO_DMA32_BASE3 0x260
67 #define B43legacy_MMIO_DMA32_BASE4 0x280
68 #define B43legacy_MMIO_DMA32_BASE5 0x2A0
69 /* 64-bit DMA */
70 #define B43legacy_MMIO_DMA64_BASE0 0x200
71 #define B43legacy_MMIO_DMA64_BASE1 0x240
72 #define B43legacy_MMIO_DMA64_BASE2 0x280
73 #define B43legacy_MMIO_DMA64_BASE3 0x2C0
74 #define B43legacy_MMIO_DMA64_BASE4 0x300
75 #define B43legacy_MMIO_DMA64_BASE5 0x340
76 /* PIO */
77 #define B43legacy_MMIO_PIO1_BASE 0x300
78 #define B43legacy_MMIO_PIO2_BASE 0x310
79 #define B43legacy_MMIO_PIO3_BASE 0x320
80 #define B43legacy_MMIO_PIO4_BASE 0x330
81
82 #define B43legacy_MMIO_PHY_VER 0x3E0
83 #define B43legacy_MMIO_PHY_RADIO 0x3E2
84 #define B43legacy_MMIO_PHY0 0x3E6
85 #define B43legacy_MMIO_ANTENNA 0x3E8
86 #define B43legacy_MMIO_CHANNEL 0x3F0
87 #define B43legacy_MMIO_CHANNEL_EXT 0x3F4
88 #define B43legacy_MMIO_RADIO_CONTROL 0x3F6
89 #define B43legacy_MMIO_RADIO_DATA_HIGH 0x3F8
90 #define B43legacy_MMIO_RADIO_DATA_LOW 0x3FA
91 #define B43legacy_MMIO_PHY_CONTROL 0x3FC
92 #define B43legacy_MMIO_PHY_DATA 0x3FE
93 #define B43legacy_MMIO_MACFILTER_CONTROL 0x420
94 #define B43legacy_MMIO_MACFILTER_DATA 0x422
95 #define B43legacy_MMIO_RCMTA_COUNT 0x43C /* Receive Match Transmitter Addr */
96 #define B43legacy_MMIO_RADIO_HWENABLED_LO 0x49A
97 #define B43legacy_MMIO_GPIO_CONTROL 0x49C
98 #define B43legacy_MMIO_GPIO_MASK 0x49E
99 #define B43legacy_MMIO_TSF_CFP_PRETBTT 0x612
100 #define B43legacy_MMIO_TSF_0 0x632 /* core rev < 3 only */
101 #define B43legacy_MMIO_TSF_1 0x634 /* core rev < 3 only */
102 #define B43legacy_MMIO_TSF_2 0x636 /* core rev < 3 only */
103 #define B43legacy_MMIO_TSF_3 0x638 /* core rev < 3 only */
104 #define B43legacy_MMIO_RNG 0x65A
105 #define B43legacy_MMIO_POWERUP_DELAY 0x6A8
106
107 /* SPROM boardflags_lo values */
108 #define B43legacy_BFL_PACTRL 0x0002
109 #define B43legacy_BFL_RSSI 0x0008
110 #define B43legacy_BFL_EXTLNA 0x1000
111
112 /* GPIO register offset, in both ChipCommon and PCI core. */
113 #define B43legacy_GPIO_CONTROL 0x6c
114
115 /* SHM Routing */
116 #define B43legacy_SHM_SHARED 0x0001
117 #define B43legacy_SHM_WIRELESS 0x0002
118 #define B43legacy_SHM_HW 0x0004
119 #define B43legacy_SHM_UCODE 0x0300
120
121 /* SHM Routing modifiers */
122 #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
123 #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
124 #define B43legacy_SHM_AUTOINC_RW (B43legacy_SHM_AUTOINC_R | \
125 B43legacy_SHM_AUTOINC_W)
126
127 /* Misc SHM_SHARED offsets */
128 #define B43legacy_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
129 #define B43legacy_SHM_SH_HOSTFLO 0x005E /* Hostflags ucode opts (low) */
130 #define B43legacy_SHM_SH_HOSTFHI 0x0060 /* Hostflags ucode opts (high) */
131 /* SHM_SHARED crypto engine */
132 #define B43legacy_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block */
133 /* SHM_SHARED beacon/AP variables */
134 #define B43legacy_SHM_SH_DTIMP 0x0012 /* DTIM period */
135 #define B43legacy_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
136 #define B43legacy_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
137 #define B43legacy_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
138 #define B43legacy_SHM_SH_TIMPOS 0x001E /* TIM position in beacon */
139 #define B43legacy_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word */
140 /* SHM_SHARED ACK/CTS control */
141 #define B43legacy_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word */
142 /* SHM_SHARED probe response variables */
143 #define B43legacy_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
144 #define B43legacy_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
145 #define B43legacy_SHM_SH_PRPHYCTL 0x0188 /* Probe Resp PHY TX control */
146 /* SHM_SHARED rate tables */
147 #define B43legacy_SHM_SH_OFDMDIRECT 0x0480 /* Pointer to OFDM direct map */
148 #define B43legacy_SHM_SH_OFDMBASIC 0x04A0 /* Pointer to OFDM basic rate map */
149 #define B43legacy_SHM_SH_CCKDIRECT 0x04C0 /* Pointer to CCK direct map */
150 #define B43legacy_SHM_SH_CCKBASIC 0x04E0 /* Pointer to CCK basic rate map */
151 /* SHM_SHARED microcode soft registers */
152 #define B43legacy_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
153 #define B43legacy_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
154 #define B43legacy_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
155 #define B43legacy_SHM_SH_UCODETIME 0x0006 /* Microcode time */
156 #define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
157 #define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
158
159 #define B43legacy_UCODEFLAGS_OFFSET 0x005E
160
161 /* Hardware Radio Enable masks */
162 #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
163 #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
164
165 /* HostFlags. See b43legacy_hf_read/write() */
166 #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
167 #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
168 #define B43legacy_HF_OFDMPABOOST 0x00000040 /* Enable PA boost OFDM */
169 #define B43legacy_HF_EDCF 0x00000100 /* on if WME/MAC suspended */
170
171 /* MacFilter offsets. */
172 #define B43legacy_MACFILTER_SELF 0x0000
173 #define B43legacy_MACFILTER_BSSID 0x0003
174 #define B43legacy_MACFILTER_MAC 0x0010
175
176 /* PHYVersioning */
177 #define B43legacy_PHYTYPE_B 0x01
178 #define B43legacy_PHYTYPE_G 0x02
179
180 /* PHYRegisters */
181 #define B43legacy_PHY_G_LO_CONTROL 0x0810
182 #define B43legacy_PHY_ILT_G_CTRL 0x0472
183 #define B43legacy_PHY_ILT_G_DATA1 0x0473
184 #define B43legacy_PHY_ILT_G_DATA2 0x0474
185 #define B43legacy_PHY_G_PCTL 0x0029
186 #define B43legacy_PHY_RADIO_BITFIELD 0x0401
187 #define B43legacy_PHY_G_CRS 0x0429
188 #define B43legacy_PHY_NRSSILT_CTRL 0x0803
189 #define B43legacy_PHY_NRSSILT_DATA 0x0804
190
191 /* RadioRegisters */
192 #define B43legacy_RADIOCTL_ID 0x01
193
194 /* MAC Control bitfield */
195 #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
196 #define B43legacy_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
197 #define B43legacy_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
198 #define B43legacy_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
199 #define B43legacy_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
200 #define B43legacy_MACCTL_BE 0x00010000 /* Big Endian mode */
201 #define B43legacy_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
202 #define B43legacy_MACCTL_AP 0x00040000 /* AccessPoint mode */
203 #define B43legacy_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
204 #define B43legacy_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
205 #define B43legacy_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep bad PLCP frames */
206 #define B43legacy_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
207 #define B43legacy_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
208 #define B43legacy_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
209 #define B43legacy_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
210 #define B43legacy_MACCTL_AWAKE 0x04000000 /* Device is awake */
211 #define B43legacy_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
212 #define B43legacy_MACCTL_GMODE 0x80000000 /* G Mode */
213
214 /* MAC Command bitfield */
215 #define B43legacy_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
216 #define B43legacy_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
217 #define B43legacy_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
218 #define B43legacy_MACCMD_CCA 0x00000008 /* Clear channel assessment */
219 #define B43legacy_MACCMD_BGNOISE 0x00000010 /* Background noise */
220
221 /* 802.11 core specific TM State Low flags */
222 #define B43legacy_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
223 #define B43legacy_TMSLOW_PLLREFSEL 0x00200000 /* PLL Freq Ref Select */
224 #define B43legacy_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Ctrl Enbl */
225 #define B43legacy_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
226 #define B43legacy_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
227
228 /* 802.11 core specific TM State High flags */
229 #define B43legacy_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available */
230 #define B43legacy_TMSHIGH_GPHY 0x00010000 /* G-PHY avail (rev >= 5) */
231
232 #define B43legacy_UCODEFLAG_AUTODIV 0x0001
233
234 /* Generic-Interrupt reasons. */
235 #define B43legacy_IRQ_MAC_SUSPENDED 0x00000001
236 #define B43legacy_IRQ_BEACON 0x00000002
237 #define B43legacy_IRQ_TBTT_INDI 0x00000004 /* Target Beacon Transmit Time */
238 #define B43legacy_IRQ_BEACON_TX_OK 0x00000008
239 #define B43legacy_IRQ_BEACON_CANCEL 0x00000010
240 #define B43legacy_IRQ_ATIM_END 0x00000020
241 #define B43legacy_IRQ_PMQ 0x00000040
242 #define B43legacy_IRQ_PIO_WORKAROUND 0x00000100
243 #define B43legacy_IRQ_MAC_TXERR 0x00000200
244 #define B43legacy_IRQ_PHY_TXERR 0x00000800
245 #define B43legacy_IRQ_PMEVENT 0x00001000
246 #define B43legacy_IRQ_TIMER0 0x00002000
247 #define B43legacy_IRQ_TIMER1 0x00004000
248 #define B43legacy_IRQ_DMA 0x00008000
249 #define B43legacy_IRQ_TXFIFO_FLUSH_OK 0x00010000
250 #define B43legacy_IRQ_CCA_MEASURE_OK 0x00020000
251 #define B43legacy_IRQ_NOISESAMPLE_OK 0x00040000
252 #define B43legacy_IRQ_UCODE_DEBUG 0x08000000
253 #define B43legacy_IRQ_RFKILL 0x10000000
254 #define B43legacy_IRQ_TX_OK 0x20000000
255 #define B43legacy_IRQ_PHY_G_CHANGED 0x40000000
256 #define B43legacy_IRQ_TIMEOUT 0x80000000
257
258 #define B43legacy_IRQ_ALL 0xFFFFFFFF
259 #define B43legacy_IRQ_MASKTEMPLATE (B43legacy_IRQ_MAC_SUSPENDED | \
260 B43legacy_IRQ_TBTT_INDI | \
261 B43legacy_IRQ_ATIM_END | \
262 B43legacy_IRQ_PMQ | \
263 B43legacy_IRQ_MAC_TXERR | \
264 B43legacy_IRQ_PHY_TXERR | \
265 B43legacy_IRQ_DMA | \
266 B43legacy_IRQ_TXFIFO_FLUSH_OK | \
267 B43legacy_IRQ_NOISESAMPLE_OK | \
268 B43legacy_IRQ_UCODE_DEBUG | \
269 B43legacy_IRQ_RFKILL | \
270 B43legacy_IRQ_TX_OK)
271
272 /* Device specific rate values.
273 * The actual values defined here are (rate_in_mbps * 2).
274 * Some code depends on this. Don't change it. */
275 #define B43legacy_CCK_RATE_1MB 2
276 #define B43legacy_CCK_RATE_2MB 4
277 #define B43legacy_CCK_RATE_5MB 11
278 #define B43legacy_CCK_RATE_11MB 22
279 #define B43legacy_OFDM_RATE_6MB 12
280 #define B43legacy_OFDM_RATE_9MB 18
281 #define B43legacy_OFDM_RATE_12MB 24
282 #define B43legacy_OFDM_RATE_18MB 36
283 #define B43legacy_OFDM_RATE_24MB 48
284 #define B43legacy_OFDM_RATE_36MB 72
285 #define B43legacy_OFDM_RATE_48MB 96
286 #define B43legacy_OFDM_RATE_54MB 108
287 /* Convert a b43legacy rate value to a rate in 100kbps */
288 #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2)
289
290
291 #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT 7
292 #define B43legacy_DEFAULT_LONG_RETRY_LIMIT 4
293
294 #define B43legacy_PHY_TX_BADNESS_LIMIT 1000
295
296 /* Max size of a security key */
297 #define B43legacy_SEC_KEYSIZE 16
298 /* Security algorithms. */
299 enum {
300 B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
301 B43legacy_SEC_ALGO_WEP40,
302 B43legacy_SEC_ALGO_TKIP,
303 B43legacy_SEC_ALGO_AES,
304 B43legacy_SEC_ALGO_WEP104,
305 B43legacy_SEC_ALGO_AES_LEGACY,
306 };
307
308 /* Core Information Registers */
309 #define B43legacy_CIR_BASE 0xf00
310 #define B43legacy_CIR_SBTPSFLAG (B43legacy_CIR_BASE + 0x18)
311 #define B43legacy_CIR_SBIMSTATE (B43legacy_CIR_BASE + 0x90)
312 #define B43legacy_CIR_SBINTVEC (B43legacy_CIR_BASE + 0x94)
313 #define B43legacy_CIR_SBTMSTATELOW (B43legacy_CIR_BASE + 0x98)
314 #define B43legacy_CIR_SBTMSTATEHIGH (B43legacy_CIR_BASE + 0x9c)
315 #define B43legacy_CIR_SBIMCONFIGLOW (B43legacy_CIR_BASE + 0xa8)
316 #define B43legacy_CIR_SB_ID_HI (B43legacy_CIR_BASE + 0xfc)
317
318 /* sbtmstatehigh state flags */
319 #define B43legacy_SBTMSTATEHIGH_SERROR 0x00000001
320 #define B43legacy_SBTMSTATEHIGH_BUSY 0x00000004
321 #define B43legacy_SBTMSTATEHIGH_TIMEOUT 0x00000020
322 #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000
323 #define B43legacy_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
324 #define B43legacy_SBTMSTATEHIGH_DMA64BIT 0x10000000
325 #define B43legacy_SBTMSTATEHIGH_GATEDCLK 0x20000000
326 #define B43legacy_SBTMSTATEHIGH_BISTFAILED 0x40000000
327 #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
328
329 /* sbimstate flags */
330 #define B43legacy_SBIMSTATE_IB_ERROR 0x20000
331 #define B43legacy_SBIMSTATE_TIMEOUT 0x40000
332
333 #define PFX KBUILD_MODNAME ": "
334 #ifdef assert
335 # undef assert
336 #endif
337 #ifdef CONFIG_B43LEGACY_DEBUG
338 # define B43legacy_WARN_ON(x) WARN_ON(x)
339 # define B43legacy_BUG_ON(expr) \
340 do { \
341 if (unlikely((expr))) { \
342 printk(KERN_INFO PFX "Test (%s) failed\n", \
343 #expr); \
344 BUG_ON(expr); \
345 } \
346 } while (0)
347 # define B43legacy_DEBUG 1
348 #else
349 /* This will evaluate the argument even if debugging is disabled. */
__b43legacy_warn_on_dummy(bool x)350 static inline bool __b43legacy_warn_on_dummy(bool x) { return x; }
351 # define B43legacy_WARN_ON(x) __b43legacy_warn_on_dummy(unlikely(!!(x)))
352 # define B43legacy_BUG_ON(x) do { /* nothing */ } while (0)
353 # define B43legacy_DEBUG 0
354 #endif
355
356
357 struct net_device;
358 struct pci_dev;
359 struct b43legacy_dmaring;
360 struct b43legacy_pioqueue;
361
362 /* The firmware file header */
363 #define B43legacy_FW_TYPE_UCODE 'u'
364 #define B43legacy_FW_TYPE_PCM 'p'
365 #define B43legacy_FW_TYPE_IV 'i'
366 struct b43legacy_fw_header {
367 /* File type */
368 u8 type;
369 /* File format version */
370 u8 ver;
371 u8 __padding[2];
372 /* Size of the data. For ucode and PCM this is in bytes.
373 * For IV this is number-of-ivs. */
374 __be32 size;
375 } __packed;
376
377 /* Initial Value file format */
378 #define B43legacy_IV_OFFSET_MASK 0x7FFF
379 #define B43legacy_IV_32BIT 0x8000
380 struct b43legacy_iv {
381 __be16 offset_size;
382 union {
383 __be16 d16;
384 __be32 d32;
385 } data __packed;
386 } __packed;
387
388 #define B43legacy_PHYMODE(phytype) (1 << (phytype))
389 #define B43legacy_PHYMODE_B B43legacy_PHYMODE \
390 ((B43legacy_PHYTYPE_B))
391 #define B43legacy_PHYMODE_G B43legacy_PHYMODE \
392 ((B43legacy_PHYTYPE_G))
393
394 /* Value pair to measure the LocalOscillator. */
395 struct b43legacy_lopair {
396 s8 low;
397 s8 high;
398 u8 used:1;
399 };
400 #define B43legacy_LO_COUNT (14*4)
401
402 struct b43legacy_phy {
403 /* Possible PHYMODEs on this PHY */
404 u8 possible_phymodes;
405 /* GMODE bit enabled in MACCTL? */
406 bool gmode;
407
408 /* Analog Type */
409 u8 analog;
410 /* B43legacy_PHYTYPE_ */
411 u8 type;
412 /* PHY revision number. */
413 u8 rev;
414
415 u16 antenna_diversity;
416 u16 savedpctlreg;
417 /* Radio versioning */
418 u16 radio_manuf; /* Radio manufacturer */
419 u16 radio_ver; /* Radio version */
420 u8 calibrated:1;
421 u8 radio_rev; /* Radio revision */
422
423 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
424
425 /* ACI (adjacent channel interference) flags. */
426 bool aci_enable;
427 bool aci_wlan_automatic;
428 bool aci_hw_rssi;
429
430 /* Radio switched on/off */
431 bool radio_on;
432 struct {
433 /* Values saved when turning the radio off.
434 * They are needed when turning it on again. */
435 bool valid;
436 u16 rfover;
437 u16 rfoverval;
438 } radio_off_context;
439
440 u16 minlowsig[2];
441 u16 minlowsigpos[2];
442
443 /* LO Measurement Data.
444 * Use b43legacy_get_lopair() to get a value.
445 */
446 struct b43legacy_lopair *_lo_pairs;
447 /* TSSI to dBm table in use */
448 const s8 *tssi2dbm;
449 /* idle TSSI value */
450 s8 idle_tssi;
451 /* Target idle TSSI */
452 int tgt_idle_tssi;
453 /* Current idle TSSI */
454 int cur_idle_tssi;
455
456 /* LocalOscillator control values. */
457 struct b43legacy_txpower_lo_control *lo_control;
458 /* Values from b43legacy_calc_loopback_gain() */
459 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
460 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
461 s16 lna_lod_gain; /* LNA lod */
462 s16 lna_gain; /* LNA */
463 s16 pga_gain; /* PGA */
464
465 /* Desired TX power level (in dBm). This is set by the user and
466 * adjusted in b43legacy_phy_xmitpower(). */
467 u8 power_level;
468
469 /* Values from b43legacy_calc_loopback_gain() */
470 u16 loopback_gain[2];
471
472 /* TX Power control values. */
473 /* B/G PHY */
474 struct {
475 /* Current Radio Attenuation for TXpower recalculation. */
476 u16 rfatt;
477 /* Current Baseband Attenuation for TXpower recalculation. */
478 u16 bbatt;
479 /* Current TXpower control value for TXpower recalculation. */
480 u16 txctl1;
481 u16 txctl2;
482 };
483 /* A PHY */
484 struct {
485 u16 txpwr_offset;
486 };
487
488 /* Current Interference Mitigation mode */
489 int interfmode;
490 /* Stack of saved values from the Interference Mitigation code.
491 * Each value in the stack is laid out as follows:
492 * bit 0-11: offset
493 * bit 12-15: register ID
494 * bit 16-32: value
495 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
496 */
497 #define B43legacy_INTERFSTACK_SIZE 26
498 u32 interfstack[B43legacy_INTERFSTACK_SIZE];
499
500 /* Saved values from the NRSSI Slope calculation */
501 s16 nrssi[2];
502 s32 nrssislope;
503 /* In memory nrssi lookup table. */
504 s8 nrssi_lt[64];
505
506 /* current channel */
507 u8 channel;
508
509 u16 lofcal;
510
511 u16 initval;
512
513 /* PHY TX errors counter. */
514 atomic_t txerr_cnt;
515
516 #if B43legacy_DEBUG
517 /* Manual TX-power control enabled? */
518 bool manual_txpower_control;
519 /* PHY registers locked by b43legacy_phy_lock()? */
520 bool phy_locked;
521 #endif /* B43legacy_DEBUG */
522 };
523
524 /* Data structures for DMA transmission, per 80211 core. */
525 struct b43legacy_dma {
526 struct b43legacy_dmaring *tx_ring0;
527 struct b43legacy_dmaring *tx_ring1;
528 struct b43legacy_dmaring *tx_ring2;
529 struct b43legacy_dmaring *tx_ring3;
530 struct b43legacy_dmaring *tx_ring4;
531 struct b43legacy_dmaring *tx_ring5;
532
533 struct b43legacy_dmaring *rx_ring0;
534 struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
535 };
536
537 /* Data structures for PIO transmission, per 80211 core. */
538 struct b43legacy_pio {
539 struct b43legacy_pioqueue *queue0;
540 struct b43legacy_pioqueue *queue1;
541 struct b43legacy_pioqueue *queue2;
542 struct b43legacy_pioqueue *queue3;
543 };
544
545 /* Context information for a noise calculation (Link Quality). */
546 struct b43legacy_noise_calculation {
547 u8 channel_at_start;
548 bool calculation_running;
549 u8 nr_samples;
550 s8 samples[8][4];
551 };
552
553 struct b43legacy_stats {
554 u8 link_noise;
555 /* Store the last TX/RX times here for updating the leds. */
556 unsigned long last_tx;
557 unsigned long last_rx;
558 };
559
560 struct b43legacy_key {
561 void *keyconf;
562 bool enabled;
563 u8 algorithm;
564 };
565
566 struct b43legacy_wldev;
567
568 /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */
569 struct b43legacy_wl {
570 /* Pointer to the active wireless device on this chip */
571 struct b43legacy_wldev *current_dev;
572 /* Pointer to the ieee80211 hardware data structure */
573 struct ieee80211_hw *hw;
574
575 spinlock_t irq_lock; /* locks IRQ */
576 struct mutex mutex; /* locks wireless core state */
577 spinlock_t leds_lock; /* lock for leds */
578
579 /* We can only have one operating interface (802.11 core)
580 * at a time. General information about this interface follows.
581 */
582
583 struct ieee80211_vif *vif;
584 /* MAC address (can be NULL). */
585 u8 mac_addr[ETH_ALEN];
586 /* Current BSSID (can be NULL). */
587 u8 bssid[ETH_ALEN];
588 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
589 int if_type;
590 /* Is the card operating in AP, STA or IBSS mode? */
591 bool operating;
592 /* filter flags */
593 unsigned int filter_flags;
594 /* Stats about the wireless interface */
595 struct ieee80211_low_level_stats ieee_stats;
596
597 #ifdef CONFIG_B43LEGACY_HWRNG
598 struct hwrng rng;
599 u8 rng_initialized;
600 char rng_name[30 + 1];
601 #endif
602
603 /* List of all wireless devices on this chip */
604 struct list_head devlist;
605 u8 nr_devs;
606
607 bool radiotap_enabled;
608 bool radio_enabled;
609
610 /* The beacon we are currently using (AP or IBSS mode).
611 * This beacon stuff is protected by the irq_lock. */
612 struct sk_buff *current_beacon;
613 bool beacon0_uploaded;
614 bool beacon1_uploaded;
615 bool beacon_templates_virgin; /* Never wrote the templates? */
616 struct work_struct beacon_update_trigger;
617 };
618
619 /* Pointers to the firmware data and meta information about it. */
620 struct b43legacy_firmware {
621 /* Microcode */
622 const struct firmware *ucode;
623 /* PCM code */
624 const struct firmware *pcm;
625 /* Initial MMIO values for the firmware */
626 const struct firmware *initvals;
627 /* Initial MMIO values for the firmware, band-specific */
628 const struct firmware *initvals_band;
629 /* Firmware revision */
630 u16 rev;
631 /* Firmware patchlevel */
632 u16 patch;
633 };
634
635 /* Device (802.11 core) initialization status. */
636 enum {
637 B43legacy_STAT_UNINIT = 0, /* Uninitialized. */
638 B43legacy_STAT_INITIALIZED = 1, /* Initialized, not yet started. */
639 B43legacy_STAT_STARTED = 2, /* Up and running. */
640 };
641 #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status)
642 #define b43legacy_set_status(wldev, stat) do { \
643 atomic_set(&(wldev)->__init_status, (stat)); \
644 smp_wmb(); \
645 } while (0)
646
647 /* *** --- HOW LOCKING WORKS IN B43legacy --- ***
648 *
649 * You should always acquire both, wl->mutex and wl->irq_lock unless:
650 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
651 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
652 * and packet TX path (and _ONLY_ there.)
653 */
654
655 /* Data structure for one wireless device (802.11 core) */
656 struct b43legacy_wldev {
657 struct ssb_device *dev;
658 struct b43legacy_wl *wl;
659
660 /* The device initialization status.
661 * Use b43legacy_status() to query. */
662 atomic_t __init_status;
663 /* Saved init status for handling suspend. */
664 int suspend_init_status;
665
666 bool __using_pio; /* Using pio rather than dma. */
667 bool bad_frames_preempt;/* Use "Bad Frames Preemption". */
668 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM). */
669 bool short_preamble; /* TRUE if using short preamble. */
670 bool radio_hw_enable; /* State of radio hardware enable bit. */
671
672 /* PHY/Radio device. */
673 struct b43legacy_phy phy;
674 union {
675 /* DMA engines. */
676 struct b43legacy_dma dma;
677 /* PIO engines. */
678 struct b43legacy_pio pio;
679 };
680
681 /* Various statistics about the physical device. */
682 struct b43legacy_stats stats;
683
684 /* The device LEDs. */
685 struct b43legacy_led led_tx;
686 struct b43legacy_led led_rx;
687 struct b43legacy_led led_assoc;
688 struct b43legacy_led led_radio;
689
690 /* Reason code of the last interrupt. */
691 u32 irq_reason;
692 u32 dma_reason[6];
693 /* The currently active generic-interrupt mask. */
694 u32 irq_mask;
695 /* Link Quality calculation context. */
696 struct b43legacy_noise_calculation noisecalc;
697 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
698 int mac_suspended;
699
700 /* Interrupt Service Routine tasklet (bottom-half) */
701 struct tasklet_struct isr_tasklet;
702
703 /* Periodic tasks */
704 struct delayed_work periodic_work;
705 unsigned int periodic_state;
706
707 struct work_struct restart_work;
708
709 /* encryption/decryption */
710 u16 ktp; /* Key table pointer */
711 u8 max_nr_keys;
712 struct b43legacy_key key[58];
713
714 /* Firmware data */
715 struct b43legacy_firmware fw;
716
717 /* Devicelist in struct b43legacy_wl (all 802.11 cores) */
718 struct list_head list;
719
720 /* Debugging stuff follows. */
721 #ifdef CONFIG_B43LEGACY_DEBUG
722 struct b43legacy_dfsentry *dfsentry;
723 #endif
724 };
725
726
727 static inline
hw_to_b43legacy_wl(struct ieee80211_hw * hw)728 struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw)
729 {
730 return hw->priv;
731 }
732
733 /* Helper function, which returns a boolean.
734 * TRUE, if PIO is used; FALSE, if DMA is used.
735 */
736 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
737 static inline
b43legacy_using_pio(struct b43legacy_wldev * dev)738 int b43legacy_using_pio(struct b43legacy_wldev *dev)
739 {
740 return dev->__using_pio;
741 }
742 #elif defined(CONFIG_B43LEGACY_DMA)
743 static inline
b43legacy_using_pio(struct b43legacy_wldev * dev)744 int b43legacy_using_pio(struct b43legacy_wldev *dev)
745 {
746 return 0;
747 }
748 #elif defined(CONFIG_B43LEGACY_PIO)
749 static inline
b43legacy_using_pio(struct b43legacy_wldev * dev)750 int b43legacy_using_pio(struct b43legacy_wldev *dev)
751 {
752 return 1;
753 }
754 #else
755 # error "Using neither DMA nor PIO? Confused..."
756 #endif
757
758
759 static inline
dev_to_b43legacy_wldev(struct device * dev)760 struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev)
761 {
762 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
763 return ssb_get_drvdata(ssb_dev);
764 }
765
766 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
767 static inline
b43legacy_is_mode(struct b43legacy_wl * wl,int type)768 int b43legacy_is_mode(struct b43legacy_wl *wl, int type)
769 {
770 return (wl->operating &&
771 wl->if_type == type);
772 }
773
774 static inline
is_bcm_board_vendor(struct b43legacy_wldev * dev)775 bool is_bcm_board_vendor(struct b43legacy_wldev *dev)
776 {
777 return (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM);
778 }
779
780 static inline
b43legacy_read16(struct b43legacy_wldev * dev,u16 offset)781 u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset)
782 {
783 return ssb_read16(dev->dev, offset);
784 }
785
786 static inline
b43legacy_write16(struct b43legacy_wldev * dev,u16 offset,u16 value)787 void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value)
788 {
789 ssb_write16(dev->dev, offset, value);
790 }
791
792 static inline
b43legacy_read32(struct b43legacy_wldev * dev,u16 offset)793 u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset)
794 {
795 return ssb_read32(dev->dev, offset);
796 }
797
798 static inline
b43legacy_write32(struct b43legacy_wldev * dev,u16 offset,u32 value)799 void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value)
800 {
801 ssb_write32(dev->dev, offset, value);
802 }
803
804 static inline
b43legacy_get_lopair(struct b43legacy_phy * phy,u16 radio_attenuation,u16 baseband_attenuation)805 struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy,
806 u16 radio_attenuation,
807 u16 baseband_attenuation)
808 {
809 return phy->_lo_pairs + (radio_attenuation
810 + 14 * (baseband_attenuation / 2));
811 }
812
813
814
815 /* Message printing */
816 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
817 __attribute__((format(printf, 2, 3)));
818 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
819 __attribute__((format(printf, 2, 3)));
820 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
821 __attribute__((format(printf, 2, 3)));
822 #if B43legacy_DEBUG
823 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
824 __attribute__((format(printf, 2, 3)));
825 #else /* DEBUG */
826 # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
827 #endif /* DEBUG */
828
829 /* Macros for printing a value in Q5.2 format */
830 #define Q52_FMT "%u.%u"
831 #define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4)
832
833 #endif /* B43legacy_H_ */
834