1 #ifndef B43_DMA_H_
2 #define B43_DMA_H_
3
4 #include <linux/err.h>
5
6 #include "b43.h"
7
8
9 /* DMA-Interrupt reasons. */
10 #define B43_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \
11 | (1 << 14) | (1 << 15))
12 #define B43_DMAIRQ_NONFATALMASK (1 << 13)
13 #define B43_DMAIRQ_RX_DONE (1 << 16)
14
15 /*** 32-bit DMA Engine. ***/
16
17 /* 32-bit DMA controller registers. */
18 #define B43_DMA32_TXCTL 0x00
19 #define B43_DMA32_TXENABLE 0x00000001
20 #define B43_DMA32_TXSUSPEND 0x00000002
21 #define B43_DMA32_TXLOOPBACK 0x00000004
22 #define B43_DMA32_TXFLUSH 0x00000010
23 #define B43_DMA32_TXADDREXT_MASK 0x00030000
24 #define B43_DMA32_TXADDREXT_SHIFT 16
25 #define B43_DMA32_TXRING 0x04
26 #define B43_DMA32_TXINDEX 0x08
27 #define B43_DMA32_TXSTATUS 0x0C
28 #define B43_DMA32_TXDPTR 0x00000FFF
29 #define B43_DMA32_TXSTATE 0x0000F000
30 #define B43_DMA32_TXSTAT_DISABLED 0x00000000
31 #define B43_DMA32_TXSTAT_ACTIVE 0x00001000
32 #define B43_DMA32_TXSTAT_IDLEWAIT 0x00002000
33 #define B43_DMA32_TXSTAT_STOPPED 0x00003000
34 #define B43_DMA32_TXSTAT_SUSP 0x00004000
35 #define B43_DMA32_TXERROR 0x000F0000
36 #define B43_DMA32_TXERR_NOERR 0x00000000
37 #define B43_DMA32_TXERR_PROT 0x00010000
38 #define B43_DMA32_TXERR_UNDERRUN 0x00020000
39 #define B43_DMA32_TXERR_BUFREAD 0x00030000
40 #define B43_DMA32_TXERR_DESCREAD 0x00040000
41 #define B43_DMA32_TXACTIVE 0xFFF00000
42 #define B43_DMA32_RXCTL 0x10
43 #define B43_DMA32_RXENABLE 0x00000001
44 #define B43_DMA32_RXFROFF_MASK 0x000000FE
45 #define B43_DMA32_RXFROFF_SHIFT 1
46 #define B43_DMA32_RXDIRECTFIFO 0x00000100
47 #define B43_DMA32_RXADDREXT_MASK 0x00030000
48 #define B43_DMA32_RXADDREXT_SHIFT 16
49 #define B43_DMA32_RXRING 0x14
50 #define B43_DMA32_RXINDEX 0x18
51 #define B43_DMA32_RXSTATUS 0x1C
52 #define B43_DMA32_RXDPTR 0x00000FFF
53 #define B43_DMA32_RXSTATE 0x0000F000
54 #define B43_DMA32_RXSTAT_DISABLED 0x00000000
55 #define B43_DMA32_RXSTAT_ACTIVE 0x00001000
56 #define B43_DMA32_RXSTAT_IDLEWAIT 0x00002000
57 #define B43_DMA32_RXSTAT_STOPPED 0x00003000
58 #define B43_DMA32_RXERROR 0x000F0000
59 #define B43_DMA32_RXERR_NOERR 0x00000000
60 #define B43_DMA32_RXERR_PROT 0x00010000
61 #define B43_DMA32_RXERR_OVERFLOW 0x00020000
62 #define B43_DMA32_RXERR_BUFWRITE 0x00030000
63 #define B43_DMA32_RXERR_DESCREAD 0x00040000
64 #define B43_DMA32_RXACTIVE 0xFFF00000
65
66 /* 32-bit DMA descriptor. */
67 struct b43_dmadesc32 {
68 __le32 control;
69 __le32 address;
70 } __packed;
71 #define B43_DMA32_DCTL_BYTECNT 0x00001FFF
72 #define B43_DMA32_DCTL_ADDREXT_MASK 0x00030000
73 #define B43_DMA32_DCTL_ADDREXT_SHIFT 16
74 #define B43_DMA32_DCTL_DTABLEEND 0x10000000
75 #define B43_DMA32_DCTL_IRQ 0x20000000
76 #define B43_DMA32_DCTL_FRAMEEND 0x40000000
77 #define B43_DMA32_DCTL_FRAMESTART 0x80000000
78
79 /*** 64-bit DMA Engine. ***/
80
81 /* 64-bit DMA controller registers. */
82 #define B43_DMA64_TXCTL 0x00
83 #define B43_DMA64_TXENABLE 0x00000001
84 #define B43_DMA64_TXSUSPEND 0x00000002
85 #define B43_DMA64_TXLOOPBACK 0x00000004
86 #define B43_DMA64_TXFLUSH 0x00000010
87 #define B43_DMA64_TXADDREXT_MASK 0x00030000
88 #define B43_DMA64_TXADDREXT_SHIFT 16
89 #define B43_DMA64_TXINDEX 0x04
90 #define B43_DMA64_TXRINGLO 0x08
91 #define B43_DMA64_TXRINGHI 0x0C
92 #define B43_DMA64_TXSTATUS 0x10
93 #define B43_DMA64_TXSTATDPTR 0x00001FFF
94 #define B43_DMA64_TXSTAT 0xF0000000
95 #define B43_DMA64_TXSTAT_DISABLED 0x00000000
96 #define B43_DMA64_TXSTAT_ACTIVE 0x10000000
97 #define B43_DMA64_TXSTAT_IDLEWAIT 0x20000000
98 #define B43_DMA64_TXSTAT_STOPPED 0x30000000
99 #define B43_DMA64_TXSTAT_SUSP 0x40000000
100 #define B43_DMA64_TXERROR 0x14
101 #define B43_DMA64_TXERRDPTR 0x0001FFFF
102 #define B43_DMA64_TXERR 0xF0000000
103 #define B43_DMA64_TXERR_NOERR 0x00000000
104 #define B43_DMA64_TXERR_PROT 0x10000000
105 #define B43_DMA64_TXERR_UNDERRUN 0x20000000
106 #define B43_DMA64_TXERR_TRANSFER 0x30000000
107 #define B43_DMA64_TXERR_DESCREAD 0x40000000
108 #define B43_DMA64_TXERR_CORE 0x50000000
109 #define B43_DMA64_RXCTL 0x20
110 #define B43_DMA64_RXENABLE 0x00000001
111 #define B43_DMA64_RXFROFF_MASK 0x000000FE
112 #define B43_DMA64_RXFROFF_SHIFT 1
113 #define B43_DMA64_RXDIRECTFIFO 0x00000100
114 #define B43_DMA64_RXADDREXT_MASK 0x00030000
115 #define B43_DMA64_RXADDREXT_SHIFT 16
116 #define B43_DMA64_RXINDEX 0x24
117 #define B43_DMA64_RXRINGLO 0x28
118 #define B43_DMA64_RXRINGHI 0x2C
119 #define B43_DMA64_RXSTATUS 0x30
120 #define B43_DMA64_RXSTATDPTR 0x00001FFF
121 #define B43_DMA64_RXSTAT 0xF0000000
122 #define B43_DMA64_RXSTAT_DISABLED 0x00000000
123 #define B43_DMA64_RXSTAT_ACTIVE 0x10000000
124 #define B43_DMA64_RXSTAT_IDLEWAIT 0x20000000
125 #define B43_DMA64_RXSTAT_STOPPED 0x30000000
126 #define B43_DMA64_RXSTAT_SUSP 0x40000000
127 #define B43_DMA64_RXERROR 0x34
128 #define B43_DMA64_RXERRDPTR 0x0001FFFF
129 #define B43_DMA64_RXERR 0xF0000000
130 #define B43_DMA64_RXERR_NOERR 0x00000000
131 #define B43_DMA64_RXERR_PROT 0x10000000
132 #define B43_DMA64_RXERR_UNDERRUN 0x20000000
133 #define B43_DMA64_RXERR_TRANSFER 0x30000000
134 #define B43_DMA64_RXERR_DESCREAD 0x40000000
135 #define B43_DMA64_RXERR_CORE 0x50000000
136
137 /* 64-bit DMA descriptor. */
138 struct b43_dmadesc64 {
139 __le32 control0;
140 __le32 control1;
141 __le32 address_low;
142 __le32 address_high;
143 } __packed;
144 #define B43_DMA64_DCTL0_DTABLEEND 0x10000000
145 #define B43_DMA64_DCTL0_IRQ 0x20000000
146 #define B43_DMA64_DCTL0_FRAMEEND 0x40000000
147 #define B43_DMA64_DCTL0_FRAMESTART 0x80000000
148 #define B43_DMA64_DCTL1_BYTECNT 0x00001FFF
149 #define B43_DMA64_DCTL1_ADDREXT_MASK 0x00030000
150 #define B43_DMA64_DCTL1_ADDREXT_SHIFT 16
151
152 struct b43_dmadesc_generic {
153 union {
154 struct b43_dmadesc32 dma32;
155 struct b43_dmadesc64 dma64;
156 } __packed;
157 } __packed;
158
159 /* Misc DMA constants */
160 #define B43_DMA_RINGMEMSIZE PAGE_SIZE
161 #define B43_DMA0_RX_FRAMEOFFSET 30
162
163 /* DMA engine tuning knobs */
164 #define B43_TXRING_SLOTS 256
165 #define B43_RXRING_SLOTS 64
166 #define B43_DMA0_RX_BUFFERSIZE (B43_DMA0_RX_FRAMEOFFSET + IEEE80211_MAX_FRAME_LEN)
167
168 /* Pointer poison */
169 #define B43_DMA_PTR_POISON ((void *)ERR_PTR(-ENOMEM))
170 #define b43_dma_ptr_is_poisoned(ptr) (unlikely((ptr) == B43_DMA_PTR_POISON))
171
172
173 struct sk_buff;
174 struct b43_private;
175 struct b43_txstatus;
176
177 struct b43_dmadesc_meta {
178 /* The kernel DMA-able buffer. */
179 struct sk_buff *skb;
180 /* DMA base bus-address of the descriptor buffer. */
181 dma_addr_t dmaaddr;
182 /* ieee80211 TX status. Only used once per 802.11 frag. */
183 bool is_last_fragment;
184 };
185
186 struct b43_dmaring;
187
188 /* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
189 struct b43_dma_ops {
190 struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring,
191 int slot,
192 struct b43_dmadesc_meta **
193 meta);
194 void (*fill_descriptor) (struct b43_dmaring * ring,
195 struct b43_dmadesc_generic * desc,
196 dma_addr_t dmaaddr, u16 bufsize, int start,
197 int end, int irq);
198 void (*poke_tx) (struct b43_dmaring * ring, int slot);
199 void (*tx_suspend) (struct b43_dmaring * ring);
200 void (*tx_resume) (struct b43_dmaring * ring);
201 int (*get_current_rxslot) (struct b43_dmaring * ring);
202 void (*set_current_rxslot) (struct b43_dmaring * ring, int slot);
203 };
204
205 enum b43_dmatype {
206 B43_DMA_30BIT = 30,
207 B43_DMA_32BIT = 32,
208 B43_DMA_64BIT = 64,
209 };
210
211 struct b43_dmaring {
212 /* Lowlevel DMA ops. */
213 const struct b43_dma_ops *ops;
214 /* Kernel virtual base address of the ring memory. */
215 void *descbase;
216 /* Meta data about all descriptors. */
217 struct b43_dmadesc_meta *meta;
218 /* Cache of TX headers for each TX frame.
219 * This is to avoid an allocation on each TX.
220 * This is NULL for an RX ring.
221 */
222 u8 *txhdr_cache;
223 /* (Unadjusted) DMA base bus-address of the ring memory. */
224 dma_addr_t dmabase;
225 /* Number of descriptor slots in the ring. */
226 int nr_slots;
227 /* Number of used descriptor slots. */
228 int used_slots;
229 /* Currently used slot in the ring. */
230 int current_slot;
231 /* Frameoffset in octets. */
232 u32 frameoffset;
233 /* Descriptor buffer size. */
234 u16 rx_buffersize;
235 /* The MMIO base register of the DMA controller. */
236 u16 mmio_base;
237 /* DMA controller index number (0-5). */
238 int index;
239 /* Boolean. Is this a TX ring? */
240 bool tx;
241 /* The type of DMA engine used. */
242 enum b43_dmatype type;
243 /* Boolean. Is this ring stopped at ieee80211 level? */
244 bool stopped;
245 /* The QOS priority assigned to this ring. Only used for TX rings.
246 * This is the mac80211 "queue" value. */
247 u8 queue_prio;
248 struct b43_wldev *dev;
249 #ifdef CONFIG_B43_DEBUG
250 /* Maximum number of used slots. */
251 int max_used_slots;
252 /* Last time we injected a ring overflow. */
253 unsigned long last_injected_overflow;
254 /* Statistics: Number of successfully transmitted packets */
255 u64 nr_succeed_tx_packets;
256 /* Statistics: Number of failed TX packets */
257 u64 nr_failed_tx_packets;
258 /* Statistics: Total number of TX plus all retries. */
259 u64 nr_total_packet_tries;
260 #endif /* CONFIG_B43_DEBUG */
261 };
262
b43_dma_read(struct b43_dmaring * ring,u16 offset)263 static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset)
264 {
265 return b43_read32(ring->dev, ring->mmio_base + offset);
266 }
267
b43_dma_write(struct b43_dmaring * ring,u16 offset,u32 value)268 static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value)
269 {
270 b43_write32(ring->dev, ring->mmio_base + offset, value);
271 }
272
273 int b43_dma_init(struct b43_wldev *dev);
274 void b43_dma_free(struct b43_wldev *dev);
275
276 void b43_dma_tx_suspend(struct b43_wldev *dev);
277 void b43_dma_tx_resume(struct b43_wldev *dev);
278
279 int b43_dma_tx(struct b43_wldev *dev,
280 struct sk_buff *skb);
281 void b43_dma_handle_txstatus(struct b43_wldev *dev,
282 const struct b43_txstatus *status);
283
284 void b43_dma_rx(struct b43_dmaring *ring);
285
286 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
287 unsigned int engine_index, bool enable);
288
289 #endif /* B43_DMA_H_ */
290