1 /*  *********************************************************************
2     *  SB1250 Board Support Package
3     *
4     *  Register Definitions                     File: sb1250_regs.h
5     *
6     *  This module contains the addresses of the on-chip peripherals
7     *  on the SB1250.
8     *
9     *  SB1250 specification level:  01/02/2002
10     *
11     *********************************************************************
12     *
13     *  Copyright 2000,2001,2002,2003
14     *  Broadcom Corporation. All rights reserved.
15     *
16     *  This program is free software; you can redistribute it and/or
17     *  modify it under the terms of the GNU General Public License as
18     *  published by the Free Software Foundation; either version 2 of
19     *  the License, or (at your option) any later version.
20     *
21     *  This program is distributed in the hope that it will be useful,
22     *  but WITHOUT ANY WARRANTY; without even the implied warranty of
23     *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24     *  GNU General Public License for more details.
25     *
26     *  You should have received a copy of the GNU General Public License
27     *  along with this program; if not, write to the Free Software
28     *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29     *  MA 02111-1307 USA
30     ********************************************************************* */
31 
32 
33 #ifndef _SB1250_REGS_H
34 #define _SB1250_REGS_H
35 
36 #include "sb1250_defs.h"
37 
38 
39 /*  *********************************************************************
40     *  Some general notes:
41     *
42     *  For the most part, when there is more than one peripheral
43     *  of the same type on the SOC, the constants below will be
44     *  offsets from the base of each peripheral.  For example,
45     *  the MAC registers are described as offsets from the first
46     *  MAC register, and there will be a MAC_REGISTER() macro
47     *  to calculate the base address of a given MAC.
48     *
49     *  The information in this file is based on the SB1250 SOC
50     *  manual version 0.2, July 2000.
51     ********************************************************************* */
52 
53 
54 /*  *********************************************************************
55     * Memory Controller Registers
56     ********************************************************************* */
57 
58 /*
59  * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
60  * since there is one reg there (but it could get its addr/offset constant).
61  */
62 
63 #if SIBYTE_HDR_FEATURE_1250_112x		/* This MC only on 1250 & 112x */
64 #define A_MC_BASE_0                 0x0010051000
65 #define A_MC_BASE_1                 0x0010052000
66 #define MC_REGISTER_SPACING         0x1000
67 
68 #define A_MC_BASE(ctlid)            ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
69 #define A_MC_REGISTER(ctlid, reg)    (A_MC_BASE(ctlid)+(reg))
70 
71 #define R_MC_CONFIG                 0x0000000100
72 #define R_MC_DRAMCMD                0x0000000120
73 #define R_MC_DRAMMODE               0x0000000140
74 #define R_MC_TIMING1                0x0000000160
75 #define R_MC_TIMING2                0x0000000180
76 #define R_MC_CS_START               0x00000001A0
77 #define R_MC_CS_END                 0x00000001C0
78 #define R_MC_CS_INTERLEAVE          0x00000001E0
79 #define S_MC_CS_STARTEND            16
80 
81 #define R_MC_CSX_BASE               0x0000000200
82 #define R_MC_CSX_ROW                0x0000000000	/* relative to CSX_BASE, above */
83 #define R_MC_CSX_COL                0x0000000020	/* relative to CSX_BASE, above */
84 #define R_MC_CSX_BA                 0x0000000040	/* relative to CSX_BASE, above */
85 #define MC_CSX_SPACING              0x0000000060	/* relative to CSX_BASE, above */
86 
87 #define R_MC_CS0_ROW                0x0000000200
88 #define R_MC_CS0_COL                0x0000000220
89 #define R_MC_CS0_BA                 0x0000000240
90 #define R_MC_CS1_ROW                0x0000000260
91 #define R_MC_CS1_COL                0x0000000280
92 #define R_MC_CS1_BA                 0x00000002A0
93 #define R_MC_CS2_ROW                0x00000002C0
94 #define R_MC_CS2_COL                0x00000002E0
95 #define R_MC_CS2_BA                 0x0000000300
96 #define R_MC_CS3_ROW                0x0000000320
97 #define R_MC_CS3_COL                0x0000000340
98 #define R_MC_CS3_BA                 0x0000000360
99 #define R_MC_CS_ATTR                0x0000000380
100 #define R_MC_TEST_DATA              0x0000000400
101 #define R_MC_TEST_ECC               0x0000000420
102 #define R_MC_MCLK_CFG               0x0000000500
103 
104 #endif	/* 1250 & 112x */
105 
106 /*  *********************************************************************
107     * L2 Cache Control Registers
108     ********************************************************************* */
109 
110 #if SIBYTE_HDR_FEATURE_1250_112x	/* This L2C only on 1250/112x */
111 
112 #define A_L2_READ_TAG               0x0010040018
113 #define A_L2_ECC_TAG                0x0010040038
114 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
115 #define A_L2_READ_MISC              0x0010040058
116 #endif /* 1250 PASS3 || 112x PASS1 */
117 #define A_L2_WAY_DISABLE            0x0010041000
118 #define A_L2_MAKEDISABLE(x)         (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
119 #define A_L2_MGMT_TAG_BASE          0x00D0000000
120 
121 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
122 #define A_L2_CACHE_DISABLE	   0x0010042000
123 #define A_L2_MAKECACHEDISABLE(x)   (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
124 #define A_L2_MISC_CONFIG	   0x0010043000
125 #endif /* 1250 PASS2 || 112x PASS1 */
126 
127 /* Backward-compatibility definitions.  */
128 /* XXX: discourage people from using these constants.  */
129 #define A_L2_READ_ADDRESS           A_L2_READ_TAG
130 #define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
131 
132 #endif
133 
134 
135 /*  *********************************************************************
136     * PCI Interface Registers
137     ********************************************************************* */
138 
139 #if SIBYTE_HDR_FEATURE_1250_112x	/* This PCI/HT only on 1250/112x */
140 #define A_PCI_TYPE00_HEADER         0x00DE000000
141 #define A_PCI_TYPE01_HEADER         0x00DE000800
142 #endif
143 
144 
145 /*  *********************************************************************
146     * Ethernet DMA and MACs
147     ********************************************************************* */
148 
149 #define A_MAC_BASE_0                0x0010064000
150 #define A_MAC_BASE_1                0x0010065000
151 #if SIBYTE_HDR_FEATURE_CHIP(1250)
152 #define A_MAC_BASE_2                0x0010066000
153 #endif /* 1250 */
154 
155 #define MAC_SPACING                 0x1000
156 #define MAC_DMA_TXRX_SPACING        0x0400
157 #define MAC_DMA_CHANNEL_SPACING     0x0100
158 #define DMA_RX                      0
159 #define DMA_TX                      1
160 #define MAC_NUM_DMACHAN		    2		    /* channels per direction */
161 
162 /* XXX: not correct; depends on SOC type.  */
163 #define MAC_NUM_PORTS               3
164 
165 #define A_MAC_CHANNEL_BASE(macnum)                  \
166             (A_MAC_BASE_0 +                         \
167              MAC_SPACING*(macnum))
168 
169 #define A_MAC_REGISTER(macnum,reg)                  \
170             (A_MAC_BASE_0 +                         \
171              MAC_SPACING*(macnum) + (reg))
172 
173 
174 #define R_MAC_DMA_CHANNELS		0x800 /* Relative to A_MAC_CHANNEL_BASE */
175 
176 #define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan)  \
177              ((A_MAC_CHANNEL_BASE(macnum)) +        \
178              R_MAC_DMA_CHANNELS +                   \
179              (MAC_DMA_TXRX_SPACING*(txrx)) +        \
180              (MAC_DMA_CHANNEL_SPACING*(chan)))
181 
182 #define R_MAC_DMA_CHANNEL_BASE(txrx, chan)		\
183              (R_MAC_DMA_CHANNELS +                   \
184              (MAC_DMA_TXRX_SPACING*(txrx)) +        \
185              (MAC_DMA_CHANNEL_SPACING*(chan)))
186 
187 #define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg)           \
188             (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) +    \
189             (reg))
190 
191 #define R_MAC_DMA_REGISTER(txrx, chan, reg)           \
192             (R_MAC_DMA_CHANNEL_BASE(txrx, chan) +    \
193             (reg))
194 
195 /*
196  * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
197  */
198 
199 #define R_MAC_DMA_CONFIG0               0x00000000
200 #define R_MAC_DMA_CONFIG1               0x00000008
201 #define R_MAC_DMA_DSCR_BASE             0x00000010
202 #define R_MAC_DMA_DSCR_CNT              0x00000018
203 #define R_MAC_DMA_CUR_DSCRA             0x00000020
204 #define R_MAC_DMA_CUR_DSCRB             0x00000028
205 #define R_MAC_DMA_CUR_DSCRADDR          0x00000030
206 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
207 #define R_MAC_DMA_OODPKTLOST_RX         0x00000038	/* rx only */
208 #endif /* 1250 PASS3 || 112x PASS1 */
209 
210 /*
211  * RMON Counters
212  */
213 
214 #define R_MAC_RMON_TX_BYTES             0x00000000
215 #define R_MAC_RMON_COLLISIONS           0x00000008
216 #define R_MAC_RMON_LATE_COL             0x00000010
217 #define R_MAC_RMON_EX_COL               0x00000018
218 #define R_MAC_RMON_FCS_ERROR            0x00000020
219 #define R_MAC_RMON_TX_ABORT             0x00000028
220 /* Counter #6 (0x30) now reserved */
221 #define R_MAC_RMON_TX_BAD               0x00000038
222 #define R_MAC_RMON_TX_GOOD              0x00000040
223 #define R_MAC_RMON_TX_RUNT              0x00000048
224 #define R_MAC_RMON_TX_OVERSIZE          0x00000050
225 #define R_MAC_RMON_RX_BYTES             0x00000080
226 #define R_MAC_RMON_RX_MCAST             0x00000088
227 #define R_MAC_RMON_RX_BCAST             0x00000090
228 #define R_MAC_RMON_RX_BAD               0x00000098
229 #define R_MAC_RMON_RX_GOOD              0x000000A0
230 #define R_MAC_RMON_RX_RUNT              0x000000A8
231 #define R_MAC_RMON_RX_OVERSIZE          0x000000B0
232 #define R_MAC_RMON_RX_FCS_ERROR         0x000000B8
233 #define R_MAC_RMON_RX_LENGTH_ERROR      0x000000C0
234 #define R_MAC_RMON_RX_CODE_ERROR        0x000000C8
235 #define R_MAC_RMON_RX_ALIGN_ERROR       0x000000D0
236 
237 /* Updated to spec 0.2 */
238 #define R_MAC_CFG                       0x00000100
239 #define R_MAC_THRSH_CFG                 0x00000108
240 #define R_MAC_VLANTAG                   0x00000110
241 #define R_MAC_FRAMECFG                  0x00000118
242 #define R_MAC_EOPCNT                    0x00000120
243 #define R_MAC_FIFO_PTRS                 0x00000128
244 #define R_MAC_ADFILTER_CFG              0x00000200
245 #define R_MAC_ETHERNET_ADDR             0x00000208
246 #define R_MAC_PKT_TYPE                  0x00000210
247 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
248 #define R_MAC_ADMASK0			0x00000218
249 #define R_MAC_ADMASK1			0x00000220
250 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
251 #define R_MAC_HASH_BASE                 0x00000240
252 #define R_MAC_ADDR_BASE                 0x00000280
253 #define R_MAC_CHLO0_BASE                0x00000300
254 #define R_MAC_CHUP0_BASE                0x00000320
255 #define R_MAC_ENABLE                    0x00000400
256 #define R_MAC_STATUS                    0x00000408
257 #define R_MAC_INT_MASK                  0x00000410
258 #define R_MAC_TXD_CTL                   0x00000420
259 #define R_MAC_MDIO                      0x00000428
260 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
261 #define R_MAC_STATUS1		        0x00000430
262 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
263 #define R_MAC_DEBUG_STATUS              0x00000448
264 
265 #define MAC_HASH_COUNT			8
266 #define MAC_ADDR_COUNT			8
267 #define MAC_CHMAP_COUNT			4
268 
269 
270 /*  *********************************************************************
271     * DUART Registers
272     ********************************************************************* */
273 
274 
275 #if SIBYTE_HDR_FEATURE_1250_112x    /* This MC only on 1250 & 112x */
276 #define R_DUART_NUM_PORTS           2
277 
278 #define A_DUART                     0x0010060000
279 
280 #define DUART_CHANREG_SPACING       0x100
281 
282 #define A_DUART_CHANREG(chan, reg)					\
283 	(A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg))
284 #endif	/* 1250 & 112x */
285 
286 #define R_DUART_MODE_REG_1	    0x000
287 #define R_DUART_MODE_REG_2	    0x010
288 #define R_DUART_STATUS		    0x020
289 #define R_DUART_CLK_SEL		    0x030
290 #define R_DUART_CMD		    0x050
291 #define R_DUART_RX_HOLD		    0x060
292 #define R_DUART_TX_HOLD		    0x070
293 
294 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
295 #define R_DUART_FULL_CTL	    0x040
296 #define R_DUART_OPCR_X		    0x080
297 #define R_DUART_AUXCTL_X	    0x090
298 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
299 
300 
301 /*
302  * The IMR and ISR can't be addressed with A_DUART_CHANREG,
303  * so use these macros instead.
304  */
305 
306 #if SIBYTE_HDR_FEATURE_1250_112x    /* This MC only on 1250 & 112x */
307 #define DUART_IMRISR_SPACING	    0x20
308 #define DUART_INCHNG_SPACING	    0x10
309 
310 #define A_DUART_CTRLREG(reg)						\
311 	(A_DUART + DUART_CHANREG_SPACING * 3 + (reg))
312 
313 #define R_DUART_IMRREG(chan)						\
314 	(R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING)
315 #define R_DUART_ISRREG(chan)						\
316 	(R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING)
317 #define R_DUART_INCHREG(chan)						\
318 	(R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING)
319 
320 #define A_DUART_IMRREG(chan)	    A_DUART_CTRLREG(R_DUART_IMRREG(chan))
321 #define A_DUART_ISRREG(chan)	    A_DUART_CTRLREG(R_DUART_ISRREG(chan))
322 #define A_DUART_INCHREG(chan)	    A_DUART_CTRLREG(R_DUART_INCHREG(chan))
323 #endif	/* 1250 & 112x */
324 
325 #define R_DUART_AUX_CTRL	    0x010
326 #define R_DUART_ISR_A		    0x020
327 #define R_DUART_IMR_A		    0x030
328 #define R_DUART_ISR_B		    0x040
329 #define R_DUART_IMR_B		    0x050
330 #define R_DUART_OUT_PORT	    0x060
331 #define R_DUART_OPCR		    0x070
332 #define R_DUART_IN_PORT		    0x080
333 
334 #define R_DUART_SET_OPR		    0x0B0
335 #define R_DUART_CLEAR_OPR	    0x0C0
336 #define R_DUART_IN_CHNG_A	    0x0D0
337 #define R_DUART_IN_CHNG_B	    0x0E0
338 
339 
340 /*
341  * These constants are the absolute addresses.
342  */
343 
344 #define A_DUART_MODE_REG_1_A        0x0010060100
345 #define A_DUART_MODE_REG_2_A        0x0010060110
346 #define A_DUART_STATUS_A            0x0010060120
347 #define A_DUART_CLK_SEL_A           0x0010060130
348 #define A_DUART_CMD_A               0x0010060150
349 #define A_DUART_RX_HOLD_A           0x0010060160
350 #define A_DUART_TX_HOLD_A           0x0010060170
351 
352 #define A_DUART_MODE_REG_1_B        0x0010060200
353 #define A_DUART_MODE_REG_2_B        0x0010060210
354 #define A_DUART_STATUS_B            0x0010060220
355 #define A_DUART_CLK_SEL_B           0x0010060230
356 #define A_DUART_CMD_B               0x0010060250
357 #define A_DUART_RX_HOLD_B           0x0010060260
358 #define A_DUART_TX_HOLD_B           0x0010060270
359 
360 #define A_DUART_INPORT_CHNG         0x0010060300
361 #define A_DUART_AUX_CTRL            0x0010060310
362 #define A_DUART_ISR_A               0x0010060320
363 #define A_DUART_IMR_A               0x0010060330
364 #define A_DUART_ISR_B               0x0010060340
365 #define A_DUART_IMR_B               0x0010060350
366 #define A_DUART_OUT_PORT            0x0010060360
367 #define A_DUART_OPCR                0x0010060370
368 #define A_DUART_IN_PORT             0x0010060380
369 #define A_DUART_ISR                 0x0010060390
370 #define A_DUART_IMR                 0x00100603A0
371 #define A_DUART_SET_OPR             0x00100603B0
372 #define A_DUART_CLEAR_OPR           0x00100603C0
373 #define A_DUART_INPORT_CHNG_A       0x00100603D0
374 #define A_DUART_INPORT_CHNG_B       0x00100603E0
375 
376 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
377 #define A_DUART_FULL_CTL_A	    0x0010060140
378 #define A_DUART_FULL_CTL_B	    0x0010060240
379 
380 #define A_DUART_OPCR_A	  	    0x0010060180
381 #define A_DUART_OPCR_B	  	    0x0010060280
382 
383 #define A_DUART_INPORT_CHNG_DEBUG   0x00100603F0
384 #endif /* 1250 PASS2 || 112x PASS1 */
385 
386 
387 /*  *********************************************************************
388     * Synchronous Serial Registers
389     ********************************************************************* */
390 
391 
392 #if SIBYTE_HDR_FEATURE_1250_112x	/* sync serial only on 1250/112x */
393 
394 #define A_SER_BASE_0                0x0010060400
395 #define A_SER_BASE_1                0x0010060800
396 #define SER_SPACING                 0x400
397 
398 #define SER_DMA_TXRX_SPACING        0x80
399 
400 #define SER_NUM_PORTS               2
401 
402 #define A_SER_CHANNEL_BASE(sernum)                  \
403             (A_SER_BASE_0 +                         \
404              SER_SPACING*(sernum))
405 
406 #define A_SER_REGISTER(sernum,reg)                  \
407             (A_SER_BASE_0 +                         \
408              SER_SPACING*(sernum) + (reg))
409 
410 
411 #define R_SER_DMA_CHANNELS		0   /* Relative to A_SER_BASE_x */
412 
413 #define A_SER_DMA_CHANNEL_BASE(sernum,txrx)    \
414              ((A_SER_CHANNEL_BASE(sernum)) +        \
415              R_SER_DMA_CHANNELS +                   \
416              (SER_DMA_TXRX_SPACING*(txrx)))
417 
418 #define A_SER_DMA_REGISTER(sernum, txrx, reg)           \
419             (A_SER_DMA_CHANNEL_BASE(sernum, txrx) +    \
420             (reg))
421 
422 
423 /*
424  * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
425  */
426 
427 #define R_SER_DMA_CONFIG0           0x00000000
428 #define R_SER_DMA_CONFIG1           0x00000008
429 #define R_SER_DMA_DSCR_BASE         0x00000010
430 #define R_SER_DMA_DSCR_CNT          0x00000018
431 #define R_SER_DMA_CUR_DSCRA         0x00000020
432 #define R_SER_DMA_CUR_DSCRB         0x00000028
433 #define R_SER_DMA_CUR_DSCRADDR      0x00000030
434 
435 #define R_SER_DMA_CONFIG0_RX        0x00000000
436 #define R_SER_DMA_CONFIG1_RX        0x00000008
437 #define R_SER_DMA_DSCR_BASE_RX      0x00000010
438 #define R_SER_DMA_DSCR_COUNT_RX     0x00000018
439 #define R_SER_DMA_CUR_DSCR_A_RX     0x00000020
440 #define R_SER_DMA_CUR_DSCR_B_RX     0x00000028
441 #define R_SER_DMA_CUR_DSCR_ADDR_RX  0x00000030
442 
443 #define R_SER_DMA_CONFIG0_TX        0x00000080
444 #define R_SER_DMA_CONFIG1_TX        0x00000088
445 #define R_SER_DMA_DSCR_BASE_TX      0x00000090
446 #define R_SER_DMA_DSCR_COUNT_TX     0x00000098
447 #define R_SER_DMA_CUR_DSCR_A_TX     0x000000A0
448 #define R_SER_DMA_CUR_DSCR_B_TX     0x000000A8
449 #define R_SER_DMA_CUR_DSCR_ADDR_TX  0x000000B0
450 
451 #define R_SER_MODE                  0x00000100
452 #define R_SER_MINFRM_SZ             0x00000108
453 #define R_SER_MAXFRM_SZ             0x00000110
454 #define R_SER_ADDR                  0x00000118
455 #define R_SER_USR0_ADDR             0x00000120
456 #define R_SER_USR1_ADDR             0x00000128
457 #define R_SER_USR2_ADDR             0x00000130
458 #define R_SER_USR3_ADDR             0x00000138
459 #define R_SER_CMD                   0x00000140
460 #define R_SER_TX_RD_THRSH           0x00000160
461 #define R_SER_TX_WR_THRSH           0x00000168
462 #define R_SER_RX_RD_THRSH           0x00000170
463 #define R_SER_LINE_MODE		    0x00000178
464 #define R_SER_DMA_ENABLE            0x00000180
465 #define R_SER_INT_MASK              0x00000190
466 #define R_SER_STATUS                0x00000188
467 #define R_SER_STATUS_DEBUG          0x000001A8
468 #define R_SER_RX_TABLE_BASE         0x00000200
469 #define SER_RX_TABLE_COUNT          16
470 #define R_SER_TX_TABLE_BASE         0x00000300
471 #define SER_TX_TABLE_COUNT          16
472 
473 /* RMON Counters */
474 #define R_SER_RMON_TX_BYTE_LO       0x000001C0
475 #define R_SER_RMON_TX_BYTE_HI       0x000001C8
476 #define R_SER_RMON_RX_BYTE_LO       0x000001D0
477 #define R_SER_RMON_RX_BYTE_HI       0x000001D8
478 #define R_SER_RMON_TX_UNDERRUN      0x000001E0
479 #define R_SER_RMON_RX_OVERFLOW      0x000001E8
480 #define R_SER_RMON_RX_ERRORS        0x000001F0
481 #define R_SER_RMON_RX_BADADDR       0x000001F8
482 
483 #endif	/* 1250/112x */
484 
485 /*  *********************************************************************
486     * Generic Bus Registers
487     ********************************************************************* */
488 
489 #define IO_EXT_CFG_COUNT            8
490 
491 #define A_IO_EXT_BASE		    0x0010061000
492 #define A_IO_EXT_REG(r)		    (A_IO_EXT_BASE + (r))
493 
494 #define A_IO_EXT_CFG_BASE           0x0010061000
495 #define A_IO_EXT_MULT_SIZE_BASE     0x0010061100
496 #define A_IO_EXT_START_ADDR_BASE    0x0010061200
497 #define A_IO_EXT_TIME_CFG0_BASE     0x0010061600
498 #define A_IO_EXT_TIME_CFG1_BASE     0x0010061700
499 
500 #define IO_EXT_REGISTER_SPACING	    8
501 #define A_IO_EXT_CS_BASE(cs)	    (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
502 #define R_IO_EXT_REG(reg, cs)	    ((cs)*IO_EXT_REGISTER_SPACING + (reg))
503 
504 #define R_IO_EXT_CFG		    0x0000
505 #define R_IO_EXT_MULT_SIZE          0x0100
506 #define R_IO_EXT_START_ADDR	    0x0200
507 #define R_IO_EXT_TIME_CFG0          0x0600
508 #define R_IO_EXT_TIME_CFG1          0x0700
509 
510 
511 #define A_IO_INTERRUPT_STATUS       0x0010061A00
512 #define A_IO_INTERRUPT_DATA0        0x0010061A10
513 #define A_IO_INTERRUPT_DATA1        0x0010061A18
514 #define A_IO_INTERRUPT_DATA2        0x0010061A20
515 #define A_IO_INTERRUPT_DATA3        0x0010061A28
516 #define A_IO_INTERRUPT_ADDR0        0x0010061A30
517 #define A_IO_INTERRUPT_ADDR1        0x0010061A40
518 #define A_IO_INTERRUPT_PARITY       0x0010061A50
519 #define A_IO_PCMCIA_CFG             0x0010061A60
520 #define A_IO_PCMCIA_STATUS          0x0010061A70
521 #define A_IO_DRIVE_0		    0x0010061300
522 #define A_IO_DRIVE_1		    0x0010061308
523 #define A_IO_DRIVE_2		    0x0010061310
524 #define A_IO_DRIVE_3		    0x0010061318
525 #define A_IO_DRIVE_BASE		    A_IO_DRIVE_0
526 #define IO_DRIVE_REGISTER_SPACING   8
527 #define R_IO_DRIVE(x)		    ((x)*IO_DRIVE_REGISTER_SPACING)
528 #define A_IO_DRIVE(x)		    (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
529 
530 #define R_IO_INTERRUPT_STATUS       0x0A00
531 #define R_IO_INTERRUPT_DATA0        0x0A10
532 #define R_IO_INTERRUPT_DATA1        0x0A18
533 #define R_IO_INTERRUPT_DATA2        0x0A20
534 #define R_IO_INTERRUPT_DATA3        0x0A28
535 #define R_IO_INTERRUPT_ADDR0        0x0A30
536 #define R_IO_INTERRUPT_ADDR1        0x0A40
537 #define R_IO_INTERRUPT_PARITY       0x0A50
538 #define R_IO_PCMCIA_CFG             0x0A60
539 #define R_IO_PCMCIA_STATUS          0x0A70
540 
541 /*  *********************************************************************
542     * GPIO Registers
543     ********************************************************************* */
544 
545 #define A_GPIO_CLR_EDGE             0x0010061A80
546 #define A_GPIO_INT_TYPE             0x0010061A88
547 #define A_GPIO_INPUT_INVERT         0x0010061A90
548 #define A_GPIO_GLITCH               0x0010061A98
549 #define A_GPIO_READ                 0x0010061AA0
550 #define A_GPIO_DIRECTION            0x0010061AA8
551 #define A_GPIO_PIN_CLR              0x0010061AB0
552 #define A_GPIO_PIN_SET              0x0010061AB8
553 
554 #define A_GPIO_BASE		    0x0010061A80
555 
556 #define R_GPIO_CLR_EDGE             0x00
557 #define R_GPIO_INT_TYPE             0x08
558 #define R_GPIO_INPUT_INVERT         0x10
559 #define R_GPIO_GLITCH               0x18
560 #define R_GPIO_READ                 0x20
561 #define R_GPIO_DIRECTION            0x28
562 #define R_GPIO_PIN_CLR              0x30
563 #define R_GPIO_PIN_SET              0x38
564 
565 /*  *********************************************************************
566     * SMBus Registers
567     ********************************************************************* */
568 
569 #define A_SMB_XTRA_0                0x0010060000
570 #define A_SMB_XTRA_1                0x0010060008
571 #define A_SMB_FREQ_0                0x0010060010
572 #define A_SMB_FREQ_1                0x0010060018
573 #define A_SMB_STATUS_0              0x0010060020
574 #define A_SMB_STATUS_1              0x0010060028
575 #define A_SMB_CMD_0                 0x0010060030
576 #define A_SMB_CMD_1                 0x0010060038
577 #define A_SMB_START_0               0x0010060040
578 #define A_SMB_START_1               0x0010060048
579 #define A_SMB_DATA_0                0x0010060050
580 #define A_SMB_DATA_1                0x0010060058
581 #define A_SMB_CONTROL_0             0x0010060060
582 #define A_SMB_CONTROL_1             0x0010060068
583 #define A_SMB_PEC_0                 0x0010060070
584 #define A_SMB_PEC_1                 0x0010060078
585 
586 #define A_SMB_0                     0x0010060000
587 #define A_SMB_1                     0x0010060008
588 #define SMB_REGISTER_SPACING        0x8
589 #define A_SMB_BASE(idx)             (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
590 #define A_SMB_REGISTER(idx, reg)    (A_SMB_BASE(idx)+(reg))
591 
592 #define R_SMB_XTRA                  0x0000000000
593 #define R_SMB_FREQ                  0x0000000010
594 #define R_SMB_STATUS                0x0000000020
595 #define R_SMB_CMD                   0x0000000030
596 #define R_SMB_START                 0x0000000040
597 #define R_SMB_DATA                  0x0000000050
598 #define R_SMB_CONTROL               0x0000000060
599 #define R_SMB_PEC                   0x0000000070
600 
601 /*  *********************************************************************
602     * Timer Registers
603     ********************************************************************* */
604 
605 /*
606  * Watchdog timers
607  */
608 
609 #define A_SCD_WDOG_0		    0x0010020050
610 #define A_SCD_WDOG_1                0x0010020150
611 #define SCD_WDOG_SPACING            0x100
612 #define SCD_NUM_WDOGS		    2
613 #define A_SCD_WDOG_BASE(w)          (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
614 #define A_SCD_WDOG_REGISTER(w, r)   (A_SCD_WDOG_BASE(w) + (r))
615 
616 #define R_SCD_WDOG_INIT		    0x0000000000
617 #define R_SCD_WDOG_CNT		    0x0000000008
618 #define R_SCD_WDOG_CFG		    0x0000000010
619 
620 #define A_SCD_WDOG_INIT_0           0x0010020050
621 #define A_SCD_WDOG_CNT_0            0x0010020058
622 #define A_SCD_WDOG_CFG_0            0x0010020060
623 
624 #define A_SCD_WDOG_INIT_1           0x0010020150
625 #define A_SCD_WDOG_CNT_1            0x0010020158
626 #define A_SCD_WDOG_CFG_1            0x0010020160
627 
628 /*
629  * Generic timers
630  */
631 
632 #define A_SCD_TIMER_0		    0x0010020070
633 #define A_SCD_TIMER_1               0x0010020078
634 #define A_SCD_TIMER_2		    0x0010020170
635 #define A_SCD_TIMER_3               0x0010020178
636 #define SCD_NUM_TIMERS		    4
637 #define A_SCD_TIMER_BASE(w)         (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
638 #define A_SCD_TIMER_REGISTER(w, r)  (A_SCD_TIMER_BASE(w) + (r))
639 
640 #define R_SCD_TIMER_INIT	    0x0000000000
641 #define R_SCD_TIMER_CNT		    0x0000000010
642 #define R_SCD_TIMER_CFG		    0x0000000020
643 
644 #define A_SCD_TIMER_INIT_0          0x0010020070
645 #define A_SCD_TIMER_CNT_0           0x0010020080
646 #define A_SCD_TIMER_CFG_0           0x0010020090
647 
648 #define A_SCD_TIMER_INIT_1          0x0010020078
649 #define A_SCD_TIMER_CNT_1           0x0010020088
650 #define A_SCD_TIMER_CFG_1           0x0010020098
651 
652 #define A_SCD_TIMER_INIT_2          0x0010020170
653 #define A_SCD_TIMER_CNT_2           0x0010020180
654 #define A_SCD_TIMER_CFG_2           0x0010020190
655 
656 #define A_SCD_TIMER_INIT_3          0x0010020178
657 #define A_SCD_TIMER_CNT_3           0x0010020188
658 #define A_SCD_TIMER_CFG_3           0x0010020198
659 
660 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
661 #define A_SCD_SCRATCH		   0x0010020C10
662 #endif /* 1250 PASS2 || 112x PASS1 */
663 
664 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
665 #define A_SCD_ZBBUS_CYCLE_COUNT	   0x0010030000
666 #define A_SCD_ZBBUS_CYCLE_CP0	   0x0010020C00
667 #define A_SCD_ZBBUS_CYCLE_CP1	   0x0010020C08
668 #endif
669 
670 /*  *********************************************************************
671     * System Control Registers
672     ********************************************************************* */
673 
674 #define A_SCD_SYSTEM_REVISION       0x0010020000
675 #define A_SCD_SYSTEM_CFG            0x0010020008
676 #define A_SCD_SYSTEM_MANUF          0x0010038000
677 
678 /*  *********************************************************************
679     * System Address Trap Registers
680     ********************************************************************* */
681 
682 #define A_ADDR_TRAP_INDEX           0x00100200B0
683 #define A_ADDR_TRAP_REG             0x00100200B8
684 #define A_ADDR_TRAP_UP_0            0x0010020400
685 #define A_ADDR_TRAP_UP_1            0x0010020408
686 #define A_ADDR_TRAP_UP_2            0x0010020410
687 #define A_ADDR_TRAP_UP_3            0x0010020418
688 #define A_ADDR_TRAP_DOWN_0          0x0010020420
689 #define A_ADDR_TRAP_DOWN_1          0x0010020428
690 #define A_ADDR_TRAP_DOWN_2          0x0010020430
691 #define A_ADDR_TRAP_DOWN_3          0x0010020438
692 #define A_ADDR_TRAP_CFG_0           0x0010020440
693 #define A_ADDR_TRAP_CFG_1           0x0010020448
694 #define A_ADDR_TRAP_CFG_2           0x0010020450
695 #define A_ADDR_TRAP_CFG_3           0x0010020458
696 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
697 #define A_ADDR_TRAP_REG_DEBUG	    0x0010020460
698 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
699 
700 #define ADDR_TRAP_SPACING 8
701 #define NUM_ADDR_TRAP 4
702 #define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING))
703 #define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING))
704 #define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING))
705 
706 
707 /*  *********************************************************************
708     * System Interrupt Mapper Registers
709     ********************************************************************* */
710 
711 #define A_IMR_CPU0_BASE                 0x0010020000
712 #define A_IMR_CPU1_BASE                 0x0010022000
713 #define IMR_REGISTER_SPACING            0x2000
714 #define IMR_REGISTER_SPACING_SHIFT      13
715 
716 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
717 #define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg))
718 
719 #define R_IMR_INTERRUPT_DIAG            0x0010
720 #define R_IMR_INTERRUPT_LDT             0x0018
721 #define R_IMR_INTERRUPT_MASK            0x0028
722 #define R_IMR_INTERRUPT_TRACE           0x0038
723 #define R_IMR_INTERRUPT_SOURCE_STATUS   0x0040
724 #define R_IMR_LDT_INTERRUPT_SET         0x0048
725 #define R_IMR_LDT_INTERRUPT             0x0018
726 #define R_IMR_LDT_INTERRUPT_CLR         0x0020
727 #define R_IMR_MAILBOX_CPU               0x00c0
728 #define R_IMR_ALIAS_MAILBOX_CPU         0x1000
729 #define R_IMR_MAILBOX_SET_CPU           0x00C8
730 #define R_IMR_ALIAS_MAILBOX_SET_CPU     0x1008
731 #define R_IMR_MAILBOX_CLR_CPU           0x00D0
732 #define R_IMR_INTERRUPT_STATUS_BASE     0x0100
733 #define R_IMR_INTERRUPT_STATUS_COUNT    7
734 #define R_IMR_INTERRUPT_MAP_BASE        0x0200
735 #define R_IMR_INTERRUPT_MAP_COUNT       64
736 
737 /*
738  * these macros work together to build the address of a mailbox
739  * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1)
740  * for mbox_0_set_cpu2 returns 0x00100240C8
741  */
742 #define A_MAILBOX_REGISTER(reg,cpu) \
743     (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)
744 
745 /*  *********************************************************************
746     * System Performance Counter Registers
747     ********************************************************************* */
748 
749 #define A_SCD_PERF_CNT_CFG          0x00100204C0
750 #define A_SCD_PERF_CNT_0            0x00100204D0
751 #define A_SCD_PERF_CNT_1            0x00100204D8
752 #define A_SCD_PERF_CNT_2            0x00100204E0
753 #define A_SCD_PERF_CNT_3            0x00100204E8
754 
755 #define SCD_NUM_PERF_CNT 4
756 #define SCD_PERF_CNT_SPACING 8
757 #define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING))
758 
759 /*  *********************************************************************
760     * System Bus Watcher Registers
761     ********************************************************************* */
762 
763 #define A_SCD_BUS_ERR_STATUS        0x0010020880
764 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
765 #define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0
766 #define A_BUS_ERR_STATUS_DEBUG  0x00100208D0
767 #endif /* 1250 PASS2 || 112x PASS1 */
768 #define A_BUS_ERR_DATA_0            0x00100208A0
769 #define A_BUS_ERR_DATA_1            0x00100208A8
770 #define A_BUS_ERR_DATA_2            0x00100208B0
771 #define A_BUS_ERR_DATA_3            0x00100208B8
772 #define A_BUS_L2_ERRORS             0x00100208C0
773 #define A_BUS_MEM_IO_ERRORS         0x00100208C8
774 
775 /*  *********************************************************************
776     * System Debug Controller Registers
777     ********************************************************************* */
778 
779 #define A_SCD_JTAG_BASE             0x0010000000
780 
781 /*  *********************************************************************
782     * System Trace Buffer Registers
783     ********************************************************************* */
784 
785 #define A_SCD_TRACE_CFG             0x0010020A00
786 #define A_SCD_TRACE_READ            0x0010020A08
787 #define A_SCD_TRACE_EVENT_0         0x0010020A20
788 #define A_SCD_TRACE_EVENT_1         0x0010020A28
789 #define A_SCD_TRACE_EVENT_2         0x0010020A30
790 #define A_SCD_TRACE_EVENT_3         0x0010020A38
791 #define A_SCD_TRACE_SEQUENCE_0      0x0010020A40
792 #define A_SCD_TRACE_SEQUENCE_1      0x0010020A48
793 #define A_SCD_TRACE_SEQUENCE_2      0x0010020A50
794 #define A_SCD_TRACE_SEQUENCE_3      0x0010020A58
795 #define A_SCD_TRACE_EVENT_4         0x0010020A60
796 #define A_SCD_TRACE_EVENT_5         0x0010020A68
797 #define A_SCD_TRACE_EVENT_6         0x0010020A70
798 #define A_SCD_TRACE_EVENT_7         0x0010020A78
799 #define A_SCD_TRACE_SEQUENCE_4      0x0010020A80
800 #define A_SCD_TRACE_SEQUENCE_5      0x0010020A88
801 #define A_SCD_TRACE_SEQUENCE_6      0x0010020A90
802 #define A_SCD_TRACE_SEQUENCE_7      0x0010020A98
803 
804 #define TRACE_REGISTER_SPACING 8
805 #define TRACE_NUM_REGISTERS    8
806 #define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \
807    (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
808    (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING)))
809 #define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \
810    (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
811    (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING)))
812 
813 /*  *********************************************************************
814     * System Generic DMA Registers
815     ********************************************************************* */
816 
817 #define A_DM_0		  	    0x0010020B00
818 #define A_DM_1		  	    0x0010020B20
819 #define A_DM_2			    0x0010020B40
820 #define A_DM_3			    0x0010020B60
821 #define DM_REGISTER_SPACING	    0x20
822 #define DM_NUM_CHANNELS		    4
823 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
824 #define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg))
825 
826 #define R_DM_DSCR_BASE		    0x0000000000
827 #define R_DM_DSCR_COUNT		    0x0000000008
828 #define R_DM_CUR_DSCR_ADDR	    0x0000000010
829 #define R_DM_DSCR_BASE_DEBUG	    0x0000000018
830 
831 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
832 #define A_DM_PARTIAL_0		    0x0010020ba0
833 #define A_DM_PARTIAL_1		    0x0010020ba8
834 #define A_DM_PARTIAL_2		    0x0010020bb0
835 #define A_DM_PARTIAL_3		    0x0010020bb8
836 #define DM_PARTIAL_REGISTER_SPACING 0x8
837 #define A_DM_PARTIAL(idx)	    (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))
838 #endif /* 1250 PASS3 || 112x PASS1 */
839 
840 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
841 #define A_DM_CRC_0		    0x0010020b80
842 #define A_DM_CRC_1		    0x0010020b90
843 #define DM_CRC_REGISTER_SPACING	    0x10
844 #define DM_CRC_NUM_CHANNELS	    2
845 #define A_DM_CRC_BASE(idx)	    (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
846 #define A_DM_CRC_REGISTER(idx, reg)  (A_DM_CRC_BASE(idx) + (reg))
847 
848 #define R_CRC_DEF_0		    0x00
849 #define R_CTCP_DEF_0		    0x08
850 #endif /* 1250 PASS3 || 112x PASS1 */
851 
852 /*  *********************************************************************
853     *  Physical Address Map
854     ********************************************************************* */
855 
856 #if SIBYTE_HDR_FEATURE_1250_112x
857 #define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
858 #define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
859 #define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
860 #define A_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
861 #define A_PHYS_GENBUS			_SB_MAKE64(0x0010090000)
862 #define A_PHYS_GENBUS_END		_SB_MAKE64(0x0040000000)
863 #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
864 #define A_PHYS_LDTPCI_IO_MATCH_BITS_32  _SB_MAKE64(0x0060000000)
865 #define A_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
866 #define A_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
867 #define A_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
868 #define A_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
869 #define A_PHYS_LDT_SPECIAL_MATCH_BYTES  _SB_MAKE64(0x00D8000000)
870 #define A_PHYS_LDTPCI_IO_MATCH_BYTES    _SB_MAKE64(0x00DC000000)
871 #define A_PHYS_LDTPCI_CFG_MATCH_BYTES   _SB_MAKE64(0x00DE000000)
872 #define A_PHYS_LDT_SPECIAL_MATCH_BITS   _SB_MAKE64(0x00F8000000)
873 #define A_PHYS_LDTPCI_IO_MATCH_BITS     _SB_MAKE64(0x00FC000000)
874 #define A_PHYS_LDTPCI_CFG_MATCH_BITS    _SB_MAKE64(0x00FE000000)
875 #define A_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
876 #define A_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
877 #define A_PHYS_LDT_EXP                  _SB_MAKE64(0x8000000000)
878 #define A_PHYS_PCI_FULLACCESS_BYTES     _SB_MAKE64(0xF000000000)
879 #define A_PHYS_PCI_FULLACCESS_BITS      _SB_MAKE64(0xF100000000)
880 #define A_PHYS_RESERVED                 _SB_MAKE64(0xF200000000)
881 #define A_PHYS_RESERVED_SPECIAL_LDT     _SB_MAKE64(0xFD00000000)
882 
883 #define A_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
884 #define PHYS_L2CACHE_NUM_WAYS           4
885 #define A_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000080000)
886 #define A_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0180000)
887 #define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)
888 #define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)
889 #define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)
890 #endif
891 
892 
893 #endif
894