1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 7 #ifndef __ANX7625_H__ 8 #define __ANX7625_H__ 9 10 #define ANX7625_DRV_VERSION "0.1.04" 11 12 /* Loading OCM re-trying times */ 13 #define OCM_LOADING_TIME 10 14 15 /********* ANX7625 Register **********/ 16 #define TX_P0_ADDR 0x70 17 #define TX_P1_ADDR 0x7A 18 #define TX_P2_ADDR 0x72 19 20 #define RX_P0_ADDR 0x7e 21 #define RX_P1_ADDR 0x84 22 #define RX_P2_ADDR 0x54 23 24 #define RSVD_00_ADDR 0x00 25 #define RSVD_D1_ADDR 0xD1 26 #define RSVD_60_ADDR 0x60 27 #define RSVD_39_ADDR 0x39 28 #define RSVD_7F_ADDR 0x7F 29 30 #define TCPC_INTERFACE_ADDR 0x58 31 32 /* Clock frequency in Hz */ 33 #define XTAL_FRQ (27 * 1000000) 34 35 #define POST_DIVIDER_MIN 1 36 #define POST_DIVIDER_MAX 16 37 #define PLL_OUT_FREQ_MIN 520000000UL 38 #define PLL_OUT_FREQ_MAX 730000000UL 39 #define PLL_OUT_FREQ_ABS_MIN 300000000UL 40 #define PLL_OUT_FREQ_ABS_MAX 800000000UL 41 #define MAX_UNSIGNED_24BIT 16777215UL 42 43 /***************************************************************/ 44 /* Register definition of device address 0x58 */ 45 46 #define PRODUCT_ID_L 0x02 47 #define PRODUCT_ID_H 0x03 48 49 #define INTR_ALERT_1 0xCC 50 #define INTR_SOFTWARE_INT BIT(3) 51 #define INTR_RECEIVED_MSG BIT(5) 52 53 #define SYSTEM_STSTUS 0x45 54 #define INTERFACE_CHANGE_INT 0x44 55 #define HPD_STATUS_CHANGE 0x80 56 #define HPD_STATUS 0x80 57 58 /******** END of I2C Address 0x58 ********/ 59 60 /***************************************************************/ 61 /* Register definition of device address 0x70 */ 62 #define TX_HDCP_CTRL0 0x01 63 #define STORE_AN BIT(7) 64 #define RX_REPEATER BIT(6) 65 #define RE_AUTHEN BIT(5) 66 #define SW_AUTH_OK BIT(4) 67 #define HARD_AUTH_EN BIT(3) 68 #define ENC_EN BIT(2) 69 #define BKSV_SRM_PASS BIT(1) 70 #define KSVLIST_VLD BIT(0) 71 72 #define SP_TX_WAIT_R0_TIME 0x40 73 #define SP_TX_WAIT_KSVR_TIME 0x42 74 #define SP_TX_SYS_CTRL1_REG 0x80 75 #define HDCP2TX_FW_EN BIT(4) 76 77 #define SP_TX_LINK_BW_SET_REG 0xA0 78 #define SP_TX_LANE_COUNT_SET_REG 0xA1 79 80 #define M_VID_0 0xC0 81 #define M_VID_1 0xC1 82 #define M_VID_2 0xC2 83 #define N_VID_0 0xC3 84 #define N_VID_1 0xC4 85 #define N_VID_2 0xC5 86 87 #define KEY_START_ADDR 0x9000 88 #define KEY_RESERVED 416 89 90 #define HDCP14KEY_START_ADDR (KEY_START_ADDR + KEY_RESERVED) 91 #define HDCP14KEY_SIZE 624 92 93 /***************************************************************/ 94 /* Register definition of device address 0x72 */ 95 #define AUX_RST 0x04 96 #define RST_CTRL2 0x07 97 98 #define SP_TX_TOTAL_LINE_STA_L 0x24 99 #define SP_TX_TOTAL_LINE_STA_H 0x25 100 #define SP_TX_ACT_LINE_STA_L 0x26 101 #define SP_TX_ACT_LINE_STA_H 0x27 102 #define SP_TX_V_F_PORCH_STA 0x28 103 #define SP_TX_V_SYNC_STA 0x29 104 #define SP_TX_V_B_PORCH_STA 0x2A 105 #define SP_TX_TOTAL_PIXEL_STA_L 0x2B 106 #define SP_TX_TOTAL_PIXEL_STA_H 0x2C 107 #define SP_TX_ACT_PIXEL_STA_L 0x2D 108 #define SP_TX_ACT_PIXEL_STA_H 0x2E 109 #define SP_TX_H_F_PORCH_STA_L 0x2F 110 #define SP_TX_H_F_PORCH_STA_H 0x30 111 #define SP_TX_H_SYNC_STA_L 0x31 112 #define SP_TX_H_SYNC_STA_H 0x32 113 #define SP_TX_H_B_PORCH_STA_L 0x33 114 #define SP_TX_H_B_PORCH_STA_H 0x34 115 116 #define SP_TX_VID_CTRL 0x84 117 #define SP_TX_BPC_MASK 0xE0 118 #define SP_TX_BPC_6 0x00 119 #define SP_TX_BPC_8 0x20 120 #define SP_TX_BPC_10 0x40 121 #define SP_TX_BPC_12 0x60 122 123 #define VIDEO_BIT_MATRIX_12 0x4c 124 125 #define AUDIO_CHANNEL_STATUS_1 0xd0 126 #define AUDIO_CHANNEL_STATUS_2 0xd1 127 #define AUDIO_CHANNEL_STATUS_3 0xd2 128 #define AUDIO_CHANNEL_STATUS_4 0xd3 129 #define AUDIO_CHANNEL_STATUS_5 0xd4 130 #define AUDIO_CHANNEL_STATUS_6 0xd5 131 #define TDM_SLAVE_MODE 0x10 132 #define I2S_SLAVE_MODE 0x08 133 #define AUDIO_LAYOUT 0x01 134 135 #define HPD_DET_TIMER_BIT0_7 0xea 136 #define HPD_DET_TIMER_BIT8_15 0xeb 137 #define HPD_DET_TIMER_BIT16_23 0xec 138 /* HPD debounce time 2ms for 27M clock */ 139 #define HPD_TIME 54000 140 141 #define AUDIO_CONTROL_REGISTER 0xe6 142 #define TDM_TIMING_MODE 0x08 143 144 #define I2C_ADDR_72_DPTX 0x72 145 146 #define HP_MIN 8 147 #define HBLANKING_MIN 80 148 #define SYNC_LEN_DEF 32 149 #define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2) 150 #define VIDEO_CONTROL_0 0x08 151 152 #define ACTIVE_LINES_L 0x14 153 #define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */ 154 #define VERTICAL_FRONT_PORCH 0x16 155 #define VERTICAL_SYNC_WIDTH 0x17 156 #define VERTICAL_BACK_PORCH 0x18 157 158 #define HORIZONTAL_TOTAL_PIXELS_L 0x19 159 #define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */ 160 #define HORIZONTAL_ACTIVE_PIXELS_L 0x1B 161 #define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */ 162 #define HORIZONTAL_FRONT_PORCH_L 0x1D 163 #define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */ 164 #define HORIZONTAL_SYNC_WIDTH_L 0x1F 165 #define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */ 166 #define HORIZONTAL_BACK_PORCH_L 0x21 167 #define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */ 168 169 /******** END of I2C Address 0x72 *********/ 170 171 /***************************************************************/ 172 /* Register definition of device address 0x7a */ 173 #define DP_TX_SWING_REG_CNT 0x14 174 #define DP_TX_LANE0_SWING_REG0 0x00 175 #define DP_TX_LANE1_SWING_REG0 0x14 176 /******** END of I2C Address 0x7a *********/ 177 178 /***************************************************************/ 179 /* Register definition of device address 0x7e */ 180 181 #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E 182 183 #define R_BOOT_RETRY 0x00 184 #define R_RAM_ADDR_H 0x01 185 #define R_RAM_ADDR_L 0x02 186 #define R_RAM_LEN_H 0x03 187 #define R_RAM_LEN_L 0x04 188 #define FLASH_LOAD_STA 0x05 189 #define FLASH_LOAD_STA_CHK BIT(7) 190 191 #define R_RAM_CTRL 0x05 192 /* bit positions */ 193 #define FLASH_DONE BIT(7) 194 #define BOOT_LOAD_DONE BIT(6) 195 #define CRC_OK BIT(5) 196 #define LOAD_DONE BIT(4) 197 #define O_RW_DONE BIT(3) 198 #define FUSE_BUSY BIT(2) 199 #define DECRYPT_EN BIT(1) 200 #define LOAD_START BIT(0) 201 202 #define FLASH_ADDR_HIGH 0x0F 203 #define FLASH_ADDR_LOW 0x10 204 #define FLASH_LEN_HIGH 0x31 205 #define FLASH_LEN_LOW 0x32 206 #define R_FLASH_RW_CTRL 0x33 207 /* bit positions */ 208 #define READ_DELAY_SELECT BIT(7) 209 #define GENERAL_INSTRUCTION_EN BIT(6) 210 #define FLASH_ERASE_EN BIT(5) 211 #define RDID_READ_EN BIT(4) 212 #define REMS_READ_EN BIT(3) 213 #define WRITE_STATUS_EN BIT(2) 214 #define FLASH_READ BIT(1) 215 #define FLASH_WRITE BIT(0) 216 217 #define FLASH_BUF_BASE_ADDR 0x60 218 #define FLASH_BUF_LEN 0x20 219 220 #define XTAL_FRQ_SEL 0x3F 221 /* bit field positions */ 222 #define XTAL_FRQ_SEL_POS 5 223 /* bit field values */ 224 #define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) 225 #define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) 226 227 #define R_DSC_CTRL_0 0x40 228 #define READ_STATUS_EN 7 229 #define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ 230 #define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */ 231 #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ 232 233 #define OCM_FW_VERSION 0x31 234 #define OCM_FW_REVERSION 0x32 235 236 #define AP_AUX_ADDR_7_0 0x11 237 #define AP_AUX_ADDR_15_8 0x12 238 #define AP_AUX_ADDR_19_16 0x13 239 240 /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ 241 #define AP_AUX_CTRL_STATUS 0x14 242 #define AP_AUX_CTRL_OP_EN 0x10 243 #define AP_AUX_CTRL_ADDRONLY 0x20 244 245 #define AP_AUX_BUFF_START 0x15 246 #define PIXEL_CLOCK_L 0x25 247 #define PIXEL_CLOCK_H 0x26 248 249 #define AP_AUX_COMMAND 0x27 /* com+len */ 250 #define LENGTH_SHIFT 4 251 #define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd)) 252 253 /* Bit 0&1: 3D video structure */ 254 /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ 255 #define AP_AV_STATUS 0x28 256 #define AP_VIDEO_CHG BIT(2) 257 #define AP_AUDIO_CHG BIT(3) 258 #define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */ 259 #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */ 260 #define AP_DISABLE_PD BIT(6) 261 #define AP_DISABLE_DISPLAY BIT(7) 262 263 #define GPIO_CTRL_2 0x49 264 #define HPD_SOURCE BIT(6) 265 266 /***************************************************************/ 267 /* Register definition of device address 0x84 */ 268 #define MIPI_PHY_CONTROL_3 0x03 269 #define MIPI_HS_PWD_CLK 7 270 #define MIPI_HS_RT_CLK 6 271 #define MIPI_PD_CLK 5 272 #define MIPI_CLK_RT_MANUAL_PD_EN 4 273 #define MIPI_CLK_HS_MANUAL_PD_EN 3 274 #define MIPI_CLK_DET_DET_BYPASS 2 275 #define MIPI_CLK_MISS_CTRL 1 276 #define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 277 278 #define MIPI_LANE_CTRL_0 0x05 279 #define MIPI_TIME_HS_PRPR 0x08 280 281 /* 282 * After MIPI RX protocol layer received video frames, 283 * Protocol layer starts to reconstruct video stream from PHY 284 */ 285 #define MIPI_VIDEO_STABLE_CNT 0x0A 286 287 #define MIPI_LANE_CTRL_10 0x0F 288 #define MIPI_DIGITAL_ADJ_1 0x1B 289 #define IVO_MID0 0x26 290 #define IVO_MID1 0xCF 291 292 #define MIPI_PLL_M_NUM_23_16 0x1E 293 #define MIPI_PLL_M_NUM_15_8 0x1F 294 #define MIPI_PLL_M_NUM_7_0 0x20 295 #define MIPI_PLL_N_NUM_23_16 0x21 296 #define MIPI_PLL_N_NUM_15_8 0x22 297 #define MIPI_PLL_N_NUM_7_0 0x23 298 299 #define MIPI_DIGITAL_PLL_6 0x2A 300 /* Bit[7:6]: VCO band control, only effective */ 301 #define MIPI_M_NUM_READY 0x10 302 #define MIPI_N_NUM_READY 0x08 303 #define STABLE_INTEGER_CNT_EN 0x04 304 #define MIPI_PLL_TEST_BIT 0 305 /* Bit[1:0]: test point output select - */ 306 /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ 307 308 #define MIPI_DIGITAL_PLL_7 0x2B 309 #define MIPI_PLL_FORCE_N_EN 7 310 #define MIPI_PLL_FORCE_BAND_EN 6 311 312 #define MIPI_PLL_VCO_TUNE_REG 4 313 /* Bit[5:4]: VCO metal capacitance - */ 314 /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ 315 #define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 316 317 #define MIPI_PLL_PLL_LDO_BIT 2 318 /* Bit[3:2]: vco_v2i power - */ 319 /* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ 320 #define MIPI_PLL_RESET_N 0x02 321 #define MIPI_FRQ_FORCE_NDET 0 322 323 #define MIPI_ALERT_CLR_0 0x2D 324 #define HS_link_error_clear 7 325 /* This bit itself is S/C, and it clears 0x84:0x31[7] */ 326 327 #define MIPI_ALERT_OUT_0 0x31 328 #define check_sum_err_hs_sync 7 329 /* This bit is cleared by 0x84:0x2D[7] */ 330 331 #define MIPI_DIGITAL_PLL_8 0x33 332 #define MIPI_POST_DIV_VAL 4 333 /* N means divided by (n+1), n = 0~15 */ 334 #define MIPI_EN_LOCK_FRZ 3 335 #define MIPI_FRQ_COUNTER_RST 2 336 #define MIPI_FRQ_SET_REG_8 1 337 /* Bit 0 is reserved */ 338 339 #define MIPI_DIGITAL_PLL_9 0x34 340 341 #define MIPI_DIGITAL_PLL_16 0x3B 342 #define MIPI_FRQ_FREEZE_NDET 7 343 #define MIPI_FRQ_REG_SET_ENABLE 6 344 #define MIPI_REG_FORCE_SEL_EN 5 345 #define MIPI_REG_SEL_DIV_REG 4 346 #define MIPI_REG_FORCE_PRE_DIV_EN 3 347 /* Bit 2 is reserved */ 348 #define MIPI_FREF_D_IND 1 349 #define REF_CLK_27000KHZ 1 350 #define REF_CLK_19200KHZ 0 351 #define MIPI_REG_PLL_PLL_TEST_ENABLE 0 352 353 #define MIPI_DIGITAL_PLL_18 0x3D 354 #define FRQ_COUNT_RB_SEL 7 355 #define REG_FORCE_POST_DIV_EN 6 356 #define MIPI_DPI_SELECT 5 357 #define SELECT_DSI 1 358 #define SELECT_DPI 0 359 #define REG_BAUD_DIV_RATIO 0 360 361 #define H_BLANK_L 0x3E 362 /* For DSC only */ 363 #define H_BLANK_H 0x3F 364 /* For DSC only; note: bit[7:6] are reserved */ 365 #define MIPI_SWAP 0x4A 366 #define MIPI_SWAP_CH0 7 367 #define MIPI_SWAP_CH1 6 368 #define MIPI_SWAP_CH2 5 369 #define MIPI_SWAP_CH3 4 370 #define MIPI_SWAP_CLK 3 371 /* Bit[2:0] are reserved */ 372 373 /******** END of I2C Address 0x84 *********/ 374 375 /* DPCD regs */ 376 #define DPCD_DPCD_REV 0x00 377 #define DPCD_MAX_LINK_RATE 0x01 378 #define DPCD_MAX_LANE_COUNT 0x02 379 380 /********* ANX7625 Register End **********/ 381 382 /***************** Display *****************/ 383 enum audio_fs { 384 AUDIO_FS_441K = 0x00, 385 AUDIO_FS_48K = 0x02, 386 AUDIO_FS_32K = 0x03, 387 AUDIO_FS_882K = 0x08, 388 AUDIO_FS_96K = 0x0a, 389 AUDIO_FS_1764K = 0x0c, 390 AUDIO_FS_192K = 0x0e 391 }; 392 393 enum audio_wd_len { 394 AUDIO_W_LEN_16_20MAX = 0x02, 395 AUDIO_W_LEN_18_20MAX = 0x04, 396 AUDIO_W_LEN_17_20MAX = 0x0c, 397 AUDIO_W_LEN_19_20MAX = 0x08, 398 AUDIO_W_LEN_20_20MAX = 0x0a, 399 AUDIO_W_LEN_20_24MAX = 0x03, 400 AUDIO_W_LEN_22_24MAX = 0x05, 401 AUDIO_W_LEN_21_24MAX = 0x0d, 402 AUDIO_W_LEN_23_24MAX = 0x09, 403 AUDIO_W_LEN_24_24MAX = 0x0b 404 }; 405 406 #define I2S_CH_2 0x01 407 #define TDM_CH_4 0x03 408 #define TDM_CH_6 0x05 409 #define TDM_CH_8 0x07 410 411 #define MAX_DPCD_BUFFER_SIZE 16 412 413 #define ONE_BLOCK_SIZE 128 414 #define FOUR_BLOCK_SIZE (128 * 4) 415 416 #define MAX_EDID_BLOCK 3 417 #define EDID_TRY_CNT 3 418 #define SUPPORT_PIXEL_CLOCK 300000 419 420 struct s_edid_data { 421 int edid_block_num; 422 u8 edid_raw_data[FOUR_BLOCK_SIZE]; 423 }; 424 425 /***************** Display End *****************/ 426 427 #define MAX_LANES_SUPPORT 4 428 429 struct anx7625_platform_data { 430 struct gpio_desc *gpio_p_on; 431 struct gpio_desc *gpio_reset; 432 struct regulator_bulk_data supplies[3]; 433 struct drm_bridge *panel_bridge; 434 int intp_irq; 435 int is_dpi; 436 int mipi_lanes; 437 int audio_en; 438 int dp_lane0_swing_reg_cnt; 439 u8 lane0_reg_data[DP_TX_SWING_REG_CNT]; 440 int dp_lane1_swing_reg_cnt; 441 u8 lane1_reg_data[DP_TX_SWING_REG_CNT]; 442 u32 low_power_mode; 443 struct device_node *mipi_host_node; 444 }; 445 446 struct anx7625_i2c_client { 447 struct i2c_client *tx_p0_client; 448 struct i2c_client *tx_p1_client; 449 struct i2c_client *tx_p2_client; 450 struct i2c_client *rx_p0_client; 451 struct i2c_client *rx_p1_client; 452 struct i2c_client *rx_p2_client; 453 struct i2c_client *tcpc_client; 454 }; 455 456 struct anx7625_data { 457 struct anx7625_platform_data pdata; 458 struct platform_device *audio_pdev; 459 int hpd_status; 460 int hpd_high_cnt; 461 int dp_en; 462 int hdcp_cp; 463 /* Lock for work queue */ 464 struct mutex lock; 465 struct device *dev; 466 struct anx7625_i2c_client i2c; 467 struct i2c_client *last_client; 468 struct timer_list hdcp_timer; 469 struct s_edid_data slimport_edid_p; 470 struct device *codec_dev; 471 hdmi_codec_plugged_cb plugged_cb; 472 struct work_struct work; 473 struct workqueue_struct *workqueue; 474 struct delayed_work hdcp_work; 475 struct workqueue_struct *hdcp_workqueue; 476 /* Lock for hdcp work queue */ 477 struct mutex hdcp_wq_lock; 478 /* Lock for aux transfer and disable */ 479 struct mutex aux_lock; 480 char edid_block; 481 struct display_timing dt; 482 u8 display_timing_valid; 483 struct drm_bridge bridge; 484 u8 bridge_attached; 485 struct drm_connector *connector; 486 struct mipi_dsi_device *dsi; 487 struct drm_dp_aux aux; 488 }; 489 490 #endif /* __ANX7625_H__ */ 491