1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef MAC_H 18 #define MAC_H 19 20 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \ 21 MS(ads->ds_rxstatus0, AR_RxRate) : \ 22 (ads->ds_rxstatus3 >> 2) & 0xFF) 23 24 #define set11nTries(_series, _index) \ 25 (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) 26 27 #define set11nRate(_series, _index) \ 28 (SM((_series)[_index].Rate, AR_XmitRate##_index)) 29 30 #define set11nPktDurRTSCTS(_series, _index) \ 31 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ 32 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ 33 AR_RTSCTSQual##_index : 0)) 34 35 #define set11nRateFlags(_series, _index) \ 36 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ 37 AR_2040_##_index : 0) \ 38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 39 AR_GI##_index : 0) \ 40 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \ 41 AR_STBC##_index : 0) \ 42 |SM((_series)[_index].ChSel, AR_ChainSel##_index)) 43 44 #define CCK_SIFS_TIME 10 45 #define CCK_PREAMBLE_BITS 144 46 #define CCK_PLCP_BITS 48 47 48 #define OFDM_SIFS_TIME 16 49 #define OFDM_PREAMBLE_TIME 20 50 #define OFDM_PLCP_BITS 22 51 #define OFDM_SYMBOL_TIME 4 52 53 #define OFDM_SIFS_TIME_HALF 32 54 #define OFDM_PREAMBLE_TIME_HALF 40 55 #define OFDM_PLCP_BITS_HALF 22 56 #define OFDM_SYMBOL_TIME_HALF 8 57 58 #define OFDM_SIFS_TIME_QUARTER 64 59 #define OFDM_PREAMBLE_TIME_QUARTER 80 60 #define OFDM_PLCP_BITS_QUARTER 22 61 #define OFDM_SYMBOL_TIME_QUARTER 16 62 63 #define INIT_AIFS 2 64 #define INIT_CWMIN 15 65 #define INIT_CWMIN_11B 31 66 #define INIT_CWMAX 1023 67 #define INIT_SH_RETRY 10 68 #define INIT_LG_RETRY 10 69 #define INIT_SSH_RETRY 32 70 #define INIT_SLG_RETRY 32 71 72 #define ATH9K_SLOT_TIME_6 6 73 #define ATH9K_SLOT_TIME_9 9 74 #define ATH9K_SLOT_TIME_20 20 75 76 #define ATH9K_TXERR_XRETRY 0x01 77 #define ATH9K_TXERR_FILT 0x02 78 #define ATH9K_TXERR_FIFO 0x04 79 #define ATH9K_TXERR_XTXOP 0x08 80 #define ATH9K_TXERR_TIMER_EXPIRED 0x10 81 #define ATH9K_TX_ACKED 0x20 82 #define ATH9K_TXERR_MASK \ 83 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \ 84 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED) 85 86 #define ATH9K_TX_BA 0x01 87 #define ATH9K_TX_PWRMGMT 0x02 88 #define ATH9K_TX_DESC_CFG_ERR 0x04 89 #define ATH9K_TX_DATA_UNDERRUN 0x08 90 #define ATH9K_TX_DELIM_UNDERRUN 0x10 91 #define ATH9K_TX_SW_FILTERED 0x80 92 93 /* 64 bytes */ 94 #define MIN_TX_FIFO_THRESHOLD 0x1 95 96 /* 97 * Single stream device AR9285 and AR9271 require 2 KB 98 * to work around a hardware issue, all other devices 99 * have can use the max 4 KB limit. 100 */ 101 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) 102 103 struct ath_tx_status { 104 u32 ts_tstamp; 105 u16 ts_seqnum; 106 u8 ts_status; 107 u8 ts_rateindex; 108 int8_t ts_rssi; 109 u8 ts_shortretry; 110 u8 ts_longretry; 111 u8 ts_virtcol; 112 u8 ts_flags; 113 int8_t ts_rssi_ctl0; 114 int8_t ts_rssi_ctl1; 115 int8_t ts_rssi_ctl2; 116 int8_t ts_rssi_ext0; 117 int8_t ts_rssi_ext1; 118 int8_t ts_rssi_ext2; 119 u8 qid; 120 u16 desc_id; 121 u8 tid; 122 u32 ba_low; 123 u32 ba_high; 124 u32 evm0; 125 u32 evm1; 126 u32 evm2; 127 }; 128 129 struct ath_rx_status { 130 u32 rs_tstamp; 131 u16 rs_datalen; 132 u8 rs_status; 133 u8 rs_phyerr; 134 int8_t rs_rssi; 135 u8 rs_keyix; 136 u8 rs_rate; 137 u8 rs_antenna; 138 u8 rs_more; 139 int8_t rs_rssi_ctl0; 140 int8_t rs_rssi_ctl1; 141 int8_t rs_rssi_ctl2; 142 int8_t rs_rssi_ext0; 143 int8_t rs_rssi_ext1; 144 int8_t rs_rssi_ext2; 145 u8 rs_isaggr; 146 u8 rs_moreaggr; 147 u8 rs_num_delims; 148 u8 rs_flags; 149 u32 evm0; 150 u32 evm1; 151 u32 evm2; 152 u32 evm3; 153 u32 evm4; 154 }; 155 156 struct ath_htc_rx_status { 157 __be64 rs_tstamp; 158 __be16 rs_datalen; 159 u8 rs_status; 160 u8 rs_phyerr; 161 int8_t rs_rssi; 162 int8_t rs_rssi_ctl0; 163 int8_t rs_rssi_ctl1; 164 int8_t rs_rssi_ctl2; 165 int8_t rs_rssi_ext0; 166 int8_t rs_rssi_ext1; 167 int8_t rs_rssi_ext2; 168 u8 rs_keyix; 169 u8 rs_rate; 170 u8 rs_antenna; 171 u8 rs_more; 172 u8 rs_isaggr; 173 u8 rs_moreaggr; 174 u8 rs_num_delims; 175 u8 rs_flags; 176 u8 rs_dummy; 177 __be32 evm0; 178 __be32 evm1; 179 __be32 evm2; 180 }; 181 182 #define ATH9K_RXERR_CRC 0x01 183 #define ATH9K_RXERR_PHY 0x02 184 #define ATH9K_RXERR_FIFO 0x04 185 #define ATH9K_RXERR_DECRYPT 0x08 186 #define ATH9K_RXERR_MIC 0x10 187 188 #define ATH9K_RX_MORE 0x01 189 #define ATH9K_RX_MORE_AGGR 0x02 190 #define ATH9K_RX_GI 0x04 191 #define ATH9K_RX_2040 0x08 192 #define ATH9K_RX_DELIM_CRC_PRE 0x10 193 #define ATH9K_RX_DELIM_CRC_POST 0x20 194 #define ATH9K_RX_DECRYPT_BUSY 0x40 195 196 #define ATH9K_RXKEYIX_INVALID ((u8)-1) 197 #define ATH9K_TXKEYIX_INVALID ((u32)-1) 198 199 enum ath9k_phyerr { 200 ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 201 ATH9K_PHYERR_TIMING = 1, /* Timing error */ 202 ATH9K_PHYERR_PARITY = 2, /* Illegal parity */ 203 ATH9K_PHYERR_RATE = 3, /* Illegal rate */ 204 ATH9K_PHYERR_LENGTH = 4, /* Illegal length */ 205 ATH9K_PHYERR_RADAR = 5, /* Radar detect */ 206 ATH9K_PHYERR_SERVICE = 6, /* Illegal service */ 207 ATH9K_PHYERR_TOR = 7, /* Transmit override receive */ 208 209 ATH9K_PHYERR_OFDM_TIMING = 17, 210 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18, 211 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19, 212 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20, 213 ATH9K_PHYERR_OFDM_POWER_DROP = 21, 214 ATH9K_PHYERR_OFDM_SERVICE = 22, 215 ATH9K_PHYERR_OFDM_RESTART = 23, 216 ATH9K_PHYERR_FALSE_RADAR_EXT = 24, 217 218 ATH9K_PHYERR_CCK_TIMING = 25, 219 ATH9K_PHYERR_CCK_HEADER_CRC = 26, 220 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27, 221 ATH9K_PHYERR_CCK_SERVICE = 30, 222 ATH9K_PHYERR_CCK_RESTART = 31, 223 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 32, 224 ATH9K_PHYERR_CCK_POWER_DROP = 33, 225 226 ATH9K_PHYERR_HT_CRC_ERROR = 34, 227 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 35, 228 ATH9K_PHYERR_HT_RATE_ILLEGAL = 36, 229 230 ATH9K_PHYERR_MAX = 37, 231 }; 232 233 struct ath_desc { 234 u32 ds_link; 235 u32 ds_data; 236 u32 ds_ctl0; 237 u32 ds_ctl1; 238 u32 ds_hw[20]; 239 void *ds_vdata; 240 } __packed __aligned(4); 241 242 #define ATH9K_TXDESC_CLRDMASK 0x0001 243 #define ATH9K_TXDESC_NOACK 0x0002 244 #define ATH9K_TXDESC_RTSENA 0x0004 245 #define ATH9K_TXDESC_CTSENA 0x0008 246 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for 247 * the descriptor its marked on. We take a tx interrupt to reap 248 * descriptors when the h/w hits an EOL condition or 249 * when the descriptor is specifically marked to generate 250 * an interrupt with this flag. Descriptors should be 251 * marked periodically to insure timely replenishing of the 252 * supply needed for sending frames. Defering interrupts 253 * reduces system load and potentially allows more concurrent 254 * work to be done but if done to aggressively can cause 255 * senders to backup. When the hardware queue is left too 256 * large rate control information may also be too out of 257 * date. An Alternative for this is TX interrupt mitigation 258 * but this needs more testing. */ 259 #define ATH9K_TXDESC_INTREQ 0x0010 260 #define ATH9K_TXDESC_VEOL 0x0020 261 #define ATH9K_TXDESC_EXT_ONLY 0x0040 262 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080 263 #define ATH9K_TXDESC_VMF 0x0100 264 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 265 #define ATH9K_TXDESC_LOWRXCHAIN 0x0400 266 #define ATH9K_TXDESC_LDPC 0x00010000 267 268 #define ATH9K_RXDESC_INTREQ 0x0020 269 270 struct ar5416_desc { 271 u32 ds_link; 272 u32 ds_data; 273 u32 ds_ctl0; 274 u32 ds_ctl1; 275 union { 276 struct { 277 u32 ctl2; 278 u32 ctl3; 279 u32 ctl4; 280 u32 ctl5; 281 u32 ctl6; 282 u32 ctl7; 283 u32 ctl8; 284 u32 ctl9; 285 u32 ctl10; 286 u32 ctl11; 287 u32 status0; 288 u32 status1; 289 u32 status2; 290 u32 status3; 291 u32 status4; 292 u32 status5; 293 u32 status6; 294 u32 status7; 295 u32 status8; 296 u32 status9; 297 } tx; 298 struct { 299 u32 status0; 300 u32 status1; 301 u32 status2; 302 u32 status3; 303 u32 status4; 304 u32 status5; 305 u32 status6; 306 u32 status7; 307 u32 status8; 308 } rx; 309 } u; 310 } __packed __aligned(4); 311 312 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) 313 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) 314 315 #define ds_ctl2 u.tx.ctl2 316 #define ds_ctl3 u.tx.ctl3 317 #define ds_ctl4 u.tx.ctl4 318 #define ds_ctl5 u.tx.ctl5 319 #define ds_ctl6 u.tx.ctl6 320 #define ds_ctl7 u.tx.ctl7 321 #define ds_ctl8 u.tx.ctl8 322 #define ds_ctl9 u.tx.ctl9 323 #define ds_ctl10 u.tx.ctl10 324 #define ds_ctl11 u.tx.ctl11 325 326 #define ds_txstatus0 u.tx.status0 327 #define ds_txstatus1 u.tx.status1 328 #define ds_txstatus2 u.tx.status2 329 #define ds_txstatus3 u.tx.status3 330 #define ds_txstatus4 u.tx.status4 331 #define ds_txstatus5 u.tx.status5 332 #define ds_txstatus6 u.tx.status6 333 #define ds_txstatus7 u.tx.status7 334 #define ds_txstatus8 u.tx.status8 335 #define ds_txstatus9 u.tx.status9 336 337 #define ds_rxstatus0 u.rx.status0 338 #define ds_rxstatus1 u.rx.status1 339 #define ds_rxstatus2 u.rx.status2 340 #define ds_rxstatus3 u.rx.status3 341 #define ds_rxstatus4 u.rx.status4 342 #define ds_rxstatus5 u.rx.status5 343 #define ds_rxstatus6 u.rx.status6 344 #define ds_rxstatus7 u.rx.status7 345 #define ds_rxstatus8 u.rx.status8 346 347 #define AR_FrameLen 0x00000fff 348 #define AR_VirtMoreFrag 0x00001000 349 #define AR_TxCtlRsvd00 0x0000e000 350 #define AR_XmitPower 0x003f0000 351 #define AR_XmitPower_S 16 352 #define AR_RTSEnable 0x00400000 353 #define AR_VEOL 0x00800000 354 #define AR_ClrDestMask 0x01000000 355 #define AR_TxCtlRsvd01 0x1e000000 356 #define AR_TxIntrReq 0x20000000 357 #define AR_DestIdxValid 0x40000000 358 #define AR_CTSEnable 0x80000000 359 360 #define AR_TxMore 0x00001000 361 #define AR_DestIdx 0x000fe000 362 #define AR_DestIdx_S 13 363 #define AR_FrameType 0x00f00000 364 #define AR_FrameType_S 20 365 #define AR_NoAck 0x01000000 366 #define AR_InsertTS 0x02000000 367 #define AR_CorruptFCS 0x04000000 368 #define AR_ExtOnly 0x08000000 369 #define AR_ExtAndCtl 0x10000000 370 #define AR_MoreAggr 0x20000000 371 #define AR_IsAggr 0x40000000 372 373 #define AR_BurstDur 0x00007fff 374 #define AR_BurstDur_S 0 375 #define AR_DurUpdateEna 0x00008000 376 #define AR_XmitDataTries0 0x000f0000 377 #define AR_XmitDataTries0_S 16 378 #define AR_XmitDataTries1 0x00f00000 379 #define AR_XmitDataTries1_S 20 380 #define AR_XmitDataTries2 0x0f000000 381 #define AR_XmitDataTries2_S 24 382 #define AR_XmitDataTries3 0xf0000000 383 #define AR_XmitDataTries3_S 28 384 385 #define AR_XmitRate0 0x000000ff 386 #define AR_XmitRate0_S 0 387 #define AR_XmitRate1 0x0000ff00 388 #define AR_XmitRate1_S 8 389 #define AR_XmitRate2 0x00ff0000 390 #define AR_XmitRate2_S 16 391 #define AR_XmitRate3 0xff000000 392 #define AR_XmitRate3_S 24 393 394 #define AR_PacketDur0 0x00007fff 395 #define AR_PacketDur0_S 0 396 #define AR_RTSCTSQual0 0x00008000 397 #define AR_PacketDur1 0x7fff0000 398 #define AR_PacketDur1_S 16 399 #define AR_RTSCTSQual1 0x80000000 400 401 #define AR_PacketDur2 0x00007fff 402 #define AR_PacketDur2_S 0 403 #define AR_RTSCTSQual2 0x00008000 404 #define AR_PacketDur3 0x7fff0000 405 #define AR_PacketDur3_S 16 406 #define AR_RTSCTSQual3 0x80000000 407 408 #define AR_AggrLen 0x0000ffff 409 #define AR_AggrLen_S 0 410 #define AR_TxCtlRsvd60 0x00030000 411 #define AR_PadDelim 0x03fc0000 412 #define AR_PadDelim_S 18 413 #define AR_EncrType 0x0c000000 414 #define AR_EncrType_S 26 415 #define AR_TxCtlRsvd61 0xf0000000 416 #define AR_LDPC 0x80000000 417 418 #define AR_2040_0 0x00000001 419 #define AR_GI0 0x00000002 420 #define AR_ChainSel0 0x0000001c 421 #define AR_ChainSel0_S 2 422 #define AR_2040_1 0x00000020 423 #define AR_GI1 0x00000040 424 #define AR_ChainSel1 0x00000380 425 #define AR_ChainSel1_S 7 426 #define AR_2040_2 0x00000400 427 #define AR_GI2 0x00000800 428 #define AR_ChainSel2 0x00007000 429 #define AR_ChainSel2_S 12 430 #define AR_2040_3 0x00008000 431 #define AR_GI3 0x00010000 432 #define AR_ChainSel3 0x000e0000 433 #define AR_ChainSel3_S 17 434 #define AR_RTSCTSRate 0x0ff00000 435 #define AR_RTSCTSRate_S 20 436 #define AR_STBC0 0x10000000 437 #define AR_STBC1 0x20000000 438 #define AR_STBC2 0x40000000 439 #define AR_STBC3 0x80000000 440 441 #define AR_TxRSSIAnt00 0x000000ff 442 #define AR_TxRSSIAnt00_S 0 443 #define AR_TxRSSIAnt01 0x0000ff00 444 #define AR_TxRSSIAnt01_S 8 445 #define AR_TxRSSIAnt02 0x00ff0000 446 #define AR_TxRSSIAnt02_S 16 447 #define AR_TxStatusRsvd00 0x3f000000 448 #define AR_TxBaStatus 0x40000000 449 #define AR_TxStatusRsvd01 0x80000000 450 451 /* 452 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was 453 * transmitted successfully. If clear, no ACK or BA was received to indicate 454 * successful transmission when we were expecting an ACK or BA. 455 */ 456 #define AR_FrmXmitOK 0x00000001 457 #define AR_ExcessiveRetries 0x00000002 458 #define AR_FIFOUnderrun 0x00000004 459 #define AR_Filtered 0x00000008 460 #define AR_RTSFailCnt 0x000000f0 461 #define AR_RTSFailCnt_S 4 462 #define AR_DataFailCnt 0x00000f00 463 #define AR_DataFailCnt_S 8 464 #define AR_VirtRetryCnt 0x0000f000 465 #define AR_VirtRetryCnt_S 12 466 #define AR_TxDelimUnderrun 0x00010000 467 #define AR_TxDataUnderrun 0x00020000 468 #define AR_DescCfgErr 0x00040000 469 #define AR_TxTimerExpired 0x00080000 470 #define AR_TxStatusRsvd10 0xfff00000 471 472 #define AR_SendTimestamp ds_txstatus2 473 #define AR_BaBitmapLow ds_txstatus3 474 #define AR_BaBitmapHigh ds_txstatus4 475 476 #define AR_TxRSSIAnt10 0x000000ff 477 #define AR_TxRSSIAnt10_S 0 478 #define AR_TxRSSIAnt11 0x0000ff00 479 #define AR_TxRSSIAnt11_S 8 480 #define AR_TxRSSIAnt12 0x00ff0000 481 #define AR_TxRSSIAnt12_S 16 482 #define AR_TxRSSICombined 0xff000000 483 #define AR_TxRSSICombined_S 24 484 485 #define AR_TxTid 0xf0000000 486 #define AR_TxTid_S 28 487 488 #define AR_TxEVM0 ds_txstatus5 489 #define AR_TxEVM1 ds_txstatus6 490 #define AR_TxEVM2 ds_txstatus7 491 492 #define AR_TxDone 0x00000001 493 #define AR_SeqNum 0x00001ffe 494 #define AR_SeqNum_S 1 495 #define AR_TxStatusRsvd80 0x0001e000 496 #define AR_TxOpExceeded 0x00020000 497 #define AR_TxStatusRsvd81 0x001c0000 498 #define AR_FinalTxIdx 0x00600000 499 #define AR_FinalTxIdx_S 21 500 #define AR_TxStatusRsvd82 0x01800000 501 #define AR_PowerMgmt 0x02000000 502 #define AR_TxStatusRsvd83 0xfc000000 503 504 #define AR_RxCTLRsvd00 0xffffffff 505 506 #define AR_RxCtlRsvd00 0x00001000 507 #define AR_RxIntrReq 0x00002000 508 #define AR_RxCtlRsvd01 0xffffc000 509 510 #define AR_RxRSSIAnt00 0x000000ff 511 #define AR_RxRSSIAnt00_S 0 512 #define AR_RxRSSIAnt01 0x0000ff00 513 #define AR_RxRSSIAnt01_S 8 514 #define AR_RxRSSIAnt02 0x00ff0000 515 #define AR_RxRSSIAnt02_S 16 516 #define AR_RxRate 0xff000000 517 #define AR_RxRate_S 24 518 #define AR_RxStatusRsvd00 0xff000000 519 520 #define AR_DataLen 0x00000fff 521 #define AR_RxMore 0x00001000 522 #define AR_NumDelim 0x003fc000 523 #define AR_NumDelim_S 14 524 #define AR_RxStatusRsvd10 0xff800000 525 526 #define AR_RcvTimestamp ds_rxstatus2 527 528 #define AR_GI 0x00000001 529 #define AR_2040 0x00000002 530 #define AR_Parallel40 0x00000004 531 #define AR_Parallel40_S 2 532 #define AR_RxStatusRsvd30 0x000000f8 533 #define AR_RxAntenna 0xffffff00 534 #define AR_RxAntenna_S 8 535 536 #define AR_RxRSSIAnt10 0x000000ff 537 #define AR_RxRSSIAnt10_S 0 538 #define AR_RxRSSIAnt11 0x0000ff00 539 #define AR_RxRSSIAnt11_S 8 540 #define AR_RxRSSIAnt12 0x00ff0000 541 #define AR_RxRSSIAnt12_S 16 542 #define AR_RxRSSICombined 0xff000000 543 #define AR_RxRSSICombined_S 24 544 545 #define AR_RxEVM0 ds_rxstatus4 546 #define AR_RxEVM1 ds_rxstatus5 547 #define AR_RxEVM2 ds_rxstatus6 548 549 #define AR_RxDone 0x00000001 550 #define AR_RxFrameOK 0x00000002 551 #define AR_CRCErr 0x00000004 552 #define AR_DecryptCRCErr 0x00000008 553 #define AR_PHYErr 0x00000010 554 #define AR_MichaelErr 0x00000020 555 #define AR_PreDelimCRCErr 0x00000040 556 #define AR_RxStatusRsvd70 0x00000080 557 #define AR_RxKeyIdxValid 0x00000100 558 #define AR_KeyIdx 0x0000fe00 559 #define AR_KeyIdx_S 9 560 #define AR_PHYErrCode 0x0000ff00 561 #define AR_PHYErrCode_S 8 562 #define AR_RxMoreAggr 0x00010000 563 #define AR_RxAggr 0x00020000 564 #define AR_PostDelimCRCErr 0x00040000 565 #define AR_RxStatusRsvd71 0x3ff80000 566 #define AR_DecryptBusyErr 0x40000000 567 #define AR_KeyMiss 0x80000000 568 569 enum ath9k_tx_queue { 570 ATH9K_TX_QUEUE_INACTIVE = 0, 571 ATH9K_TX_QUEUE_DATA, 572 ATH9K_TX_QUEUE_BEACON, 573 ATH9K_TX_QUEUE_CAB, 574 ATH9K_TX_QUEUE_UAPSD, 575 ATH9K_TX_QUEUE_PSPOLL 576 }; 577 578 #define ATH9K_NUM_TX_QUEUES 10 579 580 /* Used as a queue subtype instead of a WMM AC */ 581 #define ATH9K_WME_UPSD 4 582 583 enum ath9k_tx_queue_flags { 584 TXQ_FLAG_TXOKINT_ENABLE = 0x0001, 585 TXQ_FLAG_TXERRINT_ENABLE = 0x0001, 586 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, 587 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, 588 TXQ_FLAG_TXURNINT_ENABLE = 0x0008, 589 TXQ_FLAG_BACKOFF_DISABLE = 0x0010, 590 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, 591 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, 592 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, 593 }; 594 595 #define ATH9K_TXQ_USEDEFAULT ((u32) -1) 596 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 597 598 #define ATH9K_DECOMP_MASK_SIZE 128 599 #define ATH9K_READY_TIME_LO_BOUND 50 600 #define ATH9K_READY_TIME_HI_BOUND 96 601 602 enum ath9k_pkt_type { 603 ATH9K_PKT_TYPE_NORMAL = 0, 604 ATH9K_PKT_TYPE_ATIM, 605 ATH9K_PKT_TYPE_PSPOLL, 606 ATH9K_PKT_TYPE_BEACON, 607 ATH9K_PKT_TYPE_PROBE_RESP, 608 ATH9K_PKT_TYPE_CHIRP, 609 ATH9K_PKT_TYPE_GRP_POLL, 610 }; 611 612 struct ath9k_tx_queue_info { 613 u32 tqi_ver; 614 enum ath9k_tx_queue tqi_type; 615 int tqi_subtype; 616 enum ath9k_tx_queue_flags tqi_qflags; 617 u32 tqi_priority; 618 u32 tqi_aifs; 619 u32 tqi_cwmin; 620 u32 tqi_cwmax; 621 u16 tqi_shretry; 622 u16 tqi_lgretry; 623 u32 tqi_cbrPeriod; 624 u32 tqi_cbrOverflowLimit; 625 u32 tqi_burstTime; 626 u32 tqi_readyTime; 627 u32 tqi_physCompBuf; 628 u32 tqi_intFlags; 629 }; 630 631 enum ath9k_rx_filter { 632 ATH9K_RX_FILTER_UCAST = 0x00000001, 633 ATH9K_RX_FILTER_MCAST = 0x00000002, 634 ATH9K_RX_FILTER_BCAST = 0x00000004, 635 ATH9K_RX_FILTER_CONTROL = 0x00000008, 636 ATH9K_RX_FILTER_BEACON = 0x00000010, 637 ATH9K_RX_FILTER_PROM = 0x00000020, 638 ATH9K_RX_FILTER_PROBEREQ = 0x00000080, 639 ATH9K_RX_FILTER_PHYERR = 0x00000100, 640 ATH9K_RX_FILTER_MYBEACON = 0x00000200, 641 ATH9K_RX_FILTER_COMP_BAR = 0x00000400, 642 ATH9K_RX_FILTER_COMP_BA = 0x00000800, 643 ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000, 644 ATH9K_RX_FILTER_PSPOLL = 0x00004000, 645 ATH9K_RX_FILTER_PHYRADAR = 0x00002000, 646 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 647 }; 648 649 #define ATH9K_RATESERIES_RTS_CTS 0x0001 650 #define ATH9K_RATESERIES_2040 0x0002 651 #define ATH9K_RATESERIES_HALFGI 0x0004 652 #define ATH9K_RATESERIES_STBC 0x0008 653 654 struct ath9k_11n_rate_series { 655 u32 Tries; 656 u32 Rate; 657 u32 PktDuration; 658 u32 ChSel; 659 u32 RateFlags; 660 }; 661 662 enum ath9k_key_type { 663 ATH9K_KEY_TYPE_CLEAR, 664 ATH9K_KEY_TYPE_WEP, 665 ATH9K_KEY_TYPE_AES, 666 ATH9K_KEY_TYPE_TKIP, 667 }; 668 669 struct ath_hw; 670 struct ath9k_channel; 671 enum ath9k_int; 672 673 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); 674 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); 675 void ath9k_hw_txstart(struct ath_hw *ah, u32 q); 676 void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds); 677 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); 678 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); 679 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q); 680 void ath9k_hw_abort_tx_dma(struct ath_hw *ah); 681 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs); 682 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 683 const struct ath9k_tx_queue_info *qinfo); 684 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 685 struct ath9k_tx_queue_info *qinfo); 686 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 687 const struct ath9k_tx_queue_info *qinfo); 688 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q); 689 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q); 690 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 691 struct ath_rx_status *rs, u64 tsf); 692 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, 693 u32 size, u32 flags); 694 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); 695 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); 696 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning); 697 void ath9k_hw_abortpcurecv(struct ath_hw *ah); 698 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset); 699 int ath9k_hw_beaconq_setup(struct ath_hw *ah); 700 701 /* Interrupt Handling */ 702 bool ath9k_hw_intrpend(struct ath_hw *ah); 703 void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints); 704 void ath9k_hw_enable_interrupts(struct ath_hw *ah); 705 void ath9k_hw_disable_interrupts(struct ath_hw *ah); 706 707 void ar9002_hw_attach_mac_ops(struct ath_hw *ah); 708 709 #endif /* MAC_H */ 710