1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *  i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
4  *
5  *  Copyright (C) 2011 Weinmann Medical GmbH
6  *  Author: Nikolaus Voss <n.voss@weinmann.de>
7  *
8  *  Evolved from original work by:
9  *  Copyright (C) 2004 Rick Bronson
10  *  Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
11  *
12  *  Borrowed heavily from original work by:
13  *  Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
14  */
15 
16 #include <linux/clk.h>
17 #include <linux/completion.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 
23 #define AT91_I2C_TIMEOUT	msecs_to_jiffies(100)	/* transfer timeout */
24 #define AT91_I2C_DMA_THRESHOLD	8			/* enable DMA if transfer size is bigger than this threshold */
25 #define AUTOSUSPEND_TIMEOUT		2000
26 #define AT91_I2C_MAX_ALT_CMD_DATA_SIZE	256
27 
28 /* AT91 TWI register definitions */
29 #define	AT91_TWI_CR		0x0000	/* Control Register */
30 #define	AT91_TWI_START		BIT(0)	/* Send a Start Condition */
31 #define	AT91_TWI_STOP		BIT(1)	/* Send a Stop Condition */
32 #define	AT91_TWI_MSEN		BIT(2)	/* Master Transfer Enable */
33 #define	AT91_TWI_MSDIS		BIT(3)	/* Master Transfer Disable */
34 #define	AT91_TWI_SVEN		BIT(4)	/* Slave Transfer Enable */
35 #define	AT91_TWI_SVDIS		BIT(5)	/* Slave Transfer Disable */
36 #define	AT91_TWI_QUICK		BIT(6)	/* SMBus quick command */
37 #define	AT91_TWI_SWRST		BIT(7)	/* Software Reset */
38 #define	AT91_TWI_CLEAR		BIT(15) /* Bus clear command */
39 #define	AT91_TWI_ACMEN		BIT(16) /* Alternative Command Mode Enable */
40 #define	AT91_TWI_ACMDIS		BIT(17) /* Alternative Command Mode Disable */
41 #define	AT91_TWI_THRCLR		BIT(24) /* Transmit Holding Register Clear */
42 #define	AT91_TWI_RHRCLR		BIT(25) /* Receive Holding Register Clear */
43 #define	AT91_TWI_LOCKCLR	BIT(26) /* Lock Clear */
44 #define	AT91_TWI_FIFOEN		BIT(28) /* FIFO Enable */
45 #define	AT91_TWI_FIFODIS	BIT(29) /* FIFO Disable */
46 
47 #define	AT91_TWI_MMR		0x0004	/* Master Mode Register */
48 #define	AT91_TWI_IADRSZ_1	0x0100	/* Internal Device Address Size */
49 #define	AT91_TWI_MREAD		BIT(12)	/* Master Read Direction */
50 
51 #define	AT91_TWI_SMR		0x0008	/* Slave Mode Register */
52 #define	AT91_TWI_SMR_SADR_MAX	0x007f
53 #define	AT91_TWI_SMR_SADR(x)	(((x) & AT91_TWI_SMR_SADR_MAX) << 16)
54 
55 #define	AT91_TWI_IADR		0x000c	/* Internal Address Register */
56 
57 #define	AT91_TWI_CWGR		0x0010	/* Clock Waveform Generator Reg */
58 #define	AT91_TWI_CWGR_HOLD_MAX	0x1f
59 #define	AT91_TWI_CWGR_HOLD(x)	(((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
60 
61 #define	AT91_TWI_SR		0x0020	/* Status Register */
62 #define	AT91_TWI_TXCOMP		BIT(0)	/* Transmission Complete */
63 #define	AT91_TWI_RXRDY		BIT(1)	/* Receive Holding Register Ready */
64 #define	AT91_TWI_TXRDY		BIT(2)	/* Transmit Holding Register Ready */
65 #define	AT91_TWI_SVREAD		BIT(3)	/* Slave Read */
66 #define	AT91_TWI_SVACC		BIT(4)	/* Slave Access */
67 #define	AT91_TWI_OVRE		BIT(6)	/* Overrun Error */
68 #define	AT91_TWI_UNRE		BIT(7)	/* Underrun Error */
69 #define	AT91_TWI_NACK		BIT(8)	/* Not Acknowledged */
70 #define	AT91_TWI_EOSACC		BIT(11)	/* End Of Slave Access */
71 #define	AT91_TWI_LOCK		BIT(23) /* TWI Lock due to Frame Errors */
72 #define	AT91_TWI_SCL		BIT(24) /* TWI SCL status */
73 #define	AT91_TWI_SDA		BIT(25) /* TWI SDA status */
74 
75 #define	AT91_TWI_INT_MASK \
76 	(AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK \
77 	| AT91_TWI_SVACC | AT91_TWI_EOSACC)
78 
79 #define	AT91_TWI_IER		0x0024	/* Interrupt Enable Register */
80 #define	AT91_TWI_IDR		0x0028	/* Interrupt Disable Register */
81 #define	AT91_TWI_IMR		0x002c	/* Interrupt Mask Register */
82 #define	AT91_TWI_RHR		0x0030	/* Receive Holding Register */
83 #define	AT91_TWI_THR		0x0034	/* Transmit Holding Register */
84 
85 #define	AT91_TWI_ACR		0x0040	/* Alternative Command Register */
86 #define	AT91_TWI_ACR_DATAL_MASK	GENMASK(15, 0)
87 #define	AT91_TWI_ACR_DATAL(len)	((len) & AT91_TWI_ACR_DATAL_MASK)
88 #define	AT91_TWI_ACR_DIR	BIT(8)
89 
90 #define AT91_TWI_FILTR		0x0044
91 #define AT91_TWI_FILTR_FILT	BIT(0)
92 #define AT91_TWI_FILTR_PADFEN	BIT(1)
93 #define AT91_TWI_FILTR_THRES(v)		((v) << 8)
94 #define AT91_TWI_FILTR_THRES_MAX	7
95 #define AT91_TWI_FILTR_THRES_MASK	GENMASK(10, 8)
96 
97 #define	AT91_TWI_FMR		0x0050	/* FIFO Mode Register */
98 #define	AT91_TWI_FMR_TXRDYM(mode)	(((mode) & 0x3) << 0)
99 #define	AT91_TWI_FMR_TXRDYM_MASK	(0x3 << 0)
100 #define	AT91_TWI_FMR_RXRDYM(mode)	(((mode) & 0x3) << 4)
101 #define	AT91_TWI_FMR_RXRDYM_MASK	(0x3 << 4)
102 #define	AT91_TWI_ONE_DATA	0x0
103 #define	AT91_TWI_TWO_DATA	0x1
104 #define	AT91_TWI_FOUR_DATA	0x2
105 
106 #define	AT91_TWI_FLR		0x0054	/* FIFO Level Register */
107 
108 #define	AT91_TWI_FSR		0x0060	/* FIFO Status Register */
109 #define	AT91_TWI_FIER		0x0064	/* FIFO Interrupt Enable Register */
110 #define	AT91_TWI_FIDR		0x0068	/* FIFO Interrupt Disable Register */
111 #define	AT91_TWI_FIMR		0x006c	/* FIFO Interrupt Mask Register */
112 
113 #define	AT91_TWI_VER		0x00fc	/* Version Register */
114 
115 struct at91_twi_pdata {
116 	unsigned clk_max_div;
117 	unsigned clk_offset;
118 	bool has_unre_flag;
119 	bool has_alt_cmd;
120 	bool has_hold_field;
121 	bool has_dig_filtr;
122 	bool has_adv_dig_filtr;
123 	bool has_ana_filtr;
124 	bool has_clear_cmd;
125 };
126 
127 struct at91_twi_dma {
128 	struct dma_chan *chan_rx;
129 	struct dma_chan *chan_tx;
130 	struct scatterlist sg[2];
131 	struct dma_async_tx_descriptor *data_desc;
132 	enum dma_data_direction direction;
133 	bool buf_mapped;
134 	bool xfer_in_progress;
135 };
136 
137 struct at91_twi_dev {
138 	struct device *dev;
139 	void __iomem *base;
140 	struct completion cmd_complete;
141 	struct clk *clk;
142 	u8 *buf;
143 	size_t buf_len;
144 	struct i2c_msg *msg;
145 	int irq;
146 	unsigned imr;
147 	unsigned transfer_status;
148 	struct i2c_adapter adapter;
149 	unsigned twi_cwgr_reg;
150 	struct at91_twi_pdata *pdata;
151 	bool use_dma;
152 	bool use_alt_cmd;
153 	bool recv_len_abort;
154 	u32 fifo_size;
155 	struct at91_twi_dma dma;
156 	bool slave_detected;
157 	struct i2c_bus_recovery_info rinfo;
158 #ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
159 	unsigned smr;
160 	struct i2c_client *slave;
161 #endif
162 	bool enable_dig_filt;
163 	bool enable_ana_filt;
164 	u32 filter_width;
165 };
166 
167 unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg);
168 void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val);
169 void at91_disable_twi_interrupts(struct at91_twi_dev *dev);
170 void at91_twi_irq_save(struct at91_twi_dev *dev);
171 void at91_twi_irq_restore(struct at91_twi_dev *dev);
172 void at91_init_twi_bus(struct at91_twi_dev *dev);
173 
174 void at91_init_twi_bus_master(struct at91_twi_dev *dev);
175 int at91_twi_probe_master(struct platform_device *pdev, u32 phy_addr,
176 			  struct at91_twi_dev *dev);
177 
178 #ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
179 void at91_init_twi_bus_slave(struct at91_twi_dev *dev);
180 int at91_twi_probe_slave(struct platform_device *pdev, u32 phy_addr,
181 			 struct at91_twi_dev *dev);
182 
183 #else
at91_init_twi_bus_slave(struct at91_twi_dev * dev)184 static inline void at91_init_twi_bus_slave(struct at91_twi_dev *dev) {}
at91_twi_probe_slave(struct platform_device * pdev,u32 phy_addr,struct at91_twi_dev * dev)185 static inline int at91_twi_probe_slave(struct platform_device *pdev,
186 				       u32 phy_addr, struct at91_twi_dev *dev)
187 {
188 	return -EINVAL;
189 }
190 
191 #endif
192