1 /* 2 * linux/include/asm-arm/arch-sa1100/assabet.h 3 * 4 * Created 2000/06/05 by Nicolas Pitre <nico@cam.org> 5 * 6 * This file contains the hardware specific definitions for Assabet 7 * Only include this file from SA1100-specific files. 8 * 9 * 2000/05/23 John Dorsey <john+@cs.cmu.edu> 10 * Definitions for Neponset added. 11 */ 12 #ifndef __ASM_ARCH_ASSABET_H 13 #define __ASM_ARCH_ASSABET_H 14 15 /* System Configuration Register flags */ 16 17 #define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */ 18 #define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */ 19 #define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */ 20 #define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */ 21 #define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */ 22 #define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */ 23 24 #define ASSABET_SCR_INIT -1 25 26 27 /* Board Control Register */ 28 29 #define ASSABET_BCR_BASE 0xf1000000 30 #define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE)) 31 32 #define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */ 33 #define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */ 34 #define ASSABET_BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ 35 #define ASSABET_BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */ 36 #define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */ 37 #define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */ 38 #define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */ 39 #define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */ 40 #define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */ 41 #define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */ 42 #define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */ 43 #define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */ 44 #define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */ 45 #define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */ 46 #define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */ 47 #define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */ 48 #define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */ 49 #define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */ 50 #define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */ 51 #define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */ 52 #define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */ 53 #define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */ 54 #define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */ 55 #define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */ 56 #define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */ 57 58 extern unsigned long SCR_value; 59 extern unsigned long BCR_value; 60 61 #ifdef CONFIG_SA1100_ASSABET 62 extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); 63 #else 64 #define ASSABET_BCR_frob(m,s) do { } while (0) 65 #endif 66 67 #define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x)) 68 #define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0) 69 70 #define ASSABET_BSR_BASE 0xf1000000 71 #define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE)) 72 73 #define ASSABET_BSR_RS232_VALID (1 << 24) 74 #define ASSABET_BSR_COM_DCD (1 << 25) 75 #define ASSABET_BSR_COM_CTS (1 << 26) 76 #define ASSABET_BSR_COM_DSR (1 << 27) 77 #define ASSABET_BSR_RAD_CTS (1 << 28) 78 #define ASSABET_BSR_RAD_DSR (1 << 29) 79 #define ASSABET_BSR_RAD_DCD (1 << 30) 80 #define ASSABET_BSR_RAD_RI (1 << 31) 81 82 83 /* GPIOs for which the generic definition doesn't say much */ 84 #define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ 85 #define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ 86 #define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ 87 #define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */ 88 #define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */ 89 #define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */ 90 #define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ 91 #define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */ 92 #define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ 93 #define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ 94 95 #define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21 96 #define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22 97 #define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24 98 #define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25 99 100 101 /* 102 * Neponset definitions: 103 */ 104 105 #define NEPONSET_SA1111_BASE (0x40000000) 106 107 #define NEPONSET_CPLD_BASE (0x10000000) 108 #define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000) 109 #define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE) 110 111 #define _IRR 0x10000024 /* Interrupt Reason Register */ 112 #define _AUD_CTL 0x100000c0 /* Audio controls (RW) */ 113 #define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */ 114 #define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */ 115 #define _NCR_0 0x100000a0 /* Control Register (RW) */ 116 #define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */ 117 #define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */ 118 #define _SWPK 0x10000020 /* Switch pack (RO) */ 119 #define _WHOAMI 0x10000000 /* System ID Register (RO) */ 120 121 #define _LEDS 0x10000010 /* LEDs [31:0] (WO) */ 122 123 #define IRR (*((volatile u_char *) Nep_p2v(_IRR))) 124 #define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL))) 125 #define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0))) 126 #define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1))) 127 #define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0))) 128 #define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT))) 129 #define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN))) 130 #define SWPK (*((volatile u_char *) Nep_p2v(_SWPK))) 131 #define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI))) 132 133 #define LEDS (*((volatile Word *) Nep_p2v(_LEDS))) 134 135 #define IRR_ETHERNET (1<<0) 136 #define IRR_USAR (1<<1) 137 #define IRR_SA1111 (1<<2) 138 139 #define AUD_SEL_1341 (1<<0) 140 #define AUD_MUTE_1341 (1<<1) 141 142 #define MDM_CTL0_RTS1 (1 << 0) 143 #define MDM_CTL0_DTR1 (1 << 1) 144 #define MDM_CTL0_RTS2 (1 << 2) 145 #define MDM_CTL0_DTR2 (1 << 3) 146 147 #define MDM_CTL1_CTS1 (1 << 0) 148 #define MDM_CTL1_DSR1 (1 << 1) 149 #define MDM_CTL1_DCD1 (1 << 2) 150 #define MDM_CTL1_CTS2 (1 << 3) 151 #define MDM_CTL1_DSR2 (1 << 4) 152 #define MDM_CTL1_DCD2 (1 << 5) 153 154 #define NCR_GP01_OFF (1<<0) 155 #define NCR_TP_PWR_EN (1<<1) 156 #define NCR_MS_PWR_EN (1<<2) 157 #define NCR_ENET_OSC_EN (1<<3) 158 #define NCR_SPI_KB_WK_UP (1<<4) 159 #define NCR_A0VPP (1<<5) 160 #define NCR_A1VPP (1<<6) 161 162 #ifdef CONFIG_ASSABET_NEPONSET 163 #define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0) 164 #else 165 #define machine_has_neponset() (0) 166 #endif 167 168 #endif 169