1 /*
2  * Copyright (c) 2010-2011 Atheros Communications, Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef AR9003_PHY_H
18 #define AR9003_PHY_H
19 
20 /*
21  * Channel Register Map
22  */
23 #define AR_CHAN_BASE	0x9800
24 
25 #define AR_PHY_TIMING1      (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2      (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3      (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4      (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5      (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6      (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11     (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG     (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0    (AR_CHAN_BASE + 0xdc)
34 #define AR_PHY_TX_IQCAL_CONTROL_3  (AR_CHAN_BASE + 0xb0)
35 
36 #define AR_PHY_TIMING11_SPUR_FREQ_SD    0x3FF00000
37 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S  20
38 
39 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
40 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
41 
42 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
43 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
44 
45 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
46 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
47 
48 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT         0x4000000
49 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S       26
50 
51 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM                         0x20000     /* bins move with freq offset */
52 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S                       17
53 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH            0x000000FF
54 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S          0
55 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI                        0x00000100
56 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S                      8
57 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL                          0x03FC0000
58 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S			18
59 
60 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN   0x20000000
61 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S         29
62 
63 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN   0x80000000
64 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S         31
65 
66 #define AR_PHY_FIND_SIG_LOW  (AR_CHAN_BASE + 0x20)
67 
68 #define AR_PHY_SFCORR           (AR_CHAN_BASE + 0x24)
69 #define AR_PHY_SFCORR_LOW       (AR_CHAN_BASE + 0x28)
70 #define AR_PHY_SFCORR_EXT       (AR_CHAN_BASE + 0x2c)
71 
72 #define AR_PHY_EXT_CCA              (AR_CHAN_BASE + 0x30)
73 #define AR_PHY_RADAR_0              (AR_CHAN_BASE + 0x34)
74 #define AR_PHY_RADAR_1              (AR_CHAN_BASE + 0x38)
75 #define AR_PHY_RADAR_EXT            (AR_CHAN_BASE + 0x3c)
76 #define AR_PHY_MULTICHAIN_CTRL      (AR_CHAN_BASE + 0x80)
77 #define AR_PHY_PERCHAIN_CSD         (AR_CHAN_BASE + 0x84)
78 
79 #define AR_PHY_TX_PHASE_RAMP_0      (AR_CHAN_BASE + 0xd0)
80 #define AR_PHY_ADC_GAIN_DC_CORR_0   (AR_CHAN_BASE + 0xd4)
81 #define AR_PHY_IQ_ADC_MEAS_0_B0     (AR_CHAN_BASE + 0xc0)
82 #define AR_PHY_IQ_ADC_MEAS_1_B0     (AR_CHAN_BASE + 0xc4)
83 #define AR_PHY_IQ_ADC_MEAS_2_B0     (AR_CHAN_BASE + 0xc8)
84 #define AR_PHY_IQ_ADC_MEAS_3_B0     (AR_CHAN_BASE + 0xcc)
85 
86 /* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
87 #define AR_PHY_TX_PHASE_RAMP_0_9300_10      (AR_CHAN_BASE + 0xd0 - 0x10)
88 #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10   (AR_CHAN_BASE + 0xd4 - 0x10)
89 #define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10     (AR_CHAN_BASE + 0xc0 + 0x8)
90 #define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10     (AR_CHAN_BASE + 0xc4 + 0x8)
91 #define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10     (AR_CHAN_BASE + 0xc8 + 0x8)
92 #define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10     (AR_CHAN_BASE + 0xcc + 0x8)
93 
94 #define AR_PHY_TX_CRC               (AR_CHAN_BASE + 0xa0)
95 #define AR_PHY_TST_DAC_CONST        (AR_CHAN_BASE + 0xa4)
96 #define AR_PHY_SPUR_REPORT_0        (AR_CHAN_BASE + 0xa8)
97 #define AR_PHY_CHAN_INFO_TAB_0      (AR_CHAN_BASE + 0x300)
98 
99 /*
100  * Channel Field Definitions
101  */
102 #define AR_PHY_TIMING2_USE_FORCE_PPM    0x00001000
103 #define AR_PHY_TIMING2_FORCE_PPM_VAL    0x00000fff
104 #define AR_PHY_TIMING3_DSC_MAN      0xFFFE0000
105 #define AR_PHY_TIMING3_DSC_MAN_S    17
106 #define AR_PHY_TIMING3_DSC_EXP      0x0001E000
107 #define AR_PHY_TIMING3_DSC_EXP_S    13
108 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
109 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S   12
110 #define AR_PHY_TIMING4_DO_CAL    0x10000
111 
112 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK        0x10000000
113 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S      28
114 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK         0x20000000
115 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S       29
116 
117 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
118 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
119 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
120 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
121 
122 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
123 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
124 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW  0x00000001
125 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW    0x00003F00
126 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S  8
127 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW      0x001FC000
128 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S    14
129 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW      0x0FE00000
130 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S    21
131 #define AR_PHY_SFCORR_M2COUNT_THR    0x0000001F
132 #define AR_PHY_SFCORR_M2COUNT_THR_S  0
133 #define AR_PHY_SFCORR_M1_THRESH      0x00FE0000
134 #define AR_PHY_SFCORR_M1_THRESH_S    17
135 #define AR_PHY_SFCORR_M2_THRESH      0x7F000000
136 #define AR_PHY_SFCORR_M2_THRESH_S    24
137 #define AR_PHY_SFCORR_EXT_M1_THRESH       0x0000007F
138 #define AR_PHY_SFCORR_EXT_M1_THRESH_S     0
139 #define AR_PHY_SFCORR_EXT_M2_THRESH       0x00003F80
140 #define AR_PHY_SFCORR_EXT_M2_THRESH_S     7
141 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW   0x001FC000
142 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
143 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW   0x0FE00000
144 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
145 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
146 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
147 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S   28
148 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
149 #define AR_PHY_EXT_CCA_THRESH62_S       16
150 #define AR_PHY_EXT_MINCCA_PWR   0x01FF0000
151 #define AR_PHY_EXT_MINCCA_PWR_S 16
152 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L
153 #define AR_PHY_EXT_CYCPWR_THR1_S 9
154 #define AR_PHY_TIMING5_CYCPWR_THR1  0x000000FE
155 #define AR_PHY_TIMING5_CYCPWR_THR1_S    1
156 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE  0x00000001
157 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S    0
158 #define AR_PHY_TIMING5_CYCPWR_THR1A  0x007F0000
159 #define AR_PHY_TIMING5_CYCPWR_THR1A_S    16
160 #define AR_PHY_TIMING5_RSSI_THR1A     (0x7F << 16)
161 #define AR_PHY_TIMING5_RSSI_THR1A_S   16
162 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
163 #define AR_PHY_RADAR_0_ENA  0x00000001
164 #define AR_PHY_RADAR_0_FFT_ENA  0x80000000
165 #define AR_PHY_RADAR_0_INBAND   0x0000003e
166 #define AR_PHY_RADAR_0_INBAND_S 1
167 #define AR_PHY_RADAR_0_PRSSI    0x00000FC0
168 #define AR_PHY_RADAR_0_PRSSI_S  6
169 #define AR_PHY_RADAR_0_HEIGHT   0x0003F000
170 #define AR_PHY_RADAR_0_HEIGHT_S 12
171 #define AR_PHY_RADAR_0_RRSSI    0x00FC0000
172 #define AR_PHY_RADAR_0_RRSSI_S  18
173 #define AR_PHY_RADAR_0_FIRPWR   0x7F000000
174 #define AR_PHY_RADAR_0_FIRPWR_S 24
175 #define AR_PHY_RADAR_1_RELPWR_ENA       0x00800000
176 #define AR_PHY_RADAR_1_USE_FIR128       0x00400000
177 #define AR_PHY_RADAR_1_RELPWR_THRESH    0x003F0000
178 #define AR_PHY_RADAR_1_RELPWR_THRESH_S  16
179 #define AR_PHY_RADAR_1_BLOCK_CHECK      0x00008000
180 #define AR_PHY_RADAR_1_MAX_RRSSI        0x00004000
181 #define AR_PHY_RADAR_1_RELSTEP_CHECK    0x00002000
182 #define AR_PHY_RADAR_1_RELSTEP_THRESH   0x00001F00
183 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
184 #define AR_PHY_RADAR_1_MAXLEN           0x000000FF
185 #define AR_PHY_RADAR_1_MAXLEN_S         0
186 #define AR_PHY_RADAR_EXT_ENA            0x00004000
187 #define AR_PHY_RADAR_DC_PWR_THRESH      0x007f8000
188 #define AR_PHY_RADAR_DC_PWR_THRESH_S    15
189 #define AR_PHY_RADAR_LB_DC_CAP          0x7f800000
190 #define AR_PHY_RADAR_LB_DC_CAP_S        23
191 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
192 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S   6
193 #define AR_PHY_FIND_SIG_LOW_FIRPWR      (0x7f << 12)
194 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S    12
195 #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
196 #define AR_PHY_FIND_SIG_LOW_RELSTEP     0x1f
197 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S   0
198 #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
199 #define AR_PHY_CHAN_INFO_TAB_S2_READ    0x00000008
200 #define AR_PHY_CHAN_INFO_TAB_S2_READ_S           3
201 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
202 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S   0
203 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
204 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S   7
205 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE   0x00004000
206 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF   0x003f8000
207 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
208 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF   0x1fc00000
209 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
210 
211 /*
212  * MRC Register Map
213  */
214 #define AR_MRC_BASE	0x9c00
215 
216 #define AR_PHY_TIMING_3A       (AR_MRC_BASE + 0x0)
217 #define AR_PHY_LDPC_CNTL1      (AR_MRC_BASE + 0x4)
218 #define AR_PHY_LDPC_CNTL2      (AR_MRC_BASE + 0x8)
219 #define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc)
220 #define AR_PHY_CHAN_SPUR_MASK  (AR_MRC_BASE + 0x10)
221 #define AR_PHY_SGI_DELTA       (AR_MRC_BASE + 0x14)
222 #define AR_PHY_ML_CNTL_1       (AR_MRC_BASE + 0x18)
223 #define AR_PHY_ML_CNTL_2       (AR_MRC_BASE + 0x1c)
224 #define AR_PHY_TST_ADC         (AR_MRC_BASE + 0x20)
225 
226 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A              0x00000FE0
227 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S    5
228 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A                  0x1F
229 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S                0
230 
231 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A        0x00000FE0
232 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S      5
233 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A            0x1F
234 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S		0
235 
236 /*
237  * MRC Feild Definitions
238  */
239 #define AR_PHY_SGI_DSC_MAN   0x0007FFF0
240 #define AR_PHY_SGI_DSC_MAN_S 4
241 #define AR_PHY_SGI_DSC_EXP   0x0000000F
242 #define AR_PHY_SGI_DSC_EXP_S 0
243 /*
244  * BBB Register Map
245  */
246 #define AR_BBB_BASE	0x9d00
247 
248 /*
249  * AGC Register Map
250  */
251 #define AR_AGC_BASE	0x9e00
252 
253 #define AR_PHY_SETTLING         (AR_AGC_BASE + 0x0)
254 #define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4)
255 #define AR_PHY_GAINS_MINOFF0    (AR_AGC_BASE + 0x8)
256 #define AR_PHY_DESIRED_SZ       (AR_AGC_BASE + 0xc)
257 #define AR_PHY_FIND_SIG         (AR_AGC_BASE + 0x10)
258 #define AR_PHY_AGC              (AR_AGC_BASE + 0x14)
259 #define AR_PHY_EXT_ATTEN_CTL_0  (AR_AGC_BASE + 0x18)
260 #define AR_PHY_CCA_0            (AR_AGC_BASE + 0x1c)
261 #define AR_PHY_EXT_CCA0         (AR_AGC_BASE + 0x20)
262 #define AR_PHY_RESTART          (AR_AGC_BASE + 0x24)
263 
264 /*
265  * Antenna Diversity  settings
266  */
267 #define AR_PHY_MC_GAIN_CTRL     (AR_AGC_BASE + 0x28)
268 #define AR_ANT_DIV_CTRL_ALL	0x7e000000
269 #define AR_ANT_DIV_CTRL_ALL_S	25
270 #define AR_ANT_DIV_ENABLE	0x1000000
271 #define AR_ANT_DIV_ENABLE_S	24
272 
273 
274 #define AR_PHY_9485_ANT_FAST_DIV_BIAS			0x00007e00
275 #define AR_PHY_9485_ANT_FAST_DIV_BIAS_S                  9
276 #define AR_PHY_9485_ANT_DIV_LNADIV			0x01000000
277 #define AR_PHY_9485_ANT_DIV_LNADIV_S			24
278 #define AR_PHY_9485_ANT_DIV_ALT_LNACONF			0x06000000
279 #define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S		25
280 #define AR_PHY_9485_ANT_DIV_MAIN_LNACONF		0x18000000
281 #define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S		27
282 #define AR_PHY_9485_ANT_DIV_ALT_GAINTB			0x20000000
283 #define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S		29
284 #define AR_PHY_9485_ANT_DIV_MAIN_GAINTB			0x40000000
285 #define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S		30
286 
287 #define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2		0x0
288 #define AR_PHY_9485_ANT_DIV_LNA2			0x1
289 #define AR_PHY_9485_ANT_DIV_LNA1			0x2
290 #define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2		0x3
291 
292 #define AR_PHY_EXTCHN_PWRTHR1   (AR_AGC_BASE + 0x2c)
293 #define AR_PHY_EXT_CHN_WIN      (AR_AGC_BASE + 0x30)
294 #define AR_PHY_20_40_DET_THR    (AR_AGC_BASE + 0x34)
295 #define AR_PHY_RIFS_SRCH        (AR_AGC_BASE + 0x38)
296 #define AR_PHY_PEAK_DET_CTRL_1  (AR_AGC_BASE + 0x3c)
297 #define AR_PHY_PEAK_DET_CTRL_2  (AR_AGC_BASE + 0x40)
298 #define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44)
299 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
300 #define AR_PHY_RSSI_0           (AR_AGC_BASE + 0x180)
301 #define AR_PHY_SPUR_CCK_REP0    (AR_AGC_BASE + 0x184)
302 
303 #define AR_PHY_CCK_DETECT       (AR_AGC_BASE + 0x1c0)
304 #define AR_FAST_DIV_ENABLE	0x2000
305 #define AR_FAST_DIV_ENABLE_S	13
306 
307 #define AR_PHY_DAG_CTRLCCK      (AR_AGC_BASE + 0x1c4)
308 #define AR_PHY_IQCORR_CTRL_CCK  (AR_AGC_BASE + 0x1c8)
309 
310 #define AR_PHY_CCK_SPUR_MIT     (AR_AGC_BASE + 0x1cc)
311 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR                           0x000001fe
312 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S                                  1
313 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE                        0x60000000
314 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S                              29
315 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT                        0x00000001
316 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S                               0
317 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ                           0x1ffffe00
318 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S                                  9
319 
320 #define AR_PHY_MRC_CCK_CTRL         (AR_AGC_BASE + 0x1d0)
321 #define AR_PHY_MRC_CCK_ENABLE       0x00000001
322 #define AR_PHY_MRC_CCK_ENABLE_S              0
323 #define AR_PHY_MRC_CCK_MUX_REG      0x00000002
324 #define AR_PHY_MRC_CCK_MUX_REG_S             1
325 
326 #define AR_PHY_RX_OCGAIN        (AR_AGC_BASE + 0x200)
327 
328 #define AR_PHY_CCA_NOM_VAL_9300_2GHZ          -110
329 #define AR_PHY_CCA_NOM_VAL_9300_5GHZ          -115
330 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ     -125
331 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ     -125
332 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ     -95
333 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ     -100
334 
335 #define AR_PHY_CCA_NOM_VAL_9462_2GHZ          -127
336 #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ     -127
337 #define AR_PHY_CCA_NOM_VAL_9462_5GHZ          -127
338 #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ     -127
339 
340 #define AR_PHY_CCA_NOM_VAL_9330_2GHZ          -118
341 
342 #define AR9300_EXT_LNA_CTL_GPIO_AR9485 9
343 
344 /*
345  * AGC Field Definitions
346  */
347 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN    0x00FC0000
348 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S  18
349 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN     0x00003C00
350 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S   10
351 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN      0x0000001F
352 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S    0
353 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN     0x003E0000
354 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S   17
355 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN     0x0001F000
356 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S   12
357 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB         0x00000FC0
358 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S       6
359 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB         0x0000003F
360 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S       0
361 #define AR_PHY_RXGAIN_TXRX_ATTEN    0x0003F000
362 #define AR_PHY_RXGAIN_TXRX_ATTEN_S  12
363 #define AR_PHY_RXGAIN_TXRX_RF_MAX   0x007C0000
364 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
365 #define AR9280_PHY_RXGAIN_TXRX_ATTEN    0x00003F80
366 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S  7
367 #define AR9280_PHY_RXGAIN_TXRX_MARGIN   0x001FC000
368 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
369 #define AR_PHY_SETTLING_SWITCH  0x00003F80
370 #define AR_PHY_SETTLING_SWITCH_S    7
371 #define AR_PHY_DESIRED_SZ_ADC       0x000000FF
372 #define AR_PHY_DESIRED_SZ_ADC_S     0
373 #define AR_PHY_DESIRED_SZ_PGA       0x0000FF00
374 #define AR_PHY_DESIRED_SZ_PGA_S     8
375 #define AR_PHY_DESIRED_SZ_TOT_DES   0x0FF00000
376 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20
377 #define AR_PHY_MINCCA_PWR       0x1FF00000
378 #define AR_PHY_MINCCA_PWR_S     20
379 #define AR_PHY_CCA_THRESH62     0x0007F000
380 #define AR_PHY_CCA_THRESH62_S   12
381 #define AR9280_PHY_MINCCA_PWR       0x1FF00000
382 #define AR9280_PHY_MINCCA_PWR_S     20
383 #define AR9280_PHY_CCA_THRESH62     0x000FF000
384 #define AR9280_PHY_CCA_THRESH62_S   12
385 #define AR_PHY_EXT_CCA0_THRESH62    0x000000FF
386 #define AR_PHY_EXT_CCA0_THRESH62_S  0
387 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK          0x0000003F
388 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S        0
389 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME           0x00001FC0
390 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S         6
391 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV    0x2000
392 
393 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR  0x00000200
394 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S  9
395 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
396 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S   10
397 
398 #define AR_PHY_RIFS_INIT_DELAY         0x3ff0000
399 #define AR_PHY_AGC_QUICK_DROP       0x03c00000
400 #define AR_PHY_AGC_QUICK_DROP_S     22
401 #define AR_PHY_AGC_COARSE_LOW       0x00007F80
402 #define AR_PHY_AGC_COARSE_LOW_S     7
403 #define AR_PHY_AGC_COARSE_HIGH      0x003F8000
404 #define AR_PHY_AGC_COARSE_HIGH_S    15
405 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
406 #define AR_PHY_AGC_COARSE_PWR_CONST_S   0
407 #define AR_PHY_FIND_SIG_FIRSTEP  0x0003F000
408 #define AR_PHY_FIND_SIG_FIRSTEP_S        12
409 #define AR_PHY_FIND_SIG_FIRPWR   0x03FC0000
410 #define AR_PHY_FIND_SIG_FIRPWR_S         18
411 #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT  25
412 #define AR_PHY_FIND_SIG_RELPWR   (0x1f << 6)
413 #define AR_PHY_FIND_SIG_RELPWR_S          6
414 #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT  11
415 #define AR_PHY_FIND_SIG_RELSTEP        0x1f
416 #define AR_PHY_FIND_SIG_RELSTEP_S         0
417 #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT  5
418 #define AR_PHY_RESTART_DIV_GC   0x001C0000
419 #define AR_PHY_RESTART_DIV_GC_S 18
420 #define AR_PHY_RESTART_ENA      0x01
421 #define AR_PHY_DC_RESTART_DIS   0x40000000
422 
423 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON       0xFF000000
424 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S     24
425 #define AR_PHY_TPC_OLPC_GAIN_DELTA              0x00FF0000
426 #define AR_PHY_TPC_OLPC_GAIN_DELTA_S            16
427 
428 #define AR_PHY_TPC_6_ERROR_EST_MODE             0x03000000
429 #define AR_PHY_TPC_6_ERROR_EST_MODE_S           24
430 
431 /*
432  * SM Register Map
433  */
434 #define AR_SM_BASE	0xa200
435 
436 #define AR_PHY_D2_CHIP_ID        (AR_SM_BASE + 0x0)
437 #define AR_PHY_GEN_CTRL          (AR_SM_BASE + 0x4)
438 #define AR_PHY_MODE              (AR_SM_BASE + 0x8)
439 #define AR_PHY_ACTIVE            (AR_SM_BASE + 0xc)
440 #define AR_PHY_SPUR_MASK_A       (AR_SM_BASE + 0x20)
441 #define AR_PHY_SPUR_MASK_B       (AR_SM_BASE + 0x24)
442 #define AR_PHY_SPECTRAL_SCAN     (AR_SM_BASE + 0x28)
443 #define AR_PHY_RADAR_BW_FILTER   (AR_SM_BASE + 0x2c)
444 #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)
445 #define AR_PHY_MAX_RX_LEN        (AR_SM_BASE + 0x34)
446 #define AR_PHY_FRAME_CTL         (AR_SM_BASE + 0x38)
447 #define AR_PHY_RFBUS_REQ         (AR_SM_BASE + 0x3c)
448 #define AR_PHY_RFBUS_GRANT       (AR_SM_BASE + 0x40)
449 #define AR_PHY_RIFS              (AR_SM_BASE + 0x44)
450 #define AR_PHY_RX_CLR_DELAY      (AR_SM_BASE + 0x50)
451 #define AR_PHY_RX_DELAY          (AR_SM_BASE + 0x54)
452 
453 #define AR_PHY_XPA_TIMING_CTL    (AR_SM_BASE + 0x64)
454 #define AR_PHY_MISC_PA_CTL       (AR_SM_BASE + 0x80)
455 #define AR_PHY_SWITCH_CHAIN_0    (AR_SM_BASE + 0x84)
456 #define AR_PHY_SWITCH_COM        (AR_SM_BASE + 0x88)
457 #define AR_PHY_SWITCH_COM_2      (AR_SM_BASE + 0x8c)
458 #define AR_PHY_RX_CHAINMASK      (AR_SM_BASE + 0xa0)
459 #define AR_PHY_CAL_CHAINMASK     (AR_SM_BASE + 0xc0)
460 #define AR_PHY_CALMODE           (AR_SM_BASE + 0xc8)
461 #define AR_PHY_FCAL_1            (AR_SM_BASE + 0xcc)
462 #define AR_PHY_FCAL_2_0          (AR_SM_BASE + 0xd0)
463 #define AR_PHY_DFT_TONE_CTL_0    (AR_SM_BASE + 0xd4)
464 #define AR_PHY_CL_CAL_CTL        (AR_SM_BASE + 0xd8)
465 #define AR_PHY_CL_TAB_0          (AR_SM_BASE + 0x100)
466 #define AR_PHY_SYNTH_CONTROL     (AR_SM_BASE + 0x140)
467 #define AR_PHY_ADDAC_CLK_SEL     (AR_SM_BASE + 0x144)
468 #define AR_PHY_PLL_CTL           (AR_SM_BASE + 0x148)
469 #define AR_PHY_ANALOG_SWAP       (AR_SM_BASE + 0x14c)
470 #define AR_PHY_ADDAC_PARA_CTL    (AR_SM_BASE + 0x150)
471 #define AR_PHY_XPA_CFG           (AR_SM_BASE + 0x158)
472 
473 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A           0x0001FC00
474 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S         10
475 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A                       0x3FF
476 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S                     0
477 
478 #define AR_PHY_TEST              (AR_SM_BASE + 0x160)
479 
480 #define AR_PHY_TEST_BBB_OBS_SEL       0x780000
481 #define AR_PHY_TEST_BBB_OBS_SEL_S     19
482 
483 #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
484 #define AR_PHY_TEST_RX_OBS_SEL_BIT5   (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
485 
486 #define AR_PHY_TEST_CHAIN_SEL      0xC0000000
487 #define AR_PHY_TEST_CHAIN_SEL_S    30
488 
489 #define AR_PHY_TEST_CTL_STATUS   (AR_SM_BASE + 0x164)
490 #define AR_PHY_TEST_CTL_TSTDAC_EN         0x1
491 #define AR_PHY_TEST_CTL_TSTDAC_EN_S       0
492 #define AR_PHY_TEST_CTL_TX_OBS_SEL        0x1C
493 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S      2
494 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL    0x60
495 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S  5
496 #define AR_PHY_TEST_CTL_TSTADC_EN         0x100
497 #define AR_PHY_TEST_CTL_TSTADC_EN_S       8
498 #define AR_PHY_TEST_CTL_RX_OBS_SEL        0x3C00
499 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S      10
500 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL	  0xe0000000
501 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S	  29
502 
503 
504 #define AR_PHY_TSTDAC            (AR_SM_BASE + 0x168)
505 
506 #define AR_PHY_CHAN_STATUS       (AR_SM_BASE + 0x16c)
507 
508 #define AR_PHY_CHAN_INFO_MEMORY				(AR_SM_BASE + 0x170)
509 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ	0x00000008
510 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S	3
511 
512 #define AR_PHY_CHNINFO_NOISEPWR  (AR_SM_BASE + 0x174)
513 #define AR_PHY_CHNINFO_GAINDIFF  (AR_SM_BASE + 0x178)
514 #define AR_PHY_CHNINFO_FINETIM   (AR_SM_BASE + 0x17c)
515 #define AR_PHY_CHAN_INFO_GAIN_0  (AR_SM_BASE + 0x180)
516 #define AR_PHY_SCRAMBLER_SEED    (AR_SM_BASE + 0x190)
517 #define AR_PHY_CCK_TX_CTRL       (AR_SM_BASE + 0x194)
518 
519 #define AR_PHY_HEAVYCLIP_CTL     (AR_SM_BASE + 0x1a4)
520 #define AR_PHY_HEAVYCLIP_20      (AR_SM_BASE + 0x1a8)
521 #define AR_PHY_HEAVYCLIP_40      (AR_SM_BASE + 0x1ac)
522 #define AR_PHY_ILLEGAL_TXRATE    (AR_SM_BASE + 0x1b0)
523 
524 #define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))
525 
526 #define AR_PHY_PWRTX_MAX         (AR_SM_BASE + 0x1f0)
527 #define AR_PHY_POWER_TX_SUB      (AR_SM_BASE + 0x1f4)
528 
529 #define AR_PHY_TPC_1				(AR_SM_BASE + 0x1f8)
530 #define AR_PHY_TPC_1_FORCED_DAC_GAIN		0x0000003e
531 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S		1
532 #define AR_PHY_TPC_1_FORCE_DAC_GAIN		0x00000001
533 #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S		0
534 
535 #define AR_PHY_TPC_4_B0				(AR_SM_BASE + 0x204)
536 #define AR_PHY_TPC_5_B0				(AR_SM_BASE + 0x208)
537 #define AR_PHY_TPC_6_B0				(AR_SM_BASE + 0x20c)
538 
539 #define AR_PHY_TPC_11_B0			(AR_SM_BASE + 0x220)
540 #define AR_PHY_TPC_11_B1			(AR_SM1_BASE + 0x220)
541 #define AR_PHY_TPC_11_B2			(AR_SM2_BASE + 0x220)
542 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA		0x00ff0000
543 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S		16
544 
545 #define AR_PHY_TPC_12				(AR_SM_BASE + 0x224)
546 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5	0x3e000000
547 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S	25
548 
549 #define AR_PHY_TPC_18				(AR_SM_BASE + 0x23c)
550 #define AR_PHY_TPC_18_THERM_CAL_VALUE           0x000000ff
551 #define AR_PHY_TPC_18_THERM_CAL_VALUE_S         0
552 #define AR_PHY_TPC_18_VOLT_CAL_VALUE		0x0000ff00
553 #define AR_PHY_TPC_18_VOLT_CAL_VALUE_S		8
554 
555 #define AR_PHY_TPC_19				(AR_SM_BASE + 0x240)
556 #define AR_PHY_TPC_19_ALPHA_VOLT		0x001f0000
557 #define AR_PHY_TPC_19_ALPHA_VOLT_S		16
558 #define AR_PHY_TPC_19_ALPHA_THERM		0xff
559 #define AR_PHY_TPC_19_ALPHA_THERM_S		0
560 
561 #define AR_PHY_TX_FORCED_GAIN				(AR_SM_BASE + 0x258)
562 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN		0x00000001
563 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S		0
564 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN	0x0000000e
565 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S	1
566 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN	0x00000030
567 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S	4
568 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN		0x000003c0
569 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S	6
570 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA		0x00003c00
571 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S		10
572 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB		0x0003c000
573 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S		14
574 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC		0x003c0000
575 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S		18
576 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND		0x00c00000
577 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S		22
578 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL		0x01000000
579 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S	24
580 
581 
582 #define AR_PHY_PDADC_TAB_0       (AR_SM_BASE + 0x280)
583 
584 #define AR_PHY_TXGAIN_TABLE      (AR_SM_BASE + 0x300)
585 
586 #define AR_PHY_TX_IQCAL_CONTROL_0   (AR_SM_BASE + (AR_SREV_9485(ah) ? \
587 						 0x3c4 : 0x444))
588 #define AR_PHY_TX_IQCAL_CONTROL_1   (AR_SM_BASE + (AR_SREV_9485(ah) ? \
589 						 0x3c8 : 0x448))
590 #define AR_PHY_TX_IQCAL_START       (AR_SM_BASE + (AR_SREV_9485(ah) ? \
591 						 0x3c4 : 0x440))
592 #define AR_PHY_TX_IQCAL_STATUS_B0   (AR_SM_BASE + (AR_SREV_9485(ah) ? \
593 						 0x3f0 : 0x48c))
594 #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i)    (AR_SM_BASE + \
595 					     (AR_SREV_9485(ah) ? \
596 					      0x3d0 : 0x450) + ((_i) << 2))
597 #define AR_PHY_RTT_CTRL			(AR_SM_BASE + 0x380)
598 
599 #define AR_PHY_WATCHDOG_STATUS      (AR_SM_BASE + 0x5c0)
600 #define AR_PHY_WATCHDOG_CTL_1       (AR_SM_BASE + 0x5c4)
601 #define AR_PHY_WATCHDOG_CTL_2       (AR_SM_BASE + 0x5c8)
602 #define AR_PHY_WATCHDOG_CTL         (AR_SM_BASE + 0x5cc)
603 #define AR_PHY_ONLY_WARMRESET       (AR_SM_BASE + 0x5d0)
604 #define AR_PHY_ONLY_CTL             (AR_SM_BASE + 0x5d4)
605 #define AR_PHY_ECO_CTRL             (AR_SM_BASE + 0x5dc)
606 
607 #define AR_PHY_BB_THERM_ADC_1				(AR_SM_BASE + 0x248)
608 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM		0x000000ff
609 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S		0
610 
611 #define AR_PHY_BB_THERM_ADC_4				(AR_SM_BASE + 0x254)
612 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE	0x000000ff
613 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S	0
614 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE		0x0000ff00
615 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S	8
616 
617 /* AIC Registers */
618 #define AR_PHY_AIC_CTRL_0_B0	(AR_SM_BASE + 0x4b0)
619 #define AR_PHY_AIC_CTRL_1_B0	(AR_SM_BASE + 0x4b4)
620 #define AR_PHY_AIC_CTRL_2_B0	(AR_SM_BASE + 0x4b8)
621 #define AR_PHY_AIC_CTRL_3_B0	(AR_SM_BASE + 0x4bc)
622 #define AR_PHY_AIC_STAT_0_B0	(AR_SM_BASE + 0x4c4))
623 #define AR_PHY_AIC_STAT_1_B0	(AR_SM_BASE + 0x4c8))
624 #define AR_PHY_AIC_CTRL_4_B0	(AR_SM_BASE + 0x4c0)
625 #define AR_PHY_AIC_STAT_2_B0	(AR_SM_BASE + 0x4cc)
626 
627 #define AR_PHY_65NM_CH0_SYNTH4      0x1608c
628 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT   (AR_SREV_9462(ah) ? 0x00000001 : 0x00000002)
629 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S (AR_SREV_9462(ah) ? 0 : 1)
630 #define AR_PHY_65NM_CH0_SYNTH7      0x16098
631 #define AR_PHY_65NM_CH0_BIAS1       0x160c0
632 #define AR_PHY_65NM_CH0_BIAS2       0x160c4
633 #define AR_PHY_65NM_CH0_BIAS4       0x160cc
634 #define AR_PHY_65NM_CH0_RXTX4       0x1610c
635 
636 #define AR_CH0_TOP	(AR_SREV_9300(ah) ? 0x16288 : \
637 				((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
638 #define AR_CH0_TOP_XPABIASLVL (0x300)
639 #define AR_CH0_TOP_XPABIASLVL_S (8)
640 
641 #define AR_CH0_THERM	(AR_SREV_9300(ah) ? 0x16290 : \
642 				((AR_SREV_9485(ah) ? 0x1628c : 0x16294)))
643 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
644 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
645 #define AR_CH0_THERM_XPASHORT2GND 0x4
646 #define AR_CH0_THERM_XPASHORT2GND_S 2
647 
648 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
649 #define AR_SWITCH_TABLE_COM_ALL_S (0)
650 #define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)
651 #define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)
652 #define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
653 #define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
654 #define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
655 
656 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
657 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
658 
659 #define AR_SWITCH_TABLE_ALL (0xfff)
660 #define AR_SWITCH_TABLE_ALL_S (0)
661 
662 #define AR_PHY_65NM_CH0_THERM       (AR_SREV_9300(ah) ? 0x16290 :\
663 					(AR_SREV_9462(ah) ? 0x16294 : 0x1628c))
664 
665 #define AR_PHY_65NM_CH0_THERM_LOCAL   0x80000000
666 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
667 #define AR_PHY_65NM_CH0_THERM_START   0x20000000
668 #define AR_PHY_65NM_CH0_THERM_START_S 29
669 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT   0x0000ff00
670 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
671 
672 #define AR_PHY_65NM_CH0_RXTX1       0x16100
673 #define AR_PHY_65NM_CH0_RXTX2       0x16104
674 #define AR_PHY_65NM_CH1_RXTX1       0x16500
675 #define AR_PHY_65NM_CH1_RXTX2       0x16504
676 #define AR_PHY_65NM_CH2_RXTX1       0x16900
677 #define AR_PHY_65NM_CH2_RXTX2       0x16904
678 
679 #define AR_CH0_TOP2		(AR_SREV_9300(ah) ? 0x1628c : \
680 					(AR_SREV_9462(ah) ? 0x16290 : 0x16284))
681 #define AR_CH0_TOP2_XPABIASLVL		0xf000
682 #define AR_CH0_TOP2_XPABIASLVL_S	12
683 
684 #define AR_CH0_XTAL		(AR_SREV_9300(ah) ? 0x16294 : \
685 					(AR_SREV_9462(ah) ? 0x16298 : 0x16290))
686 #define AR_CH0_XTAL_CAPINDAC	0x7f000000
687 #define AR_CH0_XTAL_CAPINDAC_S	24
688 #define AR_CH0_XTAL_CAPOUTDAC	0x00fe0000
689 #define AR_CH0_XTAL_CAPOUTDAC_S	17
690 
691 #define AR_PHY_PMU1		(AR_SREV_9462(ah) ? 0x16340 : 0x16c40)
692 #define AR_PHY_PMU1_PWD		0x1
693 #define AR_PHY_PMU1_PWD_S	0
694 
695 #define AR_PHY_PMU2		(AR_SREV_9462(ah) ? 0x16344 : 0x16c44)
696 #define AR_PHY_PMU2_PGM		0x00200000
697 #define AR_PHY_PMU2_PGM_S	21
698 
699 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT		0x00380000
700 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S	19
701 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT		0x00c00000
702 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S	22
703 #define AR_PHY_LNAGAIN_LONG_SHIFT		0xe0000000
704 #define AR_PHY_LNAGAIN_LONG_SHIFT_S		29
705 #define AR_PHY_MXRGAIN_LONG_SHIFT		0x03000000
706 #define AR_PHY_MXRGAIN_LONG_SHIFT_S		24
707 #define AR_PHY_VGAGAIN_LONG_SHIFT		0x1c000000
708 #define AR_PHY_VGAGAIN_LONG_SHIFT_S		26
709 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT		0x00000001
710 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S		0
711 #define AR_PHY_MANRXGAIN_LONG_SHIFT		0x00000002
712 #define AR_PHY_MANRXGAIN_LONG_SHIFT_S		1
713 
714 /*
715  * SM Field Definitions
716  */
717 #define AR_PHY_CL_CAL_ENABLE          0x00000002
718 #define AR_PHY_PARALLEL_CAL_ENABLE    0x00000001
719 #define AR_PHY_TPCRG1_PD_CAL_ENABLE   0x00400000
720 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
721 
722 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
723 
724 #define AR_PHY_FCAL20_CAP_STATUS_0    0x01f00000
725 #define AR_PHY_FCAL20_CAP_STATUS_0_S  20
726 
727 #define AR_PHY_RFBUS_REQ_EN     0x00000001  /* request for RF bus */
728 #define AR_PHY_RFBUS_GRANT_EN   0x00000001  /* RF bus granted */
729 #define AR_PHY_GC_TURBO_MODE       0x00000001  /* set turbo mode bits */
730 #define AR_PHY_GC_TURBO_SHORT      0x00000002  /* set short symbols to turbo mode setting */
731 #define AR_PHY_GC_DYN2040_EN       0x00000004  /* enable dyn 20/40 mode */
732 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008  /* dyn 20/40 - primary only */
733 #define AR_PHY_GC_DYN2040_PRI_CH   0x00000010  /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
734 #define AR_PHY_GC_DYN2040_PRI_CH_S 4
735 #define AR_PHY_GC_DYN2040_EXT_CH   0x00000020  /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
736 #define AR_PHY_GC_HT_EN            0x00000040  /* ht enable */
737 #define AR_PHY_GC_SHORT_GI_40      0x00000080  /* allow short GI for HT 40 */
738 #define AR_PHY_GC_WALSH            0x00000100  /* walsh spatial spreading for 2 chains,2 streams TX */
739 #define AR_PHY_GC_SINGLE_HT_LTF1   0x00000200  /* single length (4us) 1st HT long training symbol */
740 #define AR_PHY_GC_GF_DETECT_EN     0x00000400  /* enable Green Field detection. Only affects rx, not tx */
741 #define AR_PHY_GC_ENABLE_DAC_FIFO  0x00000800  /* fifo between bb and dac */
742 #define AR_PHY_RX_DELAY_DELAY      0x00003FFF  /* delay from wakeup to rx ena */
743 
744 #define AR_PHY_CALMODE_IQ           0x00000000
745 #define AR_PHY_CALMODE_ADC_GAIN     0x00000001
746 #define AR_PHY_CALMODE_ADC_DC_PER   0x00000002
747 #define AR_PHY_CALMODE_ADC_DC_INIT  0x00000003
748 #define AR_PHY_SWAP_ALT_CHAIN       0x00000040
749 #define AR_PHY_MODE_OFDM            0x00000000
750 #define AR_PHY_MODE_CCK             0x00000001
751 #define AR_PHY_MODE_DYNAMIC         0x00000004
752 #define AR_PHY_MODE_DYNAMIC_S       2
753 #define AR_PHY_MODE_HALF            0x00000020
754 #define AR_PHY_MODE_QUARTER         0x00000040
755 #define AR_PHY_MAC_CLK_MODE         0x00000080
756 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
757 #define AR_PHY_MODE_SVD_HALF        0x00000200
758 #define AR_PHY_ACTIVE_EN    0x00000001
759 #define AR_PHY_ACTIVE_DIS   0x00000000
760 #define AR_PHY_FORCE_XPA_CFG    0x000000001
761 #define AR_PHY_FORCE_XPA_CFG_S  0
762 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF    0xFF000000
763 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S  24
764 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF    0x00FF0000
765 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S  16
766 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON      0x0000FF00
767 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S    8
768 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON      0x000000FF
769 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S    0
770 #define AR_PHY_TX_END_TO_A2_RX_ON       0x00FF0000
771 #define AR_PHY_TX_END_TO_A2_RX_ON_S     16
772 #define AR_PHY_TX_END_DATA_START  0x000000FF
773 #define AR_PHY_TX_END_DATA_START_S  0
774 #define AR_PHY_TX_END_PA_ON       0x0000FF00
775 #define AR_PHY_TX_END_PA_ON_S       8
776 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP   0x0000000F
777 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S     0
778 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1    0x000003F0
779 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S  4
780 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2    0x0000FC00
781 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S  10
782 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3    0x003F0000
783 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S  16
784 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4    0x0FC00000
785 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S  22
786 #define AR_PHY_TPCRG1_NUM_PD_GAIN   0x0000c000
787 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
788 #define AR_PHY_TPCRG1_PD_GAIN_1    0x00030000
789 #define AR_PHY_TPCRG1_PD_GAIN_1_S  16
790 #define AR_PHY_TPCRG1_PD_GAIN_2    0x000C0000
791 #define AR_PHY_TPCRG1_PD_GAIN_2_S  18
792 #define AR_PHY_TPCRG1_PD_GAIN_3    0x00300000
793 #define AR_PHY_TPCRG1_PD_GAIN_3_S  20
794 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN   0x0000003e
795 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
796 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN    0x00000001
797 #define AR_PHY_TXGAIN_FORCE               0x00000001
798 #define AR_PHY_TXGAIN_FORCE_S		  0
799 #define AR_PHY_TXGAIN_FORCED_PADVGNRA     0x00003c00
800 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S   10
801 #define AR_PHY_TXGAIN_FORCED_PADVGNRB     0x0003c000
802 #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S   14
803 #define AR_PHY_TXGAIN_FORCED_PADVGNRD     0x00c00000
804 #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S   22
805 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN    0x000003c0
806 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S  6
807 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN  0x0000000e
808 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
809 
810 #define AR_PHY_POWER_TX_RATE1   0x9934
811 #define AR_PHY_POWER_TX_RATE2   0x9938
812 #define AR_PHY_POWER_TX_RATE_MAX    0x993c
813 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
814 #define PHY_AGC_CLR             0x10000000
815 #define RFSILENT_BB             0x00002000
816 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK          0xFFF
817 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT    0x800
818 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT         320
819 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK         0x0001
820 #define AR_PHY_RX_DELAY_DELAY   0x00003FFF
821 #define AR_PHY_CCK_TX_CTRL_JAPAN    0x00000010
822 #define AR_PHY_SPECTRAL_SCAN_ENABLE         0x00000001
823 #define AR_PHY_SPECTRAL_SCAN_ENABLE_S       0
824 #define AR_PHY_SPECTRAL_SCAN_ACTIVE         0x00000002
825 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S       1
826 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD     0x000000F0
827 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S   4
828 #define AR_PHY_SPECTRAL_SCAN_PERIOD         0x0000FF00
829 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S       8
830 #define AR_PHY_SPECTRAL_SCAN_COUNT          0x00FF0000
831 #define AR_PHY_SPECTRAL_SCAN_COUNT_S        16
832 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT   0x01000000
833 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
834 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR      0x00000004
835 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION     0x00000001
836 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S   0
837 #define AR_PHY_RTT_CTRL_RESTORE_MASK            0x0000007E
838 #define AR_PHY_RTT_CTRL_RESTORE_MASK_S          1
839 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE     0x00000080
840 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S   7
841 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS          0x00000001
842 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S        0
843 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE           0x00000002
844 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_S         1
845 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR            0x0000001C
846 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_S          2
847 #define AR_PHY_RTT_SW_RTT_TABLE_DATA            0xFFFFFFF0
848 #define AR_PHY_RTT_SW_RTT_TABLE_DATA_S          4
849 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL                   0x80000000
850 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S                         31
851 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT             0x01fc0000
852 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S                   18
853 #define AR_PHY_TX_IQCAL_START_DO_CAL	    0x00000001
854 #define AR_PHY_TX_IQCAL_START_DO_CAL_S	    0
855 
856 #define AR_PHY_TX_IQCAL_STATUS_FAILED    0x00000001
857 #define AR_PHY_CALIBRATED_GAINS_0	 0x3e
858 #define AR_PHY_CALIBRATED_GAINS_0_S	 1
859 
860 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE      0x00003fff
861 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S    0
862 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE      0x0fffc000
863 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S    14
864 
865 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON          0x10000000
866 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S        28
867 
868 /*
869  * Channel 1 Register Map
870  */
871 #define AR_CHAN1_BASE	0xa800
872 
873 #define AR_PHY_EXT_CCA_1            (AR_CHAN1_BASE + 0x30)
874 #define AR_PHY_TX_PHASE_RAMP_1      (AR_CHAN1_BASE + 0xd0)
875 #define AR_PHY_ADC_GAIN_DC_CORR_1   (AR_CHAN1_BASE + 0xd4)
876 
877 #define AR_PHY_SPUR_REPORT_1        (AR_CHAN1_BASE + 0xa8)
878 #define AR_PHY_CHAN_INFO_TAB_1      (AR_CHAN1_BASE + 0x300)
879 #define AR_PHY_RX_IQCAL_CORR_B1     (AR_CHAN1_BASE + 0xdc)
880 
881 /*
882  * Channel 1 Field Definitions
883  */
884 #define AR_PHY_CH1_EXT_MINCCA_PWR   0x01FF0000
885 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
886 
887 /*
888  * AGC 1 Register Map
889  */
890 #define AR_AGC1_BASE	0xae00
891 
892 #define AR_PHY_FORCEMAX_GAINS_1      (AR_AGC1_BASE + 0x4)
893 #define AR_PHY_EXT_ATTEN_CTL_1       (AR_AGC1_BASE + 0x18)
894 #define AR_PHY_CCA_1                 (AR_AGC1_BASE + 0x1c)
895 #define AR_PHY_CCA_CTRL_1            (AR_AGC1_BASE + 0x20)
896 #define AR_PHY_RSSI_1                (AR_AGC1_BASE + 0x180)
897 #define AR_PHY_SPUR_CCK_REP_1        (AR_AGC1_BASE + 0x184)
898 #define AR_PHY_RX_OCGAIN_2           (AR_AGC1_BASE + 0x200)
899 
900 /*
901  * AGC 1 Field Definitions
902  */
903 #define AR_PHY_CH1_MINCCA_PWR   0x1FF00000
904 #define AR_PHY_CH1_MINCCA_PWR_S 20
905 
906 /*
907  * SM 1 Register Map
908  */
909 #define AR_SM1_BASE	0xb200
910 
911 #define AR_PHY_SWITCH_CHAIN_1   (AR_SM1_BASE + 0x84)
912 #define AR_PHY_FCAL_2_1         (AR_SM1_BASE + 0xd0)
913 #define AR_PHY_DFT_TONE_CTL_1   (AR_SM1_BASE + 0xd4)
914 #define AR_PHY_CL_TAB_1         (AR_SM1_BASE + 0x100)
915 #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
916 #define AR_PHY_TPC_4_B1         (AR_SM1_BASE + 0x204)
917 #define AR_PHY_TPC_5_B1         (AR_SM1_BASE + 0x208)
918 #define AR_PHY_TPC_6_B1         (AR_SM1_BASE + 0x20c)
919 #define AR_PHY_TPC_11_B1        (AR_SM1_BASE + 0x220)
920 #define AR_PHY_PDADC_TAB_1	(AR_SM1_BASE + (AR_SREV_AR9462(ah) ? \
921 					0x280 : 0x240))
922 #define AR_PHY_TPC_19_B1	(AR_SM1_BASE + 0x240)
923 #define AR_PHY_TPC_19_B1_ALPHA_THERM		0xff
924 #define AR_PHY_TPC_19_B1_ALPHA_THERM_S		0
925 #define AR_PHY_TX_IQCAL_STATUS_B1   (AR_SM1_BASE + 0x48c)
926 #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i)    (AR_SM1_BASE + 0x450 + ((_i) << 2))
927 
928 /* SM 1 AIC Registers */
929 
930 #define AR_PHY_AIC_CTRL_0_B1	(AR_SM1_BASE + 0x4b0)
931 #define AR_PHY_AIC_CTRL_1_B1	(AR_SM1_BASE + 0x4b4)
932 #define AR_PHY_AIC_CTRL_2_B1	(AR_SM1_BASE + 0x4b8)
933 #define AR_PHY_AIC_STAT_0_B1	(AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
934 					0x4c0 : 0x4c4))
935 #define AR_PHY_AIC_STAT_1_B1	(AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
936 					0x4c4 : 0x4c8))
937 #define AR_PHY_AIC_CTRL_4_B1	(AR_SM1_BASE + 0x4c0)
938 #define AR_PHY_AIC_STAT_2_B1	(AR_SM1_BASE + 0x4cc)
939 
940 #define AR_PHY_AIC_SRAM_ADDR_B1	(AR_SM1_BASE + 0x5f0)
941 #define AR_PHY_AIC_SRAM_DATA_B1	(AR_SM1_BASE + 0x5f4)
942 
943 #define AR_PHY_RTT_TABLE_SW_INTF_B(i)	(0x384 + ((i) ? \
944 					AR_SM1_BASE : AR_SM_BASE))
945 #define AR_PHY_RTT_TABLE_SW_INTF_1_B(i)	(0x388 + ((i) ? \
946 					AR_SM1_BASE : AR_SM_BASE))
947 /*
948  * Channel 2 Register Map
949  */
950 #define AR_CHAN2_BASE	0xb800
951 
952 #define AR_PHY_EXT_CCA_2            (AR_CHAN2_BASE + 0x30)
953 #define AR_PHY_TX_PHASE_RAMP_2      (AR_CHAN2_BASE + 0xd0)
954 #define AR_PHY_ADC_GAIN_DC_CORR_2   (AR_CHAN2_BASE + 0xd4)
955 
956 #define AR_PHY_SPUR_REPORT_2        (AR_CHAN2_BASE + 0xa8)
957 #define AR_PHY_CHAN_INFO_TAB_2      (AR_CHAN2_BASE + 0x300)
958 #define AR_PHY_RX_IQCAL_CORR_B2     (AR_CHAN2_BASE + 0xdc)
959 
960 /*
961  * Channel 2 Field Definitions
962  */
963 #define AR_PHY_CH2_EXT_MINCCA_PWR   0x01FF0000
964 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
965 /*
966  * AGC 2 Register Map
967  */
968 #define AR_AGC2_BASE	0xbe00
969 
970 #define AR_PHY_FORCEMAX_GAINS_2      (AR_AGC2_BASE + 0x4)
971 #define AR_PHY_EXT_ATTEN_CTL_2       (AR_AGC2_BASE + 0x18)
972 #define AR_PHY_CCA_2                 (AR_AGC2_BASE + 0x1c)
973 #define AR_PHY_CCA_CTRL_2            (AR_AGC2_BASE + 0x20)
974 #define AR_PHY_RSSI_2                (AR_AGC2_BASE + 0x180)
975 
976 /*
977  * AGC 2 Field Definitions
978  */
979 #define AR_PHY_CH2_MINCCA_PWR   0x1FF00000
980 #define AR_PHY_CH2_MINCCA_PWR_S 20
981 
982 /*
983  * SM 2 Register Map
984  */
985 #define AR_SM2_BASE	0xc200
986 
987 #define AR_PHY_SWITCH_CHAIN_2    (AR_SM2_BASE + 0x84)
988 #define AR_PHY_FCAL_2_2          (AR_SM2_BASE + 0xd0)
989 #define AR_PHY_DFT_TONE_CTL_2    (AR_SM2_BASE + 0xd4)
990 #define AR_PHY_CL_TAB_2          (AR_SM2_BASE + 0x100)
991 #define AR_PHY_CHAN_INFO_GAIN_2  (AR_SM2_BASE + 0x180)
992 #define AR_PHY_TPC_4_B2          (AR_SM2_BASE + 0x204)
993 #define AR_PHY_TPC_5_B2          (AR_SM2_BASE + 0x208)
994 #define AR_PHY_TPC_6_B2          (AR_SM2_BASE + 0x20c)
995 #define AR_PHY_TPC_11_B2         (AR_SM2_BASE + 0x220)
996 #define AR_PHY_PDADC_TAB_2       (AR_SM2_BASE + 0x240)
997 #define AR_PHY_TX_IQCAL_STATUS_B2   (AR_SM2_BASE + 0x48c)
998 #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i)    (AR_SM2_BASE + 0x450 + ((_i) << 2))
999 
1000 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED    0x00000001
1001 
1002 /*
1003  * AGC 3 Register Map
1004  */
1005 #define AR_AGC3_BASE	0xce00
1006 
1007 #define AR_PHY_RSSI_3            (AR_AGC3_BASE + 0x180)
1008 
1009 /* GLB Registers */
1010 #define AR_GLB_BASE	0x20000
1011 #define AR_GLB_GPIO_CONTROL	(AR_GLB_BASE)
1012 #define AR_PHY_GLB_CONTROL	(AR_GLB_BASE + 0x44)
1013 #define AR_GLB_SCRATCH(_ah)	(AR_GLB_BASE + \
1014 					(AR_SREV_9462_20(_ah) ? 0x4c : 0x50))
1015 #define AR_GLB_STATUS		(AR_GLB_BASE + 0x48)
1016 
1017 /*
1018  * Misc helper defines
1019  */
1020 #define AR_PHY_CHAIN_OFFSET     (AR_CHAN1_BASE - AR_CHAN_BASE)
1021 
1022 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1023 #define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1024 #define AR_PHY_SWITCH_CHAIN(_i)     (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1025 #define AR_PHY_EXT_ATTEN_CTL(_i)    (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1026 
1027 #define AR_PHY_RXGAIN(_i)           (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1028 #define AR_PHY_TPCRG5(_i)           (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1029 #define AR_PHY_PDADC_TAB(_i)        (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1030 
1031 #define AR_PHY_CAL_MEAS_0(_i)       (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1032 #define AR_PHY_CAL_MEAS_1(_i)       (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1033 #define AR_PHY_CAL_MEAS_2(_i)       (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1034 #define AR_PHY_CAL_MEAS_3(_i)       (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1035 #define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1036 #define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1037 #define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1038 #define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1039 
1040 #define AR_PHY_WATCHDOG_NON_IDLE_ENABLE    0x00000001
1041 #define AR_PHY_WATCHDOG_IDLE_ENABLE        0x00000002
1042 #define AR_PHY_WATCHDOG_IDLE_MASK          0xFFFF0000
1043 #define AR_PHY_WATCHDOG_NON_IDLE_MASK      0x0000FFFC
1044 
1045 #define AR_PHY_WATCHDOG_RST_ENABLE         0x00000002
1046 #define AR_PHY_WATCHDOG_IRQ_ENABLE         0x00000004
1047 #define AR_PHY_WATCHDOG_CNTL2_MASK         0xFFFFFFF9
1048 
1049 #define AR_PHY_WATCHDOG_INFO               0x00000007
1050 #define AR_PHY_WATCHDOG_INFO_S             0
1051 #define AR_PHY_WATCHDOG_DET_HANG           0x00000008
1052 #define AR_PHY_WATCHDOG_DET_HANG_S         3
1053 #define AR_PHY_WATCHDOG_RADAR_SM           0x000000F0
1054 #define AR_PHY_WATCHDOG_RADAR_SM_S         4
1055 #define AR_PHY_WATCHDOG_RX_OFDM_SM         0x00000F00
1056 #define AR_PHY_WATCHDOG_RX_OFDM_SM_S       8
1057 #define AR_PHY_WATCHDOG_RX_CCK_SM          0x0000F000
1058 #define AR_PHY_WATCHDOG_RX_CCK_SM_S        12
1059 #define AR_PHY_WATCHDOG_TX_OFDM_SM         0x000F0000
1060 #define AR_PHY_WATCHDOG_TX_OFDM_SM_S       16
1061 #define AR_PHY_WATCHDOG_TX_CCK_SM          0x00F00000
1062 #define AR_PHY_WATCHDOG_TX_CCK_SM_S        20
1063 #define AR_PHY_WATCHDOG_AGC_SM             0x0F000000
1064 #define AR_PHY_WATCHDOG_AGC_SM_S           24
1065 #define AR_PHY_WATCHDOG_SRCH_SM            0xF0000000
1066 #define AR_PHY_WATCHDOG_SRCH_SM_S          28
1067 
1068 #define AR_PHY_WATCHDOG_STATUS_CLR         0x00000008
1069 
1070 /*
1071  * PAPRD registers
1072  */
1073 #define AR_PHY_XPA_TIMING_CTL		(AR_SM_BASE + 0x64)
1074 
1075 #define AR_PHY_PAPRD_AM2AM		(AR_CHAN_BASE + 0xe4)
1076 #define AR_PHY_PAPRD_AM2AM_MASK		0x01ffffff
1077 #define AR_PHY_PAPRD_AM2AM_MASK_S	0
1078 
1079 #define AR_PHY_PAPRD_AM2PM		(AR_CHAN_BASE + 0xe8)
1080 #define AR_PHY_PAPRD_AM2PM_MASK		0x01ffffff
1081 #define AR_PHY_PAPRD_AM2PM_MASK_S	0
1082 
1083 #define AR_PHY_PAPRD_HT40		(AR_CHAN_BASE + 0xec)
1084 #define AR_PHY_PAPRD_HT40_MASK		0x01ffffff
1085 #define AR_PHY_PAPRD_HT40_MASK_S	0
1086 
1087 #define AR_PHY_PAPRD_CTRL0_B0				(AR_CHAN_BASE + 0xf0)
1088 #define AR_PHY_PAPRD_CTRL0_B1				(AR_CHAN1_BASE + 0xf0)
1089 #define AR_PHY_PAPRD_CTRL0_B2				(AR_CHAN2_BASE + 0xf0)
1090 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE			0x00000001
1091 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S		0
1092 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK	0x00000002
1093 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S	1
1094 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH		0xf8000000
1095 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S		27
1096 
1097 #define AR_PHY_PAPRD_CTRL1_B0				(AR_CHAN_BASE + 0xf4)
1098 #define AR_PHY_PAPRD_CTRL1_B1				(AR_CHAN1_BASE + 0xf4)
1099 #define AR_PHY_PAPRD_CTRL1_B2				(AR_CHAN2_BASE + 0xf4)
1100 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA		0x00000001
1101 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S	0
1102 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE	0x00000002
1103 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S	1
1104 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE	0x00000004
1105 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S	2
1106 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL	0x000001f8
1107 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S	3
1108 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK	0x0001fe00
1109 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S	9
1110 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT		0x0ffe0000
1111 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S	17
1112 
1113 #define AR_PHY_PAPRD_TRAINER_CNTL1				(AR_SM_BASE + \
1114 								 (AR_SREV_9485(ah) ? \
1115 								  0x580 : 0x490))
1116 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE	0x00000001
1117 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S	0
1118 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING	0x0000007e
1119 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S	1
1120 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE	0x00000100
1121 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S	8
1122 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE	0x00000200
1123 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S	9
1124 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE	0x00000400
1125 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S	10
1126 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE		0x00000800
1127 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S		11
1128 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP		0x0003f000
1129 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S		12
1130 
1131 #define AR_PHY_PAPRD_TRAINER_CNTL2				(AR_SM_BASE + \
1132 								 (AR_SREV_9485(ah) ? \
1133 								  0x584 : 0x494))
1134 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN	0xFFFFFFFF
1135 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S	0
1136 
1137 #define AR_PHY_PAPRD_TRAINER_CNTL3				(AR_SM_BASE + \
1138 								 (AR_SREV_9485(ah) ? \
1139 								  0x588 : 0x498))
1140 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE	0x0000003f
1141 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S	0
1142 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP		0x00000fc0
1143 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S	6
1144 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL	0x0001f000
1145 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S	12
1146 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES	0x000e0000
1147 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S	17
1148 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN	0x00f00000
1149 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S	20
1150 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN	0x0f000000
1151 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S	24
1152 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE	0x20000000
1153 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S	29
1154 
1155 #define AR_PHY_PAPRD_TRAINER_CNTL4				(AR_SM_BASE + \
1156 								 (AR_SREV_9485(ah) ? \
1157 								  0x58c : 0x49c))
1158 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES	0x03ff0000
1159 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S	16
1160 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA	0x0000f000
1161 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S	12
1162 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR		0x00000fff
1163 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S		0
1164 
1165 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0			(AR_CHAN_BASE + 0x100)
1166 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0			(AR_CHAN_BASE + 0x104)
1167 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0			(AR_CHAN_BASE + 0x108)
1168 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0			(AR_CHAN_BASE + 0x10c)
1169 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0			(AR_CHAN_BASE + 0x110)
1170 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0			(AR_CHAN_BASE + 0x114)
1171 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0			(AR_CHAN_BASE + 0x118)
1172 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0			(AR_CHAN_BASE + 0x11c)
1173 #define AR_PHY_PAPRD_PRE_POST_SCALING				0x3FFFF
1174 #define AR_PHY_PAPRD_PRE_POST_SCALING_S				0
1175 
1176 #define AR_PHY_PAPRD_TRAINER_STAT1				(AR_SM_BASE + 0x4a0)
1177 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE		0x00000001
1178 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S		0
1179 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE	0x00000002
1180 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S	1
1181 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR		0x00000004
1182 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S		2
1183 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE		0x00000008
1184 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S		3
1185 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX		0x000001f0
1186 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S		4
1187 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR		0x0001fe00
1188 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S		9
1189 
1190 #define AR_PHY_PAPRD_TRAINER_STAT2				(AR_SM_BASE + 0x4a4)
1191 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL		0x0000ffff
1192 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S		0
1193 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX		0x001f0000
1194 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S		16
1195 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX		0x00600000
1196 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S		21
1197 
1198 #define AR_PHY_PAPRD_TRAINER_STAT3				(AR_SM_BASE + 0x4a8)
1199 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT	0x000fffff
1200 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S	0
1201 
1202 #define AR_PHY_PAPRD_MEM_TAB_B0			(AR_CHAN_BASE + 0x120)
1203 #define AR_PHY_PAPRD_MEM_TAB_B1			(AR_CHAN1_BASE + 0x120)
1204 #define AR_PHY_PAPRD_MEM_TAB_B2			(AR_CHAN2_BASE + 0x120)
1205 
1206 #define AR_PHY_PA_GAIN123_B0			(AR_CHAN_BASE + 0xf8)
1207 #define AR_PHY_PA_GAIN123_B1			(AR_CHAN1_BASE + 0xf8)
1208 #define AR_PHY_PA_GAIN123_B2			(AR_CHAN2_BASE + 0xf8)
1209 #define AR_PHY_PA_GAIN123_PA_GAIN1		0x3FF
1210 #define AR_PHY_PA_GAIN123_PA_GAIN1_S		0
1211 
1212 #define AR_PHY_POWERTX_RATE5			(AR_SM_BASE + 0x1d0)
1213 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0	0x3F
1214 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S	0
1215 
1216 #define AR_PHY_POWERTX_RATE6			(AR_SM_BASE + 0x1d4)
1217 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5	0x3F00
1218 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S	8
1219 
1220 #define AR_PHY_POWERTX_RATE8			(AR_SM_BASE + 0x1dc)
1221 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5	0x3F00
1222 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S	8
1223 
1224 #define AR_PHY_CL_TAB_CL_GAIN_MOD		0x1f
1225 #define AR_PHY_CL_TAB_CL_GAIN_MOD_S		0
1226 
1227 #endif  /* AR9003_PHY_H */
1228