1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PERF_EVENT_H
3 #define _ASM_X86_PERF_EVENT_H
4
5 #include <linux/static_call.h>
6
7 /*
8 * Performance event hw details:
9 */
10
11 #define INTEL_PMC_MAX_GENERIC 32
12 #define INTEL_PMC_MAX_FIXED 16
13 #define INTEL_PMC_IDX_FIXED 32
14
15 #define X86_PMC_IDX_MAX 64
16
17 #define MSR_ARCH_PERFMON_PERFCTR0 0xc1
18 #define MSR_ARCH_PERFMON_PERFCTR1 0xc2
19
20 #define MSR_ARCH_PERFMON_EVENTSEL0 0x186
21 #define MSR_ARCH_PERFMON_EVENTSEL1 0x187
22
23 #define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
24 #define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
25 #define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
26 #define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
27 #define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
28 #define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
29 #define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
30 #define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
31 #define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
32 #define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
33 #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
34
35 #define INTEL_FIXED_BITS_MASK 0xFULL
36 #define INTEL_FIXED_BITS_STRIDE 4
37 #define INTEL_FIXED_0_KERNEL (1ULL << 0)
38 #define INTEL_FIXED_0_USER (1ULL << 1)
39 #define INTEL_FIXED_0_ANYTHREAD (1ULL << 2)
40 #define INTEL_FIXED_0_ENABLE_PMI (1ULL << 3)
41
42 #define HSW_IN_TX (1ULL << 32)
43 #define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
44 #define ICL_EVENTSEL_ADAPTIVE (1ULL << 34)
45 #define ICL_FIXED_0_ADAPTIVE (1ULL << 32)
46
47 #define intel_fixed_bits_by_idx(_idx, _bits) \
48 ((_bits) << ((_idx) * INTEL_FIXED_BITS_STRIDE))
49
50 #define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
51 #define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
52 #define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
53
54 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
55 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
56 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
57
58 #define AMD64_EVENTSEL_EVENT \
59 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
60 #define INTEL_ARCH_EVENT_MASK \
61 (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
62
63 #define AMD64_L3_SLICE_SHIFT 48
64 #define AMD64_L3_SLICE_MASK \
65 (0xFULL << AMD64_L3_SLICE_SHIFT)
66 #define AMD64_L3_SLICEID_MASK \
67 (0x7ULL << AMD64_L3_SLICE_SHIFT)
68
69 #define AMD64_L3_THREAD_SHIFT 56
70 #define AMD64_L3_THREAD_MASK \
71 (0xFFULL << AMD64_L3_THREAD_SHIFT)
72 #define AMD64_L3_F19H_THREAD_MASK \
73 (0x3ULL << AMD64_L3_THREAD_SHIFT)
74
75 #define AMD64_L3_EN_ALL_CORES BIT_ULL(47)
76 #define AMD64_L3_EN_ALL_SLICES BIT_ULL(46)
77
78 #define AMD64_L3_COREID_SHIFT 42
79 #define AMD64_L3_COREID_MASK \
80 (0x7ULL << AMD64_L3_COREID_SHIFT)
81
82 #define X86_RAW_EVENT_MASK \
83 (ARCH_PERFMON_EVENTSEL_EVENT | \
84 ARCH_PERFMON_EVENTSEL_UMASK | \
85 ARCH_PERFMON_EVENTSEL_EDGE | \
86 ARCH_PERFMON_EVENTSEL_INV | \
87 ARCH_PERFMON_EVENTSEL_CMASK)
88 #define X86_ALL_EVENT_FLAGS \
89 (ARCH_PERFMON_EVENTSEL_EDGE | \
90 ARCH_PERFMON_EVENTSEL_INV | \
91 ARCH_PERFMON_EVENTSEL_CMASK | \
92 ARCH_PERFMON_EVENTSEL_ANY | \
93 ARCH_PERFMON_EVENTSEL_PIN_CONTROL | \
94 HSW_IN_TX | \
95 HSW_IN_TX_CHECKPOINTED)
96 #define AMD64_RAW_EVENT_MASK \
97 (X86_RAW_EVENT_MASK | \
98 AMD64_EVENTSEL_EVENT)
99 #define AMD64_RAW_EVENT_MASK_NB \
100 (AMD64_EVENTSEL_EVENT | \
101 ARCH_PERFMON_EVENTSEL_UMASK)
102
103 #define AMD64_PERFMON_V2_EVENTSEL_EVENT_NB \
104 (AMD64_EVENTSEL_EVENT | \
105 GENMASK_ULL(37, 36))
106
107 #define AMD64_PERFMON_V2_EVENTSEL_UMASK_NB \
108 (ARCH_PERFMON_EVENTSEL_UMASK | \
109 GENMASK_ULL(27, 24))
110
111 #define AMD64_PERFMON_V2_RAW_EVENT_MASK_NB \
112 (AMD64_PERFMON_V2_EVENTSEL_EVENT_NB | \
113 AMD64_PERFMON_V2_EVENTSEL_UMASK_NB)
114
115 #define AMD64_NUM_COUNTERS 4
116 #define AMD64_NUM_COUNTERS_CORE 6
117 #define AMD64_NUM_COUNTERS_NB 4
118
119 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
120 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
121 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
122 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
123 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
124
125 #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
126 #define ARCH_PERFMON_EVENTS_COUNT 7
127
128 #define PEBS_DATACFG_MEMINFO BIT_ULL(0)
129 #define PEBS_DATACFG_GP BIT_ULL(1)
130 #define PEBS_DATACFG_XMMS BIT_ULL(2)
131 #define PEBS_DATACFG_LBRS BIT_ULL(3)
132 #define PEBS_DATACFG_LBR_SHIFT 24
133
134 /* Steal the highest bit of pebs_data_cfg for SW usage */
135 #define PEBS_UPDATE_DS_SW BIT_ULL(63)
136
137 /*
138 * Intel "Architectural Performance Monitoring" CPUID
139 * detection/enumeration details:
140 */
141 union cpuid10_eax {
142 struct {
143 unsigned int version_id:8;
144 unsigned int num_counters:8;
145 unsigned int bit_width:8;
146 unsigned int mask_length:8;
147 } split;
148 unsigned int full;
149 };
150
151 union cpuid10_ebx {
152 struct {
153 unsigned int no_unhalted_core_cycles:1;
154 unsigned int no_instructions_retired:1;
155 unsigned int no_unhalted_reference_cycles:1;
156 unsigned int no_llc_reference:1;
157 unsigned int no_llc_misses:1;
158 unsigned int no_branch_instruction_retired:1;
159 unsigned int no_branch_misses_retired:1;
160 } split;
161 unsigned int full;
162 };
163
164 union cpuid10_edx {
165 struct {
166 unsigned int num_counters_fixed:5;
167 unsigned int bit_width_fixed:8;
168 unsigned int reserved1:2;
169 unsigned int anythread_deprecated:1;
170 unsigned int reserved2:16;
171 } split;
172 unsigned int full;
173 };
174
175 /*
176 * Intel "Architectural Performance Monitoring extension" CPUID
177 * detection/enumeration details:
178 */
179 #define ARCH_PERFMON_EXT_LEAF 0x00000023
180 #define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT 0x1
181 #define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1
182
183 /*
184 * Intel Architectural LBR CPUID detection/enumeration details:
185 */
186 union cpuid28_eax {
187 struct {
188 /* Supported LBR depth values */
189 unsigned int lbr_depth_mask:8;
190 unsigned int reserved:22;
191 /* Deep C-state Reset */
192 unsigned int lbr_deep_c_reset:1;
193 /* IP values contain LIP */
194 unsigned int lbr_lip:1;
195 } split;
196 unsigned int full;
197 };
198
199 union cpuid28_ebx {
200 struct {
201 /* CPL Filtering Supported */
202 unsigned int lbr_cpl:1;
203 /* Branch Filtering Supported */
204 unsigned int lbr_filter:1;
205 /* Call-stack Mode Supported */
206 unsigned int lbr_call_stack:1;
207 } split;
208 unsigned int full;
209 };
210
211 union cpuid28_ecx {
212 struct {
213 /* Mispredict Bit Supported */
214 unsigned int lbr_mispred:1;
215 /* Timed LBRs Supported */
216 unsigned int lbr_timed_lbr:1;
217 /* Branch Type Field Supported */
218 unsigned int lbr_br_type:1;
219 } split;
220 unsigned int full;
221 };
222
223 /*
224 * AMD "Extended Performance Monitoring and Debug" CPUID
225 * detection/enumeration details:
226 */
227 union cpuid_0x80000022_ebx {
228 struct {
229 /* Number of Core Performance Counters */
230 unsigned int num_core_pmc:4;
231 /* Number of available LBR Stack Entries */
232 unsigned int lbr_v2_stack_sz:6;
233 /* Number of Data Fabric Counters */
234 unsigned int num_df_pmc:6;
235 } split;
236 unsigned int full;
237 };
238
239 struct x86_pmu_capability {
240 int version;
241 int num_counters_gp;
242 int num_counters_fixed;
243 int bit_width_gp;
244 int bit_width_fixed;
245 unsigned int events_mask;
246 int events_mask_len;
247 unsigned int pebs_ept :1;
248 };
249
250 /*
251 * Fixed-purpose performance events:
252 */
253
254 /* RDPMC offset for Fixed PMCs */
255 #define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30)
256 #define INTEL_PMC_FIXED_RDPMC_METRICS (1 << 29)
257
258 /*
259 * All the fixed-mode PMCs are configured via this single MSR:
260 */
261 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
262
263 /*
264 * There is no event-code assigned to the fixed-mode PMCs.
265 *
266 * For a fixed-mode PMC, which has an equivalent event on a general-purpose
267 * PMC, the event-code of the equivalent event is used for the fixed-mode PMC,
268 * e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core.
269 *
270 * For a fixed-mode PMC, which doesn't have an equivalent event, a
271 * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS.
272 * The pseudo event-code for a fixed-mode PMC must be 0x00.
273 * The pseudo umask-code is 0xX. The X equals the index of the fixed
274 * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
275 *
276 * The counts are available in separate MSRs:
277 */
278
279 /* Instr_Retired.Any: */
280 #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
281 #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
282
283 /* CPU_CLK_Unhalted.Core: */
284 #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
285 #define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
286
287 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
288 #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
289 #define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
290 #define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
291
292 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
293 #define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c
294 #define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
295 #define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
296
use_fixed_pseudo_encoding(u64 code)297 static inline bool use_fixed_pseudo_encoding(u64 code)
298 {
299 return !(code & 0xff);
300 }
301
302 /*
303 * We model BTS tracing as another fixed-mode PMC.
304 *
305 * We choose the value 47 for the fixed index of BTS, since lower
306 * values are used by actual fixed events and higher values are used
307 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
308 */
309 #define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)
310
311 /*
312 * The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for
313 * each TopDown metric event.
314 *
315 * Internally the TopDown metric events are mapped to the FxCtr 3 (SLOTS).
316 */
317 #define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16)
318 #define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0)
319 #define INTEL_PMC_IDX_TD_BAD_SPEC (INTEL_PMC_IDX_METRIC_BASE + 1)
320 #define INTEL_PMC_IDX_TD_FE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 2)
321 #define INTEL_PMC_IDX_TD_BE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 3)
322 #define INTEL_PMC_IDX_TD_HEAVY_OPS (INTEL_PMC_IDX_METRIC_BASE + 4)
323 #define INTEL_PMC_IDX_TD_BR_MISPREDICT (INTEL_PMC_IDX_METRIC_BASE + 5)
324 #define INTEL_PMC_IDX_TD_FETCH_LAT (INTEL_PMC_IDX_METRIC_BASE + 6)
325 #define INTEL_PMC_IDX_TD_MEM_BOUND (INTEL_PMC_IDX_METRIC_BASE + 7)
326 #define INTEL_PMC_IDX_METRIC_END INTEL_PMC_IDX_TD_MEM_BOUND
327 #define INTEL_PMC_MSK_TOPDOWN ((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \
328 INTEL_PMC_MSK_FIXED_SLOTS)
329
330 /*
331 * There is no event-code assigned to the TopDown events.
332 *
333 * For the slots event, use the pseudo code of the fixed counter 3.
334 *
335 * For the metric events, the pseudo event-code is 0x00.
336 * The pseudo umask-code starts from the middle of the pseudo event
337 * space, 0x80.
338 */
339 #define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */
340 /* Level 1 metrics */
341 #define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */
342 #define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */
343 #define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */
344 #define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */
345 /* Level 2 metrics */
346 #define INTEL_TD_METRIC_HEAVY_OPS 0x8400 /* Heavy Operations metric */
347 #define INTEL_TD_METRIC_BR_MISPREDICT 0x8500 /* Branch Mispredict metric */
348 #define INTEL_TD_METRIC_FETCH_LAT 0x8600 /* Fetch Latency metric */
349 #define INTEL_TD_METRIC_MEM_BOUND 0x8700 /* Memory bound metric */
350
351 #define INTEL_TD_METRIC_MAX INTEL_TD_METRIC_MEM_BOUND
352 #define INTEL_TD_METRIC_NUM 8
353
is_metric_idx(int idx)354 static inline bool is_metric_idx(int idx)
355 {
356 return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM;
357 }
358
is_topdown_idx(int idx)359 static inline bool is_topdown_idx(int idx)
360 {
361 return is_metric_idx(idx) || idx == INTEL_PMC_IDX_FIXED_SLOTS;
362 }
363
364 #define INTEL_PMC_OTHER_TOPDOWN_BITS(bit) \
365 (~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
366
367 #define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
368 #define GLOBAL_STATUS_BUFFER_OVF_BIT 62
369 #define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT)
370 #define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
371 #define GLOBAL_STATUS_ASIF BIT_ULL(60)
372 #define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
373 #define GLOBAL_STATUS_LBRS_FROZEN_BIT 58
374 #define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
375 #define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55
376 #define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)
377 #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48
378
379 #define GLOBAL_CTRL_EN_PERF_METRICS 48
380 /*
381 * We model guest LBR event tracing as another fixed-mode PMC like BTS.
382 *
383 * We choose bit 58 because it's used to indicate LBR stack frozen state
384 * for architectural perfmon v4, also we unconditionally mask that bit in
385 * the handle_pmi_common(), so it'll never be set in the overflow handling.
386 *
387 * With this fake counter assigned, the guest LBR event user (such as KVM),
388 * can program the LBR registers on its own, and we don't actually do anything
389 * with then in the host context.
390 */
391 #define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT)
392
393 /*
394 * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
395 * since it would claim bit 58 which is effectively Fixed26.
396 */
397 #define INTEL_FIXED_VLBR_EVENT 0x1b00
398
399 /*
400 * Adaptive PEBS v4
401 */
402
403 struct pebs_basic {
404 u64 format_size;
405 u64 ip;
406 u64 applicable_counters;
407 u64 tsc;
408 };
409
410 struct pebs_meminfo {
411 u64 address;
412 u64 aux;
413 u64 latency;
414 u64 tsx_tuning;
415 };
416
417 struct pebs_gprs {
418 u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
419 u64 r8, r9, r10, r11, r12, r13, r14, r15;
420 };
421
422 struct pebs_xmm {
423 u64 xmm[16*2]; /* two entries for each register */
424 };
425
426 /*
427 * AMD Extended Performance Monitoring and Debug cpuid feature detection
428 */
429 #define EXT_PERFMON_DEBUG_FEATURES 0x80000022
430
431 /*
432 * IBS cpuid feature detection
433 */
434
435 #define IBS_CPUID_FEATURES 0x8000001b
436
437 /*
438 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
439 * bit 0 is used to indicate the existence of IBS.
440 */
441 #define IBS_CAPS_AVAIL (1U<<0)
442 #define IBS_CAPS_FETCHSAM (1U<<1)
443 #define IBS_CAPS_OPSAM (1U<<2)
444 #define IBS_CAPS_RDWROPCNT (1U<<3)
445 #define IBS_CAPS_OPCNT (1U<<4)
446 #define IBS_CAPS_BRNTRGT (1U<<5)
447 #define IBS_CAPS_OPCNTEXT (1U<<6)
448 #define IBS_CAPS_RIPINVALIDCHK (1U<<7)
449 #define IBS_CAPS_OPBRNFUSE (1U<<8)
450 #define IBS_CAPS_FETCHCTLEXTD (1U<<9)
451 #define IBS_CAPS_OPDATA4 (1U<<10)
452 #define IBS_CAPS_ZEN4 (1U<<11)
453
454 #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
455 | IBS_CAPS_FETCHSAM \
456 | IBS_CAPS_OPSAM)
457
458 /*
459 * IBS APIC setup
460 */
461 #define IBSCTL 0x1cc
462 #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
463 #define IBSCTL_LVT_OFFSET_MASK 0x0F
464
465 /* IBS fetch bits/masks */
466 #define IBS_FETCH_L3MISSONLY (1ULL<<59)
467 #define IBS_FETCH_RAND_EN (1ULL<<57)
468 #define IBS_FETCH_VAL (1ULL<<49)
469 #define IBS_FETCH_ENABLE (1ULL<<48)
470 #define IBS_FETCH_CNT 0xFFFF0000ULL
471 #define IBS_FETCH_MAX_CNT 0x0000FFFFULL
472
473 /*
474 * IBS op bits/masks
475 * The lower 7 bits of the current count are random bits
476 * preloaded by hardware and ignored in software
477 */
478 #define IBS_OP_CUR_CNT (0xFFF80ULL<<32)
479 #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32)
480 #define IBS_OP_CNT_CTL (1ULL<<19)
481 #define IBS_OP_VAL (1ULL<<18)
482 #define IBS_OP_ENABLE (1ULL<<17)
483 #define IBS_OP_L3MISSONLY (1ULL<<16)
484 #define IBS_OP_MAX_CNT 0x0000FFFFULL
485 #define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
486 #define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20) /* separate upper 7 bits */
487 #define IBS_RIP_INVALID (1ULL<<38)
488
489 #ifdef CONFIG_X86_LOCAL_APIC
490 extern u32 get_ibs_caps(void);
491 extern int forward_event_to_ibs(struct perf_event *event);
492 #else
get_ibs_caps(void)493 static inline u32 get_ibs_caps(void) { return 0; }
forward_event_to_ibs(struct perf_event * event)494 static inline int forward_event_to_ibs(struct perf_event *event) { return -ENOENT; }
495 #endif
496
497 #ifdef CONFIG_PERF_EVENTS
498 extern void perf_events_lapic_init(void);
499
500 /*
501 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
502 * unused and ABI specified to be 0, so nobody should care what we do with
503 * them.
504 *
505 * EXACT - the IP points to the exact instruction that triggered the
506 * event (HW bugs exempt).
507 * VM - original X86_VM_MASK; see set_linear_ip().
508 */
509 #define PERF_EFLAGS_EXACT (1UL << 3)
510 #define PERF_EFLAGS_VM (1UL << 5)
511
512 struct pt_regs;
513 struct x86_perf_regs {
514 struct pt_regs regs;
515 u64 *xmm_regs;
516 };
517
518 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
519 extern unsigned long perf_misc_flags(struct pt_regs *regs);
520 #define perf_misc_flags(regs) perf_misc_flags(regs)
521
522 #include <asm/stacktrace.h>
523
524 /*
525 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
526 * and the comment with PERF_EFLAGS_EXACT.
527 */
528 #define perf_arch_fetch_caller_regs(regs, __ip) { \
529 (regs)->ip = (__ip); \
530 (regs)->sp = (unsigned long)__builtin_frame_address(0); \
531 (regs)->cs = __KERNEL_CS; \
532 regs->flags = 0; \
533 }
534
535 struct perf_guest_switch_msr {
536 unsigned msr;
537 u64 host, guest;
538 };
539
540 struct x86_pmu_lbr {
541 unsigned int nr;
542 unsigned int from;
543 unsigned int to;
544 unsigned int info;
545 };
546
547 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
548 extern u64 perf_get_hw_event_config(int hw_event);
549 extern void perf_check_microcode(void);
550 extern void perf_clear_dirty_counters(void);
551 extern int x86_perf_rdpmc_index(struct perf_event *event);
552 #else
perf_get_x86_pmu_capability(struct x86_pmu_capability * cap)553 static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
554 {
555 memset(cap, 0, sizeof(*cap));
556 }
557
perf_get_hw_event_config(int hw_event)558 static inline u64 perf_get_hw_event_config(int hw_event)
559 {
560 return 0;
561 }
562
perf_events_lapic_init(void)563 static inline void perf_events_lapic_init(void) { }
perf_check_microcode(void)564 static inline void perf_check_microcode(void) { }
565 #endif
566
567 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
568 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data);
569 extern void x86_perf_get_lbr(struct x86_pmu_lbr *lbr);
570 #else
571 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data);
x86_perf_get_lbr(struct x86_pmu_lbr * lbr)572 static inline void x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
573 {
574 memset(lbr, 0, sizeof(*lbr));
575 }
576 #endif
577
578 #ifdef CONFIG_CPU_SUP_INTEL
579 extern void intel_pt_handle_vmx(int on);
580 #else
intel_pt_handle_vmx(int on)581 static inline void intel_pt_handle_vmx(int on)
582 {
583
584 }
585 #endif
586
587 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
588 extern void amd_pmu_enable_virt(void);
589 extern void amd_pmu_disable_virt(void);
590
591 #if defined(CONFIG_PERF_EVENTS_AMD_BRS)
592
593 #define PERF_NEEDS_LOPWR_CB 1
594
595 /*
596 * architectural low power callback impacts
597 * drivers/acpi/processor_idle.c
598 * drivers/acpi/acpi_pad.c
599 */
600 extern void perf_amd_brs_lopwr_cb(bool lopwr_in);
601
602 DECLARE_STATIC_CALL(perf_lopwr_cb, perf_amd_brs_lopwr_cb);
603
perf_lopwr_cb(bool lopwr_in)604 static __always_inline void perf_lopwr_cb(bool lopwr_in)
605 {
606 static_call_mod(perf_lopwr_cb)(lopwr_in);
607 }
608
609 #endif /* PERF_NEEDS_LOPWR_CB */
610
611 #else
amd_pmu_enable_virt(void)612 static inline void amd_pmu_enable_virt(void) { }
amd_pmu_disable_virt(void)613 static inline void amd_pmu_disable_virt(void) { }
614 #endif
615
616 #define arch_perf_out_copy_user copy_from_user_nmi
617
618 #endif /* _ASM_X86_PERF_EVENT_H */
619