1 #ifndef _ASM_X86_ACPI_H
2 #define _ASM_X86_ACPI_H
3
4 /*
5 * Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 * Copyright (C) 2001 Patrick Mochel <mochel@osdl.org>
7 *
8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
25 */
26 #include <acpi/pdc_intel.h>
27
28 #include <asm/numa.h>
29 #include <asm/processor.h>
30 #include <asm/mmu.h>
31 #include <asm/mpspec.h>
32 #include <asm/trampoline.h>
33
34 #define COMPILER_DEPENDENT_INT64 long long
35 #define COMPILER_DEPENDENT_UINT64 unsigned long long
36
37 /*
38 * Calling conventions:
39 *
40 * ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads)
41 * ACPI_EXTERNAL_XFACE - External ACPI interfaces
42 * ACPI_INTERNAL_XFACE - Internal ACPI interfaces
43 * ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces
44 */
45 #define ACPI_SYSTEM_XFACE
46 #define ACPI_EXTERNAL_XFACE
47 #define ACPI_INTERNAL_XFACE
48 #define ACPI_INTERNAL_VAR_XFACE
49
50 /* Asm macros */
51
52 #define ACPI_ASM_MACROS
53 #define BREAKPOINT3
54 #define ACPI_DISABLE_IRQS() local_irq_disable()
55 #define ACPI_ENABLE_IRQS() local_irq_enable()
56 #define ACPI_FLUSH_CPU_CACHE() wbinvd()
57
58 int __acpi_acquire_global_lock(unsigned int *lock);
59 int __acpi_release_global_lock(unsigned int *lock);
60
61 #define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \
62 ((Acq) = __acpi_acquire_global_lock(&facs->global_lock))
63
64 #define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \
65 ((Acq) = __acpi_release_global_lock(&facs->global_lock))
66
67 /*
68 * Math helper asm macros
69 */
70 #define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \
71 asm("divl %2;" \
72 : "=a"(q32), "=d"(r32) \
73 : "r"(d32), \
74 "0"(n_lo), "1"(n_hi))
75
76
77 #define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \
78 asm("shrl $1,%2 ;" \
79 "rcrl $1,%3;" \
80 : "=r"(n_hi), "=r"(n_lo) \
81 : "0"(n_hi), "1"(n_lo))
82
83 #ifdef CONFIG_ACPI
84 extern int acpi_lapic;
85 extern int acpi_ioapic;
86 extern int acpi_noirq;
87 extern int acpi_strict;
88 extern int acpi_disabled;
89 extern int acpi_pci_disabled;
90 extern int acpi_skip_timer_override;
91 extern int acpi_use_timer_override;
92 extern int acpi_fix_pin2_polarity;
93
94 extern u8 acpi_sci_flags;
95 extern int acpi_sci_override_gsi;
96 void acpi_pic_sci_set_trigger(unsigned int, u16);
97
98 extern int (*__acpi_register_gsi)(struct device *dev, u32 gsi,
99 int trigger, int polarity);
100
disable_acpi(void)101 static inline void disable_acpi(void)
102 {
103 acpi_disabled = 1;
104 acpi_pci_disabled = 1;
105 acpi_noirq = 1;
106 }
107
108 extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq);
109
acpi_noirq_set(void)110 static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
acpi_disable_pci(void)111 static inline void acpi_disable_pci(void)
112 {
113 acpi_pci_disabled = 1;
114 acpi_noirq_set();
115 }
116
117 /* Low-level suspend routine. */
118 extern int acpi_suspend_lowlevel(void);
119
120 extern const unsigned char acpi_wakeup_code[];
121 #define acpi_wakeup_address (__pa(TRAMPOLINE_SYM(acpi_wakeup_code)))
122
123 /* early initialization routine */
124 extern void acpi_reserve_wakeup_memory(void);
125
126 /*
127 * Check if the CPU can handle C2 and deeper
128 */
acpi_processor_cstate_check(unsigned int max_cstate)129 static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
130 {
131 /*
132 * Early models (<=5) of AMD Opterons are not supposed to go into
133 * C2 state.
134 *
135 * Steppings 0x0A and later are good
136 */
137 if (boot_cpu_data.x86 == 0x0F &&
138 boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
139 boot_cpu_data.x86_model <= 0x05 &&
140 boot_cpu_data.x86_mask < 0x0A)
141 return 1;
142 else if (c1e_detected)
143 return 1;
144 else
145 return max_cstate;
146 }
147
arch_has_acpi_pdc(void)148 static inline bool arch_has_acpi_pdc(void)
149 {
150 struct cpuinfo_x86 *c = &cpu_data(0);
151 return (c->x86_vendor == X86_VENDOR_INTEL ||
152 c->x86_vendor == X86_VENDOR_CENTAUR);
153 }
154
arch_acpi_set_pdc_bits(u32 * buf)155 static inline void arch_acpi_set_pdc_bits(u32 *buf)
156 {
157 struct cpuinfo_x86 *c = &cpu_data(0);
158
159 buf[2] |= ACPI_PDC_C_CAPABILITY_SMP;
160
161 if (cpu_has(c, X86_FEATURE_EST))
162 buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP;
163
164 if (cpu_has(c, X86_FEATURE_ACPI))
165 buf[2] |= ACPI_PDC_T_FFH;
166
167 /*
168 * If mwait/monitor is unsupported, C2/C3_FFH will be disabled
169 */
170 if (!cpu_has(c, X86_FEATURE_MWAIT))
171 buf[2] &= ~(ACPI_PDC_C_C2C3_FFH);
172 }
173
174 #else /* !CONFIG_ACPI */
175
176 #define acpi_lapic 0
177 #define acpi_ioapic 0
acpi_noirq_set(void)178 static inline void acpi_noirq_set(void) { }
acpi_disable_pci(void)179 static inline void acpi_disable_pci(void) { }
disable_acpi(void)180 static inline void disable_acpi(void) { }
181
182 #endif /* !CONFIG_ACPI */
183
184 #define ARCH_HAS_POWER_INIT 1
185
186 struct bootnode;
187
188 #ifdef CONFIG_ACPI_NUMA
189 extern int acpi_numa;
190 extern int x86_acpi_numa_init(void);
191 #endif /* CONFIG_ACPI_NUMA */
192
193 #define acpi_unlazy_tlb(x) leave_mm(x)
194
195 #endif /* _ASM_X86_ACPI_H */
196