1 /*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #ifndef _ATH5K_H
19 #define _ATH5K_H
20
21 /* TODO: Clean up channel debugging (doesn't work anyway) and start
22 * working on reg. control code using all available eeprom information
23 * (rev. engineering needed) */
24 #define CHAN_DEBUG 0
25
26 #include <linux/io.h>
27 #include <linux/interrupt.h>
28 #include <linux/types.h>
29 #include <linux/average.h>
30 #include <linux/leds.h>
31 #include <net/mac80211.h>
32
33 /* RX/TX descriptor hw structs
34 * TODO: Driver part should only see sw structs */
35 #include "desc.h"
36
37 /* EEPROM structs/offsets
38 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
39 * and clean up common bits, then introduce set/get functions in eeprom.c */
40 #include "eeprom.h"
41 #include "debug.h"
42 #include "../ath.h"
43 #include "ani.h"
44
45 /* PCI IDs */
46 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
47 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
48 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
49 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
50 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
51 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
52 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
53 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
54 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
55 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
56 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
57 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
58 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
59 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
60 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
61 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
62 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
63 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
64 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
65 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
66 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
67 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
68 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
69 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
70 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
71 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
72 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
73 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
74
75 /****************************\
76 GENERIC DRIVER DEFINITIONS
77 \****************************/
78
79 #define ATH5K_PRINTF(fmt, ...) \
80 printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__)
81
82 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
83 printk(_level "ath5k %s: " _fmt, \
84 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
85 ##__VA_ARGS__)
86
87 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
88 if (net_ratelimit()) \
89 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
90 } while (0)
91
92 #define ATH5K_INFO(_sc, _fmt, ...) \
93 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
94
95 #define ATH5K_WARN(_sc, _fmt, ...) \
96 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
97
98 #define ATH5K_ERR(_sc, _fmt, ...) \
99 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
100
101 /*
102 * AR5K REGISTER ACCESS
103 */
104
105 /* Some macros to read/write fields */
106
107 /* First shift, then mask */
108 #define AR5K_REG_SM(_val, _flags) \
109 (((_val) << _flags##_S) & (_flags))
110
111 /* First mask, then shift */
112 #define AR5K_REG_MS(_val, _flags) \
113 (((_val) & (_flags)) >> _flags##_S)
114
115 /* Some registers can hold multiple values of interest. For this
116 * reason when we want to write to these registers we must first
117 * retrieve the values which we do not want to clear (lets call this
118 * old_data) and then set the register with this and our new_value:
119 * ( old_data | new_value) */
120 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
121 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
122 (((_val) << _flags##_S) & (_flags)), _reg)
123
124 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
126 (_mask)) | (_flags), _reg)
127
128 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
129 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
130
131 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
132 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
133
134 /* Access QCU registers per queue */
135 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
136 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
137
138 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
139 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
140
141 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
142 _reg |= 1 << _queue; \
143 } while (0)
144
145 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
146 _reg &= ~(1 << _queue); \
147 } while (0)
148
149 /* Used while writing initvals */
150 #define AR5K_REG_WAIT(_i) do { \
151 if (_i % 64) \
152 udelay(1); \
153 } while (0)
154
155 /*
156 * Some tunable values (these should be changeable by the user)
157 * TODO: Make use of them and add more options OR use debug/configfs
158 */
159 #define AR5K_TUNE_DMA_BEACON_RESP 2
160 #define AR5K_TUNE_SW_BEACON_RESP 10
161 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
162 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
163 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
164 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
165 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
166 * be the max value. */
167 #define AR5K_TUNE_RSSI_THRES 129
168 /* This must be set when setting the RSSI threshold otherwise it can
169 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
170 * the BMISS_THRES will be seen as 0, seems hardware doesn't keep
171 * track of it. Max value depends on hardware. For AR5210 this is just 7.
172 * For AR5211+ this seems to be up to 255. */
173 #define AR5K_TUNE_BMISS_THRES 7
174 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
175 #define AR5K_TUNE_BEACON_INTERVAL 100
176 #define AR5K_TUNE_AIFS 2
177 #define AR5K_TUNE_AIFS_11B 2
178 #define AR5K_TUNE_AIFS_XR 0
179 #define AR5K_TUNE_CWMIN 15
180 #define AR5K_TUNE_CWMIN_11B 31
181 #define AR5K_TUNE_CWMIN_XR 3
182 #define AR5K_TUNE_CWMAX 1023
183 #define AR5K_TUNE_CWMAX_11B 1023
184 #define AR5K_TUNE_CWMAX_XR 7
185 #define AR5K_TUNE_NOISE_FLOOR -72
186 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
187 #define AR5K_TUNE_MAX_TXPOWER 63
188 #define AR5K_TUNE_DEFAULT_TXPOWER 25
189 #define AR5K_TUNE_TPC_TXPOWER false
190 #define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 60000 /* 60 sec */
191 #define ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT 10000 /* 10 sec */
192 #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */
193 #define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */
194
195 #define AR5K_INIT_CARR_SENSE_EN 1
196
197 /*Swap RX/TX Descriptor for big endian archs*/
198 #if defined(__BIG_ENDIAN)
199 #define AR5K_INIT_CFG ( \
200 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
201 )
202 #else
203 #define AR5K_INIT_CFG 0x00000000
204 #endif
205
206 /* Initial values */
207 #define AR5K_INIT_CYCRSSI_THR1 2
208
209 /* Tx retry limit defaults from standard */
210 #define AR5K_INIT_RETRY_SHORT 7
211 #define AR5K_INIT_RETRY_LONG 4
212
213 /* Slot time */
214 #define AR5K_INIT_SLOT_TIME_TURBO 6
215 #define AR5K_INIT_SLOT_TIME_DEFAULT 9
216 #define AR5K_INIT_SLOT_TIME_HALF_RATE 13
217 #define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21
218 #define AR5K_INIT_SLOT_TIME_B 20
219 #define AR5K_SLOT_TIME_MAX 0xffff
220
221 /* SIFS */
222 #define AR5K_INIT_SIFS_TURBO 6
223 #define AR5K_INIT_SIFS_DEFAULT_BG 10
224 #define AR5K_INIT_SIFS_DEFAULT_A 16
225 #define AR5K_INIT_SIFS_HALF_RATE 32
226 #define AR5K_INIT_SIFS_QUARTER_RATE 64
227
228 /* Used to calculate tx time for non 5/10/40MHz
229 * operation */
230 /* It's preamble time + signal time (16 + 4) */
231 #define AR5K_INIT_OFDM_PREAMPLE_TIME 20
232 /* Preamble time for 40MHz (turbo) operation (min ?) */
233 #define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14
234 #define AR5K_INIT_OFDM_SYMBOL_TIME 4
235 #define AR5K_INIT_OFDM_PLCP_BITS 22
236
237 /* Rx latency for 5 and 10MHz operation (max ?) */
238 #define AR5K_INIT_RX_LAT_MAX 63
239 /* Tx latencies from initvals (5212 only but no problem
240 * because we only tweak them on 5212) */
241 #define AR5K_INIT_TX_LAT_A 54
242 #define AR5K_INIT_TX_LAT_BG 384
243 /* Tx latency for 40MHz (turbo) operation (min ?) */
244 #define AR5K_INIT_TX_LAT_MIN 32
245 /* Default Tx/Rx latencies (same for 5211)*/
246 #define AR5K_INIT_TX_LATENCY_5210 54
247 #define AR5K_INIT_RX_LATENCY_5210 29
248
249 /* Tx frame to Tx data start delay */
250 #define AR5K_INIT_TXF2TXD_START_DEFAULT 14
251 #define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12
252 #define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13
253
254 /* We need to increase PHY switch and agc settling time
255 * on turbo mode */
256 #define AR5K_SWITCH_SETTLING 5760
257 #define AR5K_SWITCH_SETTLING_TURBO 7168
258
259 #define AR5K_AGC_SETTLING 28
260 /* 38 on 5210 but shouldn't matter */
261 #define AR5K_AGC_SETTLING_TURBO 37
262
263
264
265 /*****************************\
266 * GENERIC CHIPSET DEFINITIONS *
267 \*****************************/
268
269 /**
270 * enum ath5k_version - MAC Chips
271 * @AR5K_AR5210: AR5210 (Crete)
272 * @AR5K_AR5211: AR5211 (Oahu/Maui)
273 * @AR5K_AR5212: AR5212 (Venice) and newer
274 */
275 enum ath5k_version {
276 AR5K_AR5210 = 0,
277 AR5K_AR5211 = 1,
278 AR5K_AR5212 = 2,
279 };
280
281 /**
282 * enum ath5k_radio - PHY Chips
283 * @AR5K_RF5110: RF5110 (Fez)
284 * @AR5K_RF5111: RF5111 (Sombrero)
285 * @AR5K_RF5112: RF2112/5112(A) (Derby/Derby2)
286 * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite)
287 * @AR5K_RF5413: RF5413/5414/5424 (Eagle/Condor)
288 * @AR5K_RF2316: RF2315/2316 (Cobra SoC)
289 * @AR5K_RF2317: RF2317 (Spider SoC)
290 * @AR5K_RF2425: RF2425/2417 (Swan/Nalla)
291 */
292 enum ath5k_radio {
293 AR5K_RF5110 = 0,
294 AR5K_RF5111 = 1,
295 AR5K_RF5112 = 2,
296 AR5K_RF2413 = 3,
297 AR5K_RF5413 = 4,
298 AR5K_RF2316 = 5,
299 AR5K_RF2317 = 6,
300 AR5K_RF2425 = 7,
301 };
302
303 /*
304 * Common silicon revision/version values
305 */
306
307 #define AR5K_SREV_UNKNOWN 0xffff
308
309 #define AR5K_SREV_AR5210 0x00 /* Crete */
310 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */
311 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
312 #define AR5K_SREV_AR5311B 0x30 /* Spirit */
313 #define AR5K_SREV_AR5211 0x40 /* Oahu */
314 #define AR5K_SREV_AR5212 0x50 /* Venice */
315 #define AR5K_SREV_AR5312_R2 0x52 /* AP31 */
316 #define AR5K_SREV_AR5212_V4 0x54 /* ??? */
317 #define AR5K_SREV_AR5213 0x55 /* ??? */
318 #define AR5K_SREV_AR5312_R7 0x57 /* AP30 */
319 #define AR5K_SREV_AR2313_R8 0x58 /* AP43 */
320 #define AR5K_SREV_AR5213A 0x59 /* Hainan */
321 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */
322 #define AR5K_SREV_AR2414 0x70 /* Griffin */
323 #define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
324 #define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
325 #define AR5K_SREV_AR5424 0x90 /* Condor */
326 #define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
327 #define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
328 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
329 #define AR5K_SREV_AR5414 0xa0 /* Eagle */
330 #define AR5K_SREV_AR2415 0xb0 /* Talon */
331 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
332 #define AR5K_SREV_AR5418 0xca /* PCI-E */
333 #define AR5K_SREV_AR2425 0xe0 /* Swan */
334 #define AR5K_SREV_AR2417 0xf0 /* Nala */
335
336 #define AR5K_SREV_RAD_5110 0x00
337 #define AR5K_SREV_RAD_5111 0x10
338 #define AR5K_SREV_RAD_5111A 0x15
339 #define AR5K_SREV_RAD_2111 0x20
340 #define AR5K_SREV_RAD_5112 0x30
341 #define AR5K_SREV_RAD_5112A 0x35
342 #define AR5K_SREV_RAD_5112B 0x36
343 #define AR5K_SREV_RAD_2112 0x40
344 #define AR5K_SREV_RAD_2112A 0x45
345 #define AR5K_SREV_RAD_2112B 0x46
346 #define AR5K_SREV_RAD_2413 0x50
347 #define AR5K_SREV_RAD_5413 0x60
348 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
349 #define AR5K_SREV_RAD_2317 0x80
350 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
351 #define AR5K_SREV_RAD_2425 0xa2
352 #define AR5K_SREV_RAD_5133 0xc0
353
354 #define AR5K_SREV_PHY_5211 0x30
355 #define AR5K_SREV_PHY_5212 0x41
356 #define AR5K_SREV_PHY_5212A 0x42
357 #define AR5K_SREV_PHY_5212B 0x43
358 #define AR5K_SREV_PHY_2413 0x45
359 #define AR5K_SREV_PHY_5413 0x61
360 #define AR5K_SREV_PHY_2425 0x70
361
362 /* TODO add support to mac80211 for vendor-specific rates and modes */
363
364 /**
365 * DOC: Atheros XR
366 *
367 * Some of this information is based on Documentation from:
368 *
369 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
370 *
371 * Atheros' eXtended Range - range enhancing extension is a modulation scheme
372 * that is supposed to double the link distance between an Atheros XR-enabled
373 * client device with an Atheros XR-enabled access point. This is achieved
374 * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB
375 * above what the 802.11 specifications demand. In addition, new (proprietary)
376 * data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
377 *
378 * Please note that can you either use XR or TURBO but you cannot use both,
379 * they are exclusive.
380 *
381 * Also note that we do not plan to support XR mode at least for now. You can
382 * get a mode similar to XR by using 5MHz bwmode.
383 */
384
385
386 /**
387 * DOC: Atheros SuperAG
388 *
389 * In addition to XR we have another modulation scheme called TURBO mode
390 * that is supposed to provide a throughput transmission speed up to 40Mbit/s
391 * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two
392 * 54Mbit/s 802.11g channels. To use this feature both ends must support it.
393 * There is also a distinction between "static" and "dynamic" turbo modes:
394 *
395 * - Static: is the dumb version: devices set to this mode stick to it until
396 * the mode is turned off.
397 *
398 * - Dynamic: is the intelligent version, the network decides itself if it
399 * is ok to use turbo. As soon as traffic is detected on adjacent channels
400 * (which would get used in turbo mode), or when a non-turbo station joins
401 * the network, turbo mode won't be used until the situation changes again.
402 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
403 * monitors the used radio band in order to decide whether turbo mode may
404 * be used or not.
405 *
406 * This article claims Super G sticks to bonding of channels 5 and 6 for
407 * USA:
408 *
409 * http://www.pcworld.com/article/id,113428-page,1/article.html
410 *
411 * The channel bonding seems to be driver specific though.
412 *
413 * In addition to TURBO modes we also have the following features for even
414 * greater speed-up:
415 *
416 * - Bursting: allows multiple frames to be sent at once, rather than pausing
417 * after each frame. Bursting is a standards-compliant feature that can be
418 * used with any Access Point.
419 *
420 * - Fast frames: increases the amount of information that can be sent per
421 * frame, also resulting in a reduction of transmission overhead. It is a
422 * proprietary feature that needs to be supported by the Access Point.
423 *
424 * - Compression: data frames are compressed in real time using a Lempel Ziv
425 * algorithm. This is done transparently. Once this feature is enabled,
426 * compression and decompression takes place inside the chipset, without
427 * putting additional load on the host CPU.
428 *
429 * As with XR we also don't plan to support SuperAG features for now. You can
430 * get a mode similar to TURBO by using 40MHz bwmode.
431 */
432
433
434 /**
435 * enum ath5k_driver_mode - PHY operation mode
436 * @AR5K_MODE_11A: 802.11a
437 * @AR5K_MODE_11B: 802.11b
438 * @AR5K_MODE_11G: 801.11g
439 * @AR5K_MODE_MAX: Used for boundary checks
440 *
441 * Do not change the order here, we use these as
442 * array indices and it also maps EEPROM structures.
443 */
444 enum ath5k_driver_mode {
445 AR5K_MODE_11A = 0,
446 AR5K_MODE_11B = 1,
447 AR5K_MODE_11G = 2,
448 AR5K_MODE_MAX = 3
449 };
450
451 /**
452 * enum ath5k_ant_mode - Antenna operation mode
453 * @AR5K_ANTMODE_DEFAULT: Default antenna setup
454 * @AR5K_ANTMODE_FIXED_A: Only antenna A is present
455 * @AR5K_ANTMODE_FIXED_B: Only antenna B is present
456 * @AR5K_ANTMODE_SINGLE_AP: STA locked on a single ap
457 * @AR5K_ANTMODE_SECTOR_AP: AP with tx antenna set on tx desc
458 * @AR5K_ANTMODE_SECTOR_STA: STA with tx antenna set on tx desc
459 * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx-
460 * @AR5K_ANTMODE_MAX: Used for boundary checks
461 *
462 * For more infos on antenna control check out phy.c
463 */
464 enum ath5k_ant_mode {
465 AR5K_ANTMODE_DEFAULT = 0,
466 AR5K_ANTMODE_FIXED_A = 1,
467 AR5K_ANTMODE_FIXED_B = 2,
468 AR5K_ANTMODE_SINGLE_AP = 3,
469 AR5K_ANTMODE_SECTOR_AP = 4,
470 AR5K_ANTMODE_SECTOR_STA = 5,
471 AR5K_ANTMODE_DEBUG = 6,
472 AR5K_ANTMODE_MAX,
473 };
474
475 /**
476 * enum ath5k_bw_mode - Bandwidth operation mode
477 * @AR5K_BWMODE_DEFAULT: 20MHz, default operation
478 * @AR5K_BWMODE_5MHZ: Quarter rate
479 * @AR5K_BWMODE_10MHZ: Half rate
480 * @AR5K_BWMODE_40MHZ: Turbo
481 */
482 enum ath5k_bw_mode {
483 AR5K_BWMODE_DEFAULT = 0,
484 AR5K_BWMODE_5MHZ = 1,
485 AR5K_BWMODE_10MHZ = 2,
486 AR5K_BWMODE_40MHZ = 3
487 };
488
489
490
491 /****************\
492 TX DEFINITIONS
493 \****************/
494
495 /**
496 * struct ath5k_tx_status - TX Status descriptor
497 * @ts_seqnum: Sequence number
498 * @ts_tstamp: Timestamp
499 * @ts_status: Status code
500 * @ts_final_idx: Final transmission series index
501 * @ts_final_retry: Final retry count
502 * @ts_rssi: RSSI for received ACK
503 * @ts_shortretry: Short retry count
504 * @ts_virtcol: Virtual collision count
505 * @ts_antenna: Antenna used
506 *
507 * TX status descriptor gets filled by the hw
508 * on each transmission attempt.
509 */
510 struct ath5k_tx_status {
511 u16 ts_seqnum;
512 u16 ts_tstamp;
513 u8 ts_status;
514 u8 ts_final_idx;
515 u8 ts_final_retry;
516 s8 ts_rssi;
517 u8 ts_shortretry;
518 u8 ts_virtcol;
519 u8 ts_antenna;
520 };
521
522 #define AR5K_TXSTAT_ALTRATE 0x80
523 #define AR5K_TXERR_XRETRY 0x01
524 #define AR5K_TXERR_FILT 0x02
525 #define AR5K_TXERR_FIFO 0x04
526
527 /**
528 * enum ath5k_tx_queue - Queue types used to classify tx queues.
529 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
530 * @AR5K_TX_QUEUE_DATA: A normal data queue
531 * @AR5K_TX_QUEUE_BEACON: The beacon queue
532 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
533 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
534 */
535 enum ath5k_tx_queue {
536 AR5K_TX_QUEUE_INACTIVE = 0,
537 AR5K_TX_QUEUE_DATA,
538 AR5K_TX_QUEUE_BEACON,
539 AR5K_TX_QUEUE_CAB,
540 AR5K_TX_QUEUE_UAPSD,
541 };
542
543 #define AR5K_NUM_TX_QUEUES 10
544 #define AR5K_NUM_TX_QUEUES_NOQCU 2
545
546 /**
547 * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues
548 * @AR5K_WME_AC_BK: Background traffic
549 * @AR5K_WME_AC_BE: Best-effort (normal) traffic
550 * @AR5K_WME_AC_VI: Video traffic
551 * @AR5K_WME_AC_VO: Voice traffic
552 *
553 * These are the 4 Access Categories as defined in
554 * WME spec. 0 is the lowest priority and 4 is the
555 * highest. Normal data that hasn't been classified
556 * goes to the Best Effort AC.
557 */
558 enum ath5k_tx_queue_subtype {
559 AR5K_WME_AC_BK = 0,
560 AR5K_WME_AC_BE,
561 AR5K_WME_AC_VI,
562 AR5K_WME_AC_VO,
563 };
564
565 /**
566 * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions
567 * @AR5K_TX_QUEUE_ID_NOQCU_DATA: Data queue on AR5210 (no QCU available)
568 * @AR5K_TX_QUEUE_ID_NOQCU_BEACON: Beacon queue on AR5210 (no QCU available)
569 * @AR5K_TX_QUEUE_ID_DATA_MIN: Data queue min index
570 * @AR5K_TX_QUEUE_ID_DATA_MAX: Data queue max index
571 * @AR5K_TX_QUEUE_ID_CAB: Content after beacon queue
572 * @AR5K_TX_QUEUE_ID_BEACON: Beacon queue
573 * @AR5K_TX_QUEUE_ID_UAPSD: Urgent Automatic Power Save Delivery,
574 *
575 * Each number represents a hw queue. If hw does not support hw queues
576 * (eg 5210) all data goes in one queue.
577 */
578 enum ath5k_tx_queue_id {
579 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
580 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
581 AR5K_TX_QUEUE_ID_DATA_MIN = 0,
582 AR5K_TX_QUEUE_ID_DATA_MAX = 3,
583 AR5K_TX_QUEUE_ID_UAPSD = 7,
584 AR5K_TX_QUEUE_ID_CAB = 8,
585 AR5K_TX_QUEUE_ID_BEACON = 9,
586 };
587
588 /*
589 * Flags to set hw queue's parameters...
590 */
591 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
592 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
593 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
594 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
595 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
596 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
597 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
598 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
599 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
600 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
601 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
602 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
603 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
604 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
605
606 /**
607 * struct ath5k_txq - Transmit queue state
608 * @qnum: Hardware q number
609 * @link: Link ptr in last TX desc
610 * @q: Transmit queue (&struct list_head)
611 * @lock: Lock on q and link
612 * @setup: Is the queue configured
613 * @txq_len:Number of queued buffers
614 * @txq_max: Max allowed num of queued buffers
615 * @txq_poll_mark: Used to check if queue got stuck
616 * @txq_stuck: Queue stuck counter
617 *
618 * One of these exists for each hardware transmit queue.
619 * Packets sent to us from above are assigned to queues based
620 * on their priority. Not all devices support a complete set
621 * of hardware transmit queues. For those devices the array
622 * sc_ac2q will map multiple priorities to fewer hardware queues
623 * (typically all to one hardware queue).
624 */
625 struct ath5k_txq {
626 unsigned int qnum;
627 u32 *link;
628 struct list_head q;
629 spinlock_t lock;
630 bool setup;
631 int txq_len;
632 int txq_max;
633 bool txq_poll_mark;
634 unsigned int txq_stuck;
635 };
636
637 /**
638 * struct ath5k_txq_info - A struct to hold TX queue's parameters
639 * @tqi_type: One of enum ath5k_tx_queue
640 * @tqi_subtype: One of enum ath5k_tx_queue_subtype
641 * @tqi_flags: TX queue flags (see above)
642 * @tqi_aifs: Arbitrated Inter-frame Space
643 * @tqi_cw_min: Minimum Contention Window
644 * @tqi_cw_max: Maximum Contention Window
645 * @tqi_cbr_period: Constant bit rate period
646 * @tqi_ready_time: Time queue waits after an event when RDYTIME is enabled
647 */
648 struct ath5k_txq_info {
649 enum ath5k_tx_queue tqi_type;
650 enum ath5k_tx_queue_subtype tqi_subtype;
651 u16 tqi_flags;
652 u8 tqi_aifs;
653 u16 tqi_cw_min;
654 u16 tqi_cw_max;
655 u32 tqi_cbr_period;
656 u32 tqi_cbr_overflow_limit;
657 u32 tqi_burst_time;
658 u32 tqi_ready_time;
659 };
660
661 /**
662 * enum ath5k_pkt_type - Transmit packet types
663 * @AR5K_PKT_TYPE_NORMAL: Normal data
664 * @AR5K_PKT_TYPE_ATIM: ATIM
665 * @AR5K_PKT_TYPE_PSPOLL: PS-Poll
666 * @AR5K_PKT_TYPE_BEACON: Beacon
667 * @AR5K_PKT_TYPE_PROBE_RESP: Probe response
668 * @AR5K_PKT_TYPE_PIFS: PIFS
669 * Used on tx control descriptor
670 */
671 enum ath5k_pkt_type {
672 AR5K_PKT_TYPE_NORMAL = 0,
673 AR5K_PKT_TYPE_ATIM = 1,
674 AR5K_PKT_TYPE_PSPOLL = 2,
675 AR5K_PKT_TYPE_BEACON = 3,
676 AR5K_PKT_TYPE_PROBE_RESP = 4,
677 AR5K_PKT_TYPE_PIFS = 5,
678 };
679
680 /*
681 * TX power and TPC settings
682 */
683 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
684 ((0 & 1) << ((_v) + 6)) | \
685 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
686 )
687
688 #define AR5K_TXPOWER_CCK(_r, _v) ( \
689 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
690 )
691
692
693
694 /****************\
695 RX DEFINITIONS
696 \****************/
697
698 /**
699 * struct ath5k_rx_status - RX Status descriptor
700 * @rs_datalen: Data length
701 * @rs_tstamp: Timestamp
702 * @rs_status: Status code
703 * @rs_phyerr: PHY error mask
704 * @rs_rssi: RSSI in 0.5dbm units
705 * @rs_keyix: Index to the key used for decrypting
706 * @rs_rate: Rate used to decode the frame
707 * @rs_antenna: Antenna used to receive the frame
708 * @rs_more: Indicates this is a frame fragment (Fast frames)
709 */
710 struct ath5k_rx_status {
711 u16 rs_datalen;
712 u16 rs_tstamp;
713 u8 rs_status;
714 u8 rs_phyerr;
715 s8 rs_rssi;
716 u8 rs_keyix;
717 u8 rs_rate;
718 u8 rs_antenna;
719 u8 rs_more;
720 };
721
722 #define AR5K_RXERR_CRC 0x01
723 #define AR5K_RXERR_PHY 0x02
724 #define AR5K_RXERR_FIFO 0x04
725 #define AR5K_RXERR_DECRYPT 0x08
726 #define AR5K_RXERR_MIC 0x10
727 #define AR5K_RXKEYIX_INVALID ((u8) -1)
728 #define AR5K_TXKEYIX_INVALID ((u32) -1)
729
730
731 /**************************\
732 BEACON TIMERS DEFINITIONS
733 \**************************/
734
735 #define AR5K_BEACON_PERIOD 0x0000ffff
736 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
737 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
738
739
740 /*
741 * TSF to TU conversion:
742 *
743 * TSF is a 64bit value in usec (microseconds).
744 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
745 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
746 */
747 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
748
749
750
751 /*******************************\
752 GAIN OPTIMIZATION DEFINITIONS
753 \*******************************/
754
755 /**
756 * enum ath5k_rfgain - RF Gain optimization engine state
757 * @AR5K_RFGAIN_INACTIVE: Engine disabled
758 * @AR5K_RFGAIN_ACTIVE: Probe active
759 * @AR5K_RFGAIN_READ_REQUESTED: Probe requested
760 * @AR5K_RFGAIN_NEED_CHANGE: Gain_F needs change
761 */
762 enum ath5k_rfgain {
763 AR5K_RFGAIN_INACTIVE = 0,
764 AR5K_RFGAIN_ACTIVE,
765 AR5K_RFGAIN_READ_REQUESTED,
766 AR5K_RFGAIN_NEED_CHANGE,
767 };
768
769 /**
770 * struct ath5k_gain - RF Gain optimization engine state data
771 * @g_step_idx: Current step index
772 * @g_current: Current gain
773 * @g_target: Target gain
774 * @g_low: Low gain boundary
775 * @g_high: High gain boundary
776 * @g_f_corr: Gain_F correction
777 * @g_state: One of enum ath5k_rfgain
778 */
779 struct ath5k_gain {
780 u8 g_step_idx;
781 u8 g_current;
782 u8 g_target;
783 u8 g_low;
784 u8 g_high;
785 u8 g_f_corr;
786 u8 g_state;
787 };
788
789
790
791 /********************\
792 COMMON DEFINITIONS
793 \********************/
794
795 #define AR5K_SLOT_TIME_9 396
796 #define AR5K_SLOT_TIME_20 880
797 #define AR5K_SLOT_TIME_MAX 0xffff
798
799 /**
800 * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111
801 * @a2_flags: Channel flags (internal)
802 * @a2_athchan: HW channel number (internal)
803 *
804 * This structure is used to map 2GHz channels to
805 * 5GHz Atheros channels on 2111 frequency converter
806 * that comes together with RF5111
807 * TODO: Clean up
808 */
809 struct ath5k_athchan_2ghz {
810 u32 a2_flags;
811 u16 a2_athchan;
812 };
813
814 /**
815 * enum ath5k_dmasize - DMA size definitions (2^(n+2))
816 * @AR5K_DMASIZE_4B: 4Bytes
817 * @AR5K_DMASIZE_8B: 8Bytes
818 * @AR5K_DMASIZE_16B: 16Bytes
819 * @AR5K_DMASIZE_32B: 32Bytes
820 * @AR5K_DMASIZE_64B: 64Bytes (Default)
821 * @AR5K_DMASIZE_128B: 128Bytes
822 * @AR5K_DMASIZE_256B: 256Bytes
823 * @AR5K_DMASIZE_512B: 512Bytes
824 *
825 * These are used to set DMA burst size on hw
826 *
827 * Note: Some platforms can't handle more than 4Bytes
828 * be careful on embedded boards.
829 */
830 enum ath5k_dmasize {
831 AR5K_DMASIZE_4B = 0,
832 AR5K_DMASIZE_8B,
833 AR5K_DMASIZE_16B,
834 AR5K_DMASIZE_32B,
835 AR5K_DMASIZE_64B,
836 AR5K_DMASIZE_128B,
837 AR5K_DMASIZE_256B,
838 AR5K_DMASIZE_512B
839 };
840
841
842
843 /******************\
844 RATE DEFINITIONS
845 \******************/
846
847 /**
848 * DOC: Rate codes
849 *
850 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
851 *
852 * The rate code is used to get the RX rate or set the TX rate on the
853 * hardware descriptors. It is also used for internal modulation control
854 * and settings.
855 *
856 * This is the hardware rate map we are aware of (html unfriendly):
857 *
858 * Rate code Rate (Kbps)
859 * --------- -----------
860 * 0x01 3000 (XR)
861 * 0x02 1000 (XR)
862 * 0x03 250 (XR)
863 * 0x04 - 05 -Reserved-
864 * 0x06 2000 (XR)
865 * 0x07 500 (XR)
866 * 0x08 48000 (OFDM)
867 * 0x09 24000 (OFDM)
868 * 0x0A 12000 (OFDM)
869 * 0x0B 6000 (OFDM)
870 * 0x0C 54000 (OFDM)
871 * 0x0D 36000 (OFDM)
872 * 0x0E 18000 (OFDM)
873 * 0x0F 9000 (OFDM)
874 * 0x10 - 17 -Reserved-
875 * 0x18 11000L (CCK)
876 * 0x19 5500L (CCK)
877 * 0x1A 2000L (CCK)
878 * 0x1B 1000L (CCK)
879 * 0x1C 11000S (CCK)
880 * 0x1D 5500S (CCK)
881 * 0x1E 2000S (CCK)
882 * 0x1F -Reserved-
883 *
884 * "S" indicates CCK rates with short preamble and "L" with long preamble.
885 *
886 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
887 * lowest 4 bits, so they are the same as above with a 0xF mask.
888 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
889 * We handle this in ath5k_setup_bands().
890 */
891 #define AR5K_MAX_RATES 32
892
893 /* B */
894 #define ATH5K_RATE_CODE_1M 0x1B
895 #define ATH5K_RATE_CODE_2M 0x1A
896 #define ATH5K_RATE_CODE_5_5M 0x19
897 #define ATH5K_RATE_CODE_11M 0x18
898 /* A and G */
899 #define ATH5K_RATE_CODE_6M 0x0B
900 #define ATH5K_RATE_CODE_9M 0x0F
901 #define ATH5K_RATE_CODE_12M 0x0A
902 #define ATH5K_RATE_CODE_18M 0x0E
903 #define ATH5K_RATE_CODE_24M 0x09
904 #define ATH5K_RATE_CODE_36M 0x0D
905 #define ATH5K_RATE_CODE_48M 0x08
906 #define ATH5K_RATE_CODE_54M 0x0C
907
908 /* Adding this flag to rate_code on B rates
909 * enables short preamble */
910 #define AR5K_SET_SHORT_PREAMBLE 0x04
911
912 /*
913 * Crypto definitions
914 */
915
916 #define AR5K_KEYCACHE_SIZE 8
917 extern bool ath5k_modparam_nohwcrypt;
918
919 /***********************\
920 HW RELATED DEFINITIONS
921 \***********************/
922
923 /*
924 * Misc definitions
925 */
926 #define AR5K_RSSI_EP_MULTIPLIER (1 << 7)
927
928 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
929 if (_e >= _s) \
930 return false; \
931 } while (0)
932
933 /*
934 * Hardware interrupt abstraction
935 */
936
937 /**
938 * enum ath5k_int - Hardware interrupt masks helpers
939 * @AR5K_INT_RXOK: Frame successfully received
940 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor
941 * @AR5K_INT_RXERR: Frame reception failed
942 * @AR5K_INT_RXNOFRM: No frame received within a specified time period
943 * @AR5K_INT_RXEOL: Reached "End Of List", means we need more RX descriptors
944 * @AR5K_INT_RXORN: Indicates we got RX FIFO overrun. Note that Rx overrun is
945 * not always fatal, on some chips we can continue operation
946 * without resetting the card, that's why %AR5K_INT_FATAL is not
947 * common for all chips.
948 * @AR5K_INT_RX_ALL: Mask to identify all RX related interrupts
949 *
950 * @AR5K_INT_TXOK: Frame transmission success
951 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor
952 * @AR5K_INT_TXERR: Frame transmission failure
953 * @AR5K_INT_TXEOL: Received End Of List for VEOL (Virtual End Of List). The
954 * Queue Control Unit (QCU) signals an EOL interrupt only if a
955 * descriptor's LinkPtr is NULL. For more details, refer to:
956 * "http://www.freepatentsonline.com/20030225739.html"
957 * @AR5K_INT_TXNOFRM: No frame was transmitted within a specified time period
958 * @AR5K_INT_TXURN: Indicates we got TX FIFO underrun. In such case we should
959 * increase the TX trigger threshold.
960 * @AR5K_INT_TX_ALL: Mask to identify all TX related interrupts
961 *
962 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
963 * one of the PHY error counters reached the maximum value and
964 * should be read and cleared.
965 * @AR5K_INT_SWI: Software triggered interrupt.
966 * @AR5K_INT_RXPHY: RX PHY Error
967 * @AR5K_INT_RXKCM: RX Key cache miss
968 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
969 * beacon that must be handled in software. The alternative is if
970 * you have VEOL support, in that case you let the hardware deal
971 * with things.
972 * @AR5K_INT_BRSSI: Beacon received with an RSSI value below our threshold
973 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
974 * beacons from the AP have associated with, we should probably
975 * try to reassociate. When in IBSS mode this might mean we have
976 * not received any beacons from any local stations. Note that
977 * every station in an IBSS schedules to send beacons at the
978 * Target Beacon Transmission Time (TBTT) with a random backoff.
979 * @AR5K_INT_BNR: Beacon queue got triggered (DMA beacon alert) while empty.
980 * @AR5K_INT_TIM: Beacon with local station's TIM bit set
981 * @AR5K_INT_DTIM: Beacon with DTIM bit and zero DTIM count received
982 * @AR5K_INT_DTIM_SYNC: DTIM sync lost
983 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill switches connected to
984 * our GPIO pins.
985 * @AR5K_INT_BCN_TIMEOUT: Beacon timeout, we waited after TBTT but got noting
986 * @AR5K_INT_CAB_TIMEOUT: We waited for CAB traffic after the beacon but got
987 * nothing or an incomplete CAB frame sequence.
988 * @AR5K_INT_QCBRORN: A queue got it's CBR counter expired
989 * @AR5K_INT_QCBRURN: A queue got triggered wile empty
990 * @AR5K_INT_QTRIG: A queue got triggered
991 *
992 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by bus/DMA
993 * errors. Indicates we need to reset the card.
994 * @AR5K_INT_GLOBAL: Used to clear and set the IER
995 * @AR5K_INT_NOCARD: Signals the card has been removed
996 * @AR5K_INT_COMMON: Common interrupts shared among MACs with the same
997 * bit value
998 *
999 * These are mapped to take advantage of some common bits
1000 * between the MACs, to be able to set intr properties
1001 * easier. Some of them are not used yet inside hw.c. Most map
1002 * to the respective hw interrupt value as they are common among different
1003 * MACs.
1004 */
1005 enum ath5k_int {
1006 AR5K_INT_RXOK = 0x00000001,
1007 AR5K_INT_RXDESC = 0x00000002,
1008 AR5K_INT_RXERR = 0x00000004,
1009 AR5K_INT_RXNOFRM = 0x00000008,
1010 AR5K_INT_RXEOL = 0x00000010,
1011 AR5K_INT_RXORN = 0x00000020,
1012 AR5K_INT_TXOK = 0x00000040,
1013 AR5K_INT_TXDESC = 0x00000080,
1014 AR5K_INT_TXERR = 0x00000100,
1015 AR5K_INT_TXNOFRM = 0x00000200,
1016 AR5K_INT_TXEOL = 0x00000400,
1017 AR5K_INT_TXURN = 0x00000800,
1018 AR5K_INT_MIB = 0x00001000,
1019 AR5K_INT_SWI = 0x00002000,
1020 AR5K_INT_RXPHY = 0x00004000,
1021 AR5K_INT_RXKCM = 0x00008000,
1022 AR5K_INT_SWBA = 0x00010000,
1023 AR5K_INT_BRSSI = 0x00020000,
1024 AR5K_INT_BMISS = 0x00040000,
1025 AR5K_INT_FATAL = 0x00080000, /* Non common */
1026 AR5K_INT_BNR = 0x00100000, /* Non common */
1027 AR5K_INT_TIM = 0x00200000, /* Non common */
1028 AR5K_INT_DTIM = 0x00400000, /* Non common */
1029 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
1030 AR5K_INT_GPIO = 0x01000000,
1031 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
1032 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
1033 AR5K_INT_QCBRORN = 0x08000000, /* Non common */
1034 AR5K_INT_QCBRURN = 0x10000000, /* Non common */
1035 AR5K_INT_QTRIG = 0x20000000, /* Non common */
1036 AR5K_INT_GLOBAL = 0x80000000,
1037
1038 AR5K_INT_TX_ALL = AR5K_INT_TXOK
1039 | AR5K_INT_TXDESC
1040 | AR5K_INT_TXERR
1041 | AR5K_INT_TXNOFRM
1042 | AR5K_INT_TXEOL
1043 | AR5K_INT_TXURN,
1044
1045 AR5K_INT_RX_ALL = AR5K_INT_RXOK
1046 | AR5K_INT_RXDESC
1047 | AR5K_INT_RXERR
1048 | AR5K_INT_RXNOFRM
1049 | AR5K_INT_RXEOL
1050 | AR5K_INT_RXORN,
1051
1052 AR5K_INT_COMMON = AR5K_INT_RXOK
1053 | AR5K_INT_RXDESC
1054 | AR5K_INT_RXERR
1055 | AR5K_INT_RXNOFRM
1056 | AR5K_INT_RXEOL
1057 | AR5K_INT_RXORN
1058 | AR5K_INT_TXOK
1059 | AR5K_INT_TXDESC
1060 | AR5K_INT_TXERR
1061 | AR5K_INT_TXNOFRM
1062 | AR5K_INT_TXEOL
1063 | AR5K_INT_TXURN
1064 | AR5K_INT_MIB
1065 | AR5K_INT_SWI
1066 | AR5K_INT_RXPHY
1067 | AR5K_INT_RXKCM
1068 | AR5K_INT_SWBA
1069 | AR5K_INT_BRSSI
1070 | AR5K_INT_BMISS
1071 | AR5K_INT_GPIO
1072 | AR5K_INT_GLOBAL,
1073
1074 AR5K_INT_NOCARD = 0xffffffff
1075 };
1076
1077 /**
1078 * enum ath5k_calibration_mask - Mask which calibration is active at the moment
1079 * @AR5K_CALIBRATION_FULL: Full calibration (AGC + SHORT)
1080 * @AR5K_CALIBRATION_SHORT: Short calibration (NF + I/Q)
1081 * @AR5K_CALIBRATION_NF: Noise Floor calibration
1082 * @AR5K_CALIBRATION_ANI: Adaptive Noise Immunity
1083 */
1084 enum ath5k_calibration_mask {
1085 AR5K_CALIBRATION_FULL = 0x01,
1086 AR5K_CALIBRATION_SHORT = 0x02,
1087 AR5K_CALIBRATION_NF = 0x04,
1088 AR5K_CALIBRATION_ANI = 0x08,
1089 };
1090
1091 /**
1092 * enum ath5k_power_mode - Power management modes
1093 * @AR5K_PM_UNDEFINED: Undefined
1094 * @AR5K_PM_AUTO: Allow card to sleep if possible
1095 * @AR5K_PM_AWAKE: Force card to wake up
1096 * @AR5K_PM_FULL_SLEEP: Force card to full sleep (DANGEROUS)
1097 * @AR5K_PM_NETWORK_SLEEP: Allow to sleep for a specified duration
1098 *
1099 * Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO
1100 * are also known to have problems on some cards. This is not a big
1101 * problem though because we can have almost the same effect as
1102 * FULL_SLEEP by putting card on warm reset (it's almost powered down).
1103 */
1104 enum ath5k_power_mode {
1105 AR5K_PM_UNDEFINED = 0,
1106 AR5K_PM_AUTO,
1107 AR5K_PM_AWAKE,
1108 AR5K_PM_FULL_SLEEP,
1109 AR5K_PM_NETWORK_SLEEP,
1110 };
1111
1112 /*
1113 * These match net80211 definitions (not used in
1114 * mac80211).
1115 * TODO: Clean this up
1116 */
1117 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
1118 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
1119 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
1120 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
1121 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
1122
1123 /* GPIO-controlled software LED */
1124 #define AR5K_SOFTLED_PIN 0
1125 #define AR5K_SOFTLED_ON 0
1126 #define AR5K_SOFTLED_OFF 1
1127
1128
1129 /* XXX: we *may* move cap_range stuff to struct wiphy */
1130 struct ath5k_capabilities {
1131 /*
1132 * Supported PHY modes
1133 * (ie. AR5K_MODE_11A, AR5K_MODE_11B, ...)
1134 */
1135 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
1136
1137 /*
1138 * Frequency range (without regulation restrictions)
1139 */
1140 struct {
1141 u16 range_2ghz_min;
1142 u16 range_2ghz_max;
1143 u16 range_5ghz_min;
1144 u16 range_5ghz_max;
1145 } cap_range;
1146
1147 /*
1148 * Values stored in the EEPROM (some of them...)
1149 */
1150 struct ath5k_eeprom_info cap_eeprom;
1151
1152 /*
1153 * Queue information
1154 */
1155 struct {
1156 u8 q_tx_num;
1157 } cap_queues;
1158
1159 bool cap_has_phyerr_counters;
1160 bool cap_has_mrr_support;
1161 bool cap_needs_2GHz_ovr;
1162 };
1163
1164 /* size of noise floor history (keep it a power of two) */
1165 #define ATH5K_NF_CAL_HIST_MAX 8
1166 struct ath5k_nfcal_hist {
1167 s16 index; /* current index into nfval */
1168 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
1169 };
1170
1171 #define ATH5K_LED_MAX_NAME_LEN 31
1172
1173 /*
1174 * State for LED triggers
1175 */
1176 struct ath5k_led {
1177 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
1178 struct ath5k_hw *ah; /* driver state */
1179 struct led_classdev led_dev; /* led classdev */
1180 };
1181
1182 /* Rfkill */
1183 struct ath5k_rfkill {
1184 /* GPIO PIN for rfkill */
1185 u16 gpio;
1186 /* polarity of rfkill GPIO PIN */
1187 bool polarity;
1188 /* RFKILL toggle tasklet */
1189 struct tasklet_struct toggleq;
1190 };
1191
1192 /* statistics */
1193 struct ath5k_statistics {
1194 /* antenna use */
1195 unsigned int antenna_rx[5]; /* frames count per antenna RX */
1196 unsigned int antenna_tx[5]; /* frames count per antenna TX */
1197
1198 /* frame errors */
1199 unsigned int rx_all_count; /* all RX frames, including errors */
1200 unsigned int tx_all_count; /* all TX frames, including errors */
1201 unsigned int rx_bytes_count; /* all RX bytes, including errored pkts
1202 * and the MAC headers for each packet
1203 */
1204 unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
1205 * and the MAC headers and padding for
1206 * each packet.
1207 */
1208 unsigned int rxerr_crc;
1209 unsigned int rxerr_phy;
1210 unsigned int rxerr_phy_code[32];
1211 unsigned int rxerr_fifo;
1212 unsigned int rxerr_decrypt;
1213 unsigned int rxerr_mic;
1214 unsigned int rxerr_proc;
1215 unsigned int rxerr_jumbo;
1216 unsigned int txerr_retry;
1217 unsigned int txerr_fifo;
1218 unsigned int txerr_filt;
1219
1220 /* MIB counters */
1221 unsigned int ack_fail;
1222 unsigned int rts_fail;
1223 unsigned int rts_ok;
1224 unsigned int fcs_error;
1225 unsigned int beacons;
1226
1227 unsigned int mib_intr;
1228 unsigned int rxorn_intr;
1229 unsigned int rxeol_intr;
1230 };
1231
1232 /*
1233 * Misc defines
1234 */
1235
1236 #define AR5K_MAX_GPIO 10
1237 #define AR5K_MAX_RF_BANKS 8
1238
1239 #if CHAN_DEBUG
1240 #define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200)
1241 #else
1242 #define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)
1243 #endif
1244
1245 #define ATH_RXBUF 40 /* number of RX buffers */
1246 #define ATH_TXBUF 200 /* number of TX buffers */
1247 #define ATH_BCBUF 4 /* number of beacon buffers */
1248 #define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
1249 #define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
1250
1251 /* Driver state associated with an instance of a device */
1252 struct ath5k_hw {
1253 struct ath_common common;
1254
1255 struct pci_dev *pdev;
1256 struct device *dev; /* for dma mapping */
1257 int irq;
1258 u16 devid;
1259 void __iomem *iobase; /* address of the device */
1260 struct mutex lock; /* dev-level lock */
1261 struct ieee80211_hw *hw; /* IEEE 802.11 common */
1262 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1263 struct ieee80211_channel channels[ATH_CHAN_MAX];
1264 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1265 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1266 enum nl80211_iftype opmode;
1267
1268 #ifdef CONFIG_ATH5K_DEBUG
1269 struct ath5k_dbg_info debug; /* debug info */
1270 #endif /* CONFIG_ATH5K_DEBUG */
1271
1272 struct ath5k_buf *bufptr; /* allocated buffer ptr */
1273 struct ath5k_desc *desc; /* TX/RX descriptors */
1274 dma_addr_t desc_daddr; /* DMA (physical) address */
1275 size_t desc_len; /* size of TX/RX descriptors */
1276
1277 DECLARE_BITMAP(status, 4);
1278 #define ATH_STAT_INVALID 0 /* disable hardware accesses */
1279 #define ATH_STAT_PROMISC 1
1280 #define ATH_STAT_LEDSOFT 2 /* enable LED gpio status */
1281 #define ATH_STAT_STARTED 3 /* opened & irqs enabled */
1282
1283 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
1284 struct ieee80211_channel *curchan; /* current h/w channel */
1285
1286 u16 nvifs;
1287
1288 enum ath5k_int imask; /* interrupt mask copy */
1289
1290 spinlock_t irqlock;
1291 bool rx_pending; /* rx tasklet pending */
1292 bool tx_pending; /* tx tasklet pending */
1293
1294 u8 bssidmask[ETH_ALEN];
1295
1296 unsigned int led_pin, /* GPIO pin for driving LED */
1297 led_on; /* pin setting for LED on */
1298
1299 struct work_struct reset_work; /* deferred chip reset */
1300 struct work_struct calib_work; /* deferred phy calibration */
1301
1302 struct list_head rxbuf; /* receive buffer */
1303 spinlock_t rxbuflock;
1304 u32 *rxlink; /* link ptr in last RX desc */
1305 struct tasklet_struct rxtq; /* rx intr tasklet */
1306 struct ath5k_led rx_led; /* rx led */
1307
1308 struct list_head txbuf; /* transmit buffer */
1309 spinlock_t txbuflock;
1310 unsigned int txbuf_len; /* buf count in txbuf list */
1311 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
1312 struct tasklet_struct txtq; /* tx intr tasklet */
1313 struct ath5k_led tx_led; /* tx led */
1314
1315 struct ath5k_rfkill rf_kill;
1316
1317 spinlock_t block; /* protects beacon */
1318 struct tasklet_struct beacontq; /* beacon intr tasklet */
1319 struct list_head bcbuf; /* beacon buffer */
1320 struct ieee80211_vif *bslot[ATH_BCBUF];
1321 u16 num_ap_vifs;
1322 u16 num_adhoc_vifs;
1323 u16 num_mesh_vifs;
1324 unsigned int bhalq, /* SW q for outgoing beacons */
1325 bmisscount, /* missed beacon transmits */
1326 bintval, /* beacon interval in TU */
1327 bsent;
1328 unsigned int nexttbtt; /* next beacon time in TU */
1329 struct ath5k_txq *cabq; /* content after beacon */
1330
1331 int power_level; /* Requested tx power in dBm */
1332 bool assoc; /* associate state */
1333 bool enable_beacon; /* true if beacons are on */
1334
1335 struct ath5k_statistics stats;
1336
1337 struct ath5k_ani_state ani_state;
1338 struct tasklet_struct ani_tasklet; /* ANI calibration */
1339
1340 struct delayed_work tx_complete_work;
1341
1342 struct survey_info survey; /* collected survey info */
1343
1344 enum ath5k_int ah_imr;
1345
1346 struct ieee80211_channel *ah_current_channel;
1347 bool ah_iq_cal_needed;
1348 bool ah_single_chip;
1349
1350 enum ath5k_version ah_version;
1351 enum ath5k_radio ah_radio;
1352 u32 ah_mac_srev;
1353 u16 ah_mac_version;
1354 u16 ah_phy_revision;
1355 u16 ah_radio_5ghz_revision;
1356 u16 ah_radio_2ghz_revision;
1357
1358 #define ah_modes ah_capabilities.cap_mode
1359 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1360
1361 u8 ah_retry_long;
1362 u8 ah_retry_short;
1363
1364 u32 ah_use_32khz_clock;
1365
1366 u8 ah_coverage_class;
1367 bool ah_ack_bitrate_high;
1368 u8 ah_bwmode;
1369 bool ah_short_slot;
1370
1371 /* Antenna Control */
1372 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1373 u8 ah_ant_mode;
1374 u8 ah_tx_ant;
1375 u8 ah_def_ant;
1376
1377 struct ath5k_capabilities ah_capabilities;
1378
1379 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1380 u32 ah_txq_status;
1381 u32 ah_txq_imr_txok;
1382 u32 ah_txq_imr_txerr;
1383 u32 ah_txq_imr_txurn;
1384 u32 ah_txq_imr_txdesc;
1385 u32 ah_txq_imr_txeol;
1386 u32 ah_txq_imr_cbrorn;
1387 u32 ah_txq_imr_cbrurn;
1388 u32 ah_txq_imr_qtrig;
1389 u32 ah_txq_imr_nofrm;
1390
1391 u32 ah_txq_isr_txok_all;
1392 u32 ah_txq_isr_txurn;
1393 u32 ah_txq_isr_qcborn;
1394 u32 ah_txq_isr_qcburn;
1395 u32 ah_txq_isr_qtrig;
1396
1397 u32 *ah_rf_banks;
1398 size_t ah_rf_banks_size;
1399 size_t ah_rf_regs_count;
1400 struct ath5k_gain ah_gain;
1401 u8 ah_offset[AR5K_MAX_RF_BANKS];
1402
1403
1404 struct {
1405 /* Temporary tables used for interpolation */
1406 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1407 [AR5K_EEPROM_POWER_TABLE_SIZE];
1408 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1409 [AR5K_EEPROM_POWER_TABLE_SIZE];
1410 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1411 u16 txp_rates_power_table[AR5K_MAX_RATES];
1412 u8 txp_min_idx;
1413 bool txp_tpc;
1414 /* Values in 0.25dB units */
1415 s16 txp_min_pwr;
1416 s16 txp_max_pwr;
1417 s16 txp_cur_pwr;
1418 /* Values in 0.5dB units */
1419 s16 txp_offset;
1420 s16 txp_ofdm;
1421 s16 txp_cck_ofdm_gainf_delta;
1422 /* Value in dB units */
1423 s16 txp_cck_ofdm_pwr_delta;
1424 bool txp_setup;
1425 } ah_txpower;
1426
1427 struct ath5k_nfcal_hist ah_nfcal_hist;
1428
1429 /* average beacon RSSI in our BSS (used by ANI) */
1430 struct ewma ah_beacon_rssi_avg;
1431
1432 /* noise floor from last periodic calibration */
1433 s32 ah_noise_floor;
1434
1435 /* Calibration timestamp */
1436 unsigned long ah_cal_next_full;
1437 unsigned long ah_cal_next_short;
1438 unsigned long ah_cal_next_ani;
1439
1440 /* Calibration mask */
1441 u8 ah_cal_mask;
1442
1443 /*
1444 * Function pointers
1445 */
1446 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1447 unsigned int, unsigned int, int, enum ath5k_pkt_type,
1448 unsigned int, unsigned int, unsigned int, unsigned int,
1449 unsigned int, unsigned int, unsigned int, unsigned int);
1450 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1451 struct ath5k_tx_status *);
1452 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1453 struct ath5k_rx_status *);
1454 };
1455
1456 struct ath_bus_ops {
1457 enum ath_bus_type ath_bus_type;
1458 void (*read_cachesize)(struct ath_common *common, int *csz);
1459 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
1460 int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac);
1461 };
1462
1463 /*
1464 * Prototypes
1465 */
1466 extern const struct ieee80211_ops ath5k_hw_ops;
1467
1468 /* Initialization and detach functions */
1469 int ath5k_hw_init(struct ath5k_hw *ah);
1470 void ath5k_hw_deinit(struct ath5k_hw *ah);
1471
1472 int ath5k_sysfs_register(struct ath5k_hw *ah);
1473 void ath5k_sysfs_unregister(struct ath5k_hw *ah);
1474
1475 /*Chip id helper functions */
1476 int ath5k_hw_read_srev(struct ath5k_hw *ah);
1477
1478 /* LED functions */
1479 int ath5k_init_leds(struct ath5k_hw *ah);
1480 void ath5k_led_enable(struct ath5k_hw *ah);
1481 void ath5k_led_off(struct ath5k_hw *ah);
1482 void ath5k_unregister_leds(struct ath5k_hw *ah);
1483
1484
1485 /* Reset Functions */
1486 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1487 int ath5k_hw_on_hold(struct ath5k_hw *ah);
1488 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1489 struct ieee80211_channel *channel, bool fast, bool skip_pcu);
1490 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1491 bool is_set);
1492 /* Power management functions */
1493
1494
1495 /* Clock rate related functions */
1496 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1497 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1498 void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
1499
1500
1501 /* DMA Related Functions */
1502 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1503 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1504 int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1505 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1506 int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
1507 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1508 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1509 u32 phys_addr);
1510 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1511 /* Interrupt handling */
1512 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1513 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1514 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1515 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
1516 /* Init/Stop functions */
1517 void ath5k_hw_dma_init(struct ath5k_hw *ah);
1518 int ath5k_hw_dma_stop(struct ath5k_hw *ah);
1519
1520 /* EEPROM access functions */
1521 int ath5k_eeprom_init(struct ath5k_hw *ah);
1522 void ath5k_eeprom_detach(struct ath5k_hw *ah);
1523
1524
1525 /* Protocol Control Unit Functions */
1526 /* Helpers */
1527 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
1528 int len, struct ieee80211_rate *rate, bool shortpre);
1529 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
1530 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
1531 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1532 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1533 /* RX filter control*/
1534 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1535 void ath5k_hw_set_bssid(struct ath5k_hw *ah);
1536 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1537 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1538 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1539 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1540 /* Receive (DRU) start/stop functions */
1541 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1542 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1543 /* Beacon control functions */
1544 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1545 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1546 void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1547 void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,
1548 u32 interval);
1549 bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
1550 /* Init function */
1551 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);
1552
1553 /* Queue Control Unit, DFS Control Unit Functions */
1554 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1555 struct ath5k_txq_info *queue_info);
1556 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1557 const struct ath5k_txq_info *queue_info);
1558 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1559 enum ath5k_tx_queue queue_type,
1560 struct ath5k_txq_info *queue_info);
1561 void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
1562 unsigned int queue);
1563 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1564 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1565 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1566 int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
1567 /* Init function */
1568 int ath5k_hw_init_queues(struct ath5k_hw *ah);
1569
1570 /* Hardware Descriptor Functions */
1571 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1572 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1573 u32 size, unsigned int flags);
1574 int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1575 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
1576 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
1577
1578
1579 /* GPIO Functions */
1580 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1581 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1582 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1583 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1584 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1585 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1586 u32 interrupt_level);
1587
1588
1589 /* RFkill Functions */
1590 void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1591 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1592
1593
1594 /* Misc functions TODO: Cleanup */
1595 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1596 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1597 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1598
1599
1600 /* Initial register settings functions */
1601 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1602
1603
1604 /* PHY functions */
1605 /* Misc PHY functions */
1606 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band);
1607 int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1608 /* Gain_F optimization */
1609 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1610 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1611 /* PHY/RF channel functions */
1612 bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1613 /* PHY calibration */
1614 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1615 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1616 struct ieee80211_channel *channel);
1617 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
1618 /* Spur mitigation */
1619 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1620 struct ieee80211_channel *channel);
1621 /* Antenna control */
1622 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1623 void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
1624 /* TX power setup */
1625 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1626 /* Init function */
1627 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1628 u8 mode, bool fast);
1629
1630 /*
1631 * Functions used internally
1632 */
1633
ath5k_hw_common(struct ath5k_hw * ah)1634 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1635 {
1636 return &ah->common;
1637 }
1638
ath5k_hw_regulatory(struct ath5k_hw * ah)1639 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1640 {
1641 return &(ath5k_hw_common(ah)->regulatory);
1642 }
1643
1644 #ifdef CONFIG_ATHEROS_AR231X
1645 #define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000)
1646
ath5k_ahb_reg(struct ath5k_hw * ah,u16 reg)1647 static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
1648 {
1649 /* On AR2315 and AR2317 the PCI clock domain registers
1650 * are outside of the WMAC register space */
1651 if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
1652 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
1653 return AR5K_AR2315_PCI_BASE + reg;
1654
1655 return ah->iobase + reg;
1656 }
1657
ath5k_hw_reg_read(struct ath5k_hw * ah,u16 reg)1658 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1659 {
1660 return ioread32(ath5k_ahb_reg(ah, reg));
1661 }
1662
ath5k_hw_reg_write(struct ath5k_hw * ah,u32 val,u16 reg)1663 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1664 {
1665 iowrite32(val, ath5k_ahb_reg(ah, reg));
1666 }
1667
1668 #else
1669
ath5k_hw_reg_read(struct ath5k_hw * ah,u16 reg)1670 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1671 {
1672 return ioread32(ah->iobase + reg);
1673 }
1674
ath5k_hw_reg_write(struct ath5k_hw * ah,u32 val,u16 reg)1675 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1676 {
1677 iowrite32(val, ah->iobase + reg);
1678 }
1679
1680 #endif
1681
ath5k_get_bus_type(struct ath5k_hw * ah)1682 static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
1683 {
1684 return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
1685 }
1686
ath5k_read_cachesize(struct ath_common * common,int * csz)1687 static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
1688 {
1689 common->bus_ops->read_cachesize(common, csz);
1690 }
1691
ath5k_hw_nvram_read(struct ath5k_hw * ah,u32 off,u16 * data)1692 static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
1693 {
1694 struct ath_common *common = ath5k_hw_common(ah);
1695 return common->bus_ops->eeprom_read(common, off, data);
1696 }
1697
ath5k_hw_bitswap(u32 val,unsigned int bits)1698 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1699 {
1700 u32 retval = 0, bit, i;
1701
1702 for (i = 0; i < bits; i++) {
1703 bit = (val >> i) & 1;
1704 retval = (retval << 1) | bit;
1705 }
1706
1707 return retval;
1708 }
1709
1710 #endif
1711