1 /*
2  * Copyright 2011 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26 
27 #include "drm.h"
28 
29 #if defined(__cplusplus)
30 extern "C" {
31 #endif
32 
33 /**
34  * DOC: overview
35  *
36  * In the DRM subsystem, framebuffer pixel formats are described using the
37  * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38  * fourcc code, a Format Modifier may optionally be provided, in order to
39  * further describe the buffer's format - for example tiling or compression.
40  *
41  * Format Modifiers
42  * ----------------
43  *
44  * Format modifiers are used in conjunction with a fourcc code, forming a
45  * unique fourcc:modifier pair. This format:modifier pair must fully define the
46  * format and data layout of the buffer, and should be the only way to describe
47  * that particular buffer.
48  *
49  * Having multiple fourcc:modifier pairs which describe the same layout should
50  * be avoided, as such aliases run the risk of different drivers exposing
51  * different names for the same data format, forcing userspace to understand
52  * that they are aliases.
53  *
54  * Format modifiers may change any property of the buffer, including the number
55  * of planes and/or the required allocation size. Format modifiers are
56  * vendor-namespaced, and as such the relationship between a fourcc code and a
57  * modifier is specific to the modifer being used. For example, some modifiers
58  * may preserve meaning - such as number of planes - from the fourcc code,
59  * whereas others may not.
60  *
61  * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62  * match only a single modifier. A modifier must not be a subset of layouts of
63  * another modifier. For instance, it's incorrect to encode pitch alignment in
64  * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
65  * aligned modifier. That said, modifiers can have implicit minimal
66  * requirements.
67  *
68  * For modifiers where the combination of fourcc code and modifier can alias,
69  * a canonical pair needs to be defined and used by all drivers. Preferred
70  * combinations are also encouraged where all combinations might lead to
71  * confusion and unnecessarily reduced interoperability. An example for the
72  * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
73  *
74  * There are two kinds of modifier users:
75  *
76  * - Kernel and user-space drivers: for drivers it's important that modifiers
77  *   don't alias, otherwise two drivers might support the same format but use
78  *   different aliases, preventing them from sharing buffers in an efficient
79  *   format.
80  * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
81  *   see modifiers as opaque tokens they can check for equality and intersect.
82  *   These users musn't need to know to reason about the modifier value
83  *   (i.e. they are not expected to extract information out of the modifier).
84  *
85  * Vendors should document their modifier usage in as much detail as
86  * possible, to ensure maximum compatibility across devices, drivers and
87  * applications.
88  *
89  * The authoritative list of format modifier codes is found in
90  * `include/uapi/drm/drm_fourcc.h`
91  *
92  * Open Source User Waiver
93  * -----------------------
94  *
95  * Because this is the authoritative source for pixel formats and modifiers
96  * referenced by GL, Vulkan extensions and other standards and hence used both
97  * by open source and closed source driver stacks, the usual requirement for an
98  * upstream in-kernel or open source userspace user does not apply.
99  *
100  * To ensure, as much as feasible, compatibility across stacks and avoid
101  * confusion with incompatible enumerations stakeholders for all relevant driver
102  * stacks should approve additions.
103  */
104 
105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
106 				 ((__u32)(c) << 16) | ((__u32)(d) << 24))
107 
108 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
109 
110 /* Reserve 0 for the invalid format specifier */
111 #define DRM_FORMAT_INVALID	0
112 
113 /* color index */
114 #define DRM_FORMAT_C1		fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
115 #define DRM_FORMAT_C2		fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
116 #define DRM_FORMAT_C4		fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
117 #define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
118 
119 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */
120 #define DRM_FORMAT_D1		fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */
121 
122 /* 2 bpp Darkness (inverse relationship between channel value and brightness) */
123 #define DRM_FORMAT_D2		fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */
124 
125 /* 4 bpp Darkness (inverse relationship between channel value and brightness) */
126 #define DRM_FORMAT_D4		fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */
127 
128 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */
129 #define DRM_FORMAT_D8		fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
130 
131 /* 1 bpp Red (direct relationship between channel value and brightness) */
132 #define DRM_FORMAT_R1		fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */
133 
134 /* 2 bpp Red (direct relationship between channel value and brightness) */
135 #define DRM_FORMAT_R2		fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */
136 
137 /* 4 bpp Red (direct relationship between channel value and brightness) */
138 #define DRM_FORMAT_R4		fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */
139 
140 /* 8 bpp Red (direct relationship between channel value and brightness) */
141 #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
142 
143 /* 10 bpp Red (direct relationship between channel value and brightness) */
144 #define DRM_FORMAT_R10		fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
145 
146 /* 12 bpp Red (direct relationship between channel value and brightness) */
147 #define DRM_FORMAT_R12		fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
148 
149 /* 16 bpp Red (direct relationship between channel value and brightness) */
150 #define DRM_FORMAT_R16		fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
151 
152 /* 16 bpp RG */
153 #define DRM_FORMAT_RG88		fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
154 #define DRM_FORMAT_GR88		fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
155 
156 /* 32 bpp RG */
157 #define DRM_FORMAT_RG1616	fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
158 #define DRM_FORMAT_GR1616	fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
159 
160 /* 8 bpp RGB */
161 #define DRM_FORMAT_RGB332	fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
162 #define DRM_FORMAT_BGR233	fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
163 
164 /* 16 bpp RGB */
165 #define DRM_FORMAT_XRGB4444	fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
166 #define DRM_FORMAT_XBGR4444	fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
167 #define DRM_FORMAT_RGBX4444	fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
168 #define DRM_FORMAT_BGRX4444	fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
169 
170 #define DRM_FORMAT_ARGB4444	fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
171 #define DRM_FORMAT_ABGR4444	fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
172 #define DRM_FORMAT_RGBA4444	fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
173 #define DRM_FORMAT_BGRA4444	fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
174 
175 #define DRM_FORMAT_XRGB1555	fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
176 #define DRM_FORMAT_XBGR1555	fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
177 #define DRM_FORMAT_RGBX5551	fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
178 #define DRM_FORMAT_BGRX5551	fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
179 
180 #define DRM_FORMAT_ARGB1555	fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
181 #define DRM_FORMAT_ABGR1555	fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
182 #define DRM_FORMAT_RGBA5551	fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
183 #define DRM_FORMAT_BGRA5551	fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
184 
185 #define DRM_FORMAT_RGB565	fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
186 #define DRM_FORMAT_BGR565	fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
187 
188 /* 24 bpp RGB */
189 #define DRM_FORMAT_RGB888	fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
190 #define DRM_FORMAT_BGR888	fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
191 
192 /* 32 bpp RGB */
193 #define DRM_FORMAT_XRGB8888	fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
194 #define DRM_FORMAT_XBGR8888	fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
195 #define DRM_FORMAT_RGBX8888	fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
196 #define DRM_FORMAT_BGRX8888	fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
197 
198 #define DRM_FORMAT_ARGB8888	fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
199 #define DRM_FORMAT_ABGR8888	fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
200 #define DRM_FORMAT_RGBA8888	fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
201 #define DRM_FORMAT_BGRA8888	fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
202 
203 #define DRM_FORMAT_XRGB2101010	fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
204 #define DRM_FORMAT_XBGR2101010	fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
205 #define DRM_FORMAT_RGBX1010102	fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
206 #define DRM_FORMAT_BGRX1010102	fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
207 
208 #define DRM_FORMAT_ARGB2101010	fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
209 #define DRM_FORMAT_ABGR2101010	fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
210 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
211 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
212 
213 /* 64 bpp RGB */
214 #define DRM_FORMAT_XRGB16161616	fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
215 #define DRM_FORMAT_XBGR16161616	fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
216 
217 #define DRM_FORMAT_ARGB16161616	fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
218 #define DRM_FORMAT_ABGR16161616	fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
219 
220 /*
221  * Floating point 64bpp RGB
222  * IEEE 754-2008 binary16 half-precision float
223  * [15:0] sign:exponent:mantissa 1:5:10
224  */
225 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
226 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
227 
228 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
229 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
230 
231 /*
232  * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
233  * of unused padding per component:
234  */
235 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
236 
237 /* packed YCbCr */
238 #define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
239 #define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
240 #define DRM_FORMAT_UYVY		fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
241 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
242 
243 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
244 #define DRM_FORMAT_AVUY8888	fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
245 #define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
246 #define DRM_FORMAT_XVUY8888	fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */
247 #define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
248 #define DRM_FORMAT_VUY101010	fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
249 
250 /*
251  * packed Y2xx indicate for each component, xx valid data occupy msb
252  * 16-xx padding occupy lsb
253  */
254 #define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
255 #define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
256 #define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
257 
258 /*
259  * packed Y4xx indicate for each component, xx valid data occupy msb
260  * 16-xx padding occupy lsb except Y410
261  */
262 #define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
263 #define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
264 #define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
265 
266 #define DRM_FORMAT_XVYU2101010	fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
267 #define DRM_FORMAT_XVYU12_16161616	fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
268 #define DRM_FORMAT_XVYU16161616	fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
269 
270 /*
271  * packed YCbCr420 2x2 tiled formats
272  * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
273  */
274 /* [63:0]   A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0  1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
275 #define DRM_FORMAT_Y0L0		fourcc_code('Y', '0', 'L', '0')
276 /* [63:0]   X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0  1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
277 #define DRM_FORMAT_X0L0		fourcc_code('X', '0', 'L', '0')
278 
279 /* [63:0]   A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */
280 #define DRM_FORMAT_Y0L2		fourcc_code('Y', '0', 'L', '2')
281 /* [63:0]   X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */
282 #define DRM_FORMAT_X0L2		fourcc_code('X', '0', 'L', '2')
283 
284 /*
285  * 1-plane YUV 4:2:0
286  * In these formats, the component ordering is specified (Y, followed by U
287  * then V), but the exact Linear layout is undefined.
288  * These formats can only be used with a non-Linear modifier.
289  */
290 #define DRM_FORMAT_YUV420_8BIT	fourcc_code('Y', 'U', '0', '8')
291 #define DRM_FORMAT_YUV420_10BIT	fourcc_code('Y', 'U', '1', '0')
292 
293 /*
294  * 2 plane RGB + A
295  * index 0 = RGB plane, same format as the corresponding non _A8 format has
296  * index 1 = A plane, [7:0] A
297  */
298 #define DRM_FORMAT_XRGB8888_A8	fourcc_code('X', 'R', 'A', '8')
299 #define DRM_FORMAT_XBGR8888_A8	fourcc_code('X', 'B', 'A', '8')
300 #define DRM_FORMAT_RGBX8888_A8	fourcc_code('R', 'X', 'A', '8')
301 #define DRM_FORMAT_BGRX8888_A8	fourcc_code('B', 'X', 'A', '8')
302 #define DRM_FORMAT_RGB888_A8	fourcc_code('R', '8', 'A', '8')
303 #define DRM_FORMAT_BGR888_A8	fourcc_code('B', '8', 'A', '8')
304 #define DRM_FORMAT_RGB565_A8	fourcc_code('R', '5', 'A', '8')
305 #define DRM_FORMAT_BGR565_A8	fourcc_code('B', '5', 'A', '8')
306 
307 /*
308  * 2 plane YCbCr
309  * index 0 = Y plane, [7:0] Y
310  * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
311  * or
312  * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
313  */
314 #define DRM_FORMAT_NV12		fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
315 #define DRM_FORMAT_NV21		fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
316 #define DRM_FORMAT_NV16		fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
317 #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
318 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
319 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
320 /*
321  * 2 plane YCbCr
322  * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
323  * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
324  */
325 #define DRM_FORMAT_NV15		fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
326 
327 /*
328  * 2 plane YCbCr MSB aligned
329  * index 0 = Y plane, [15:0] Y:x [10:6] little endian
330  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
331  */
332 #define DRM_FORMAT_P210		fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
333 
334 /*
335  * 2 plane YCbCr MSB aligned
336  * index 0 = Y plane, [15:0] Y:x [10:6] little endian
337  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
338  */
339 #define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
340 
341 /*
342  * 2 plane YCbCr MSB aligned
343  * index 0 = Y plane, [15:0] Y:x [12:4] little endian
344  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
345  */
346 #define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
347 
348 /*
349  * 2 plane YCbCr MSB aligned
350  * index 0 = Y plane, [15:0] Y little endian
351  * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
352  */
353 #define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
354 
355 /* 2 plane YCbCr420.
356  * 3 10 bit components and 2 padding bits packed into 4 bytes.
357  * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
358  * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
359  */
360 #define DRM_FORMAT_P030		fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
361 
362 /* 3 plane non-subsampled (444) YCbCr
363  * 16 bits per component, but only 10 bits are used and 6 bits are padded
364  * index 0: Y plane, [15:0] Y:x [10:6] little endian
365  * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
366  * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
367  */
368 #define DRM_FORMAT_Q410		fourcc_code('Q', '4', '1', '0')
369 
370 /* 3 plane non-subsampled (444) YCrCb
371  * 16 bits per component, but only 10 bits are used and 6 bits are padded
372  * index 0: Y plane, [15:0] Y:x [10:6] little endian
373  * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
374  * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
375  */
376 #define DRM_FORMAT_Q401		fourcc_code('Q', '4', '0', '1')
377 
378 /*
379  * 3 plane YCbCr
380  * index 0: Y plane, [7:0] Y
381  * index 1: Cb plane, [7:0] Cb
382  * index 2: Cr plane, [7:0] Cr
383  * or
384  * index 1: Cr plane, [7:0] Cr
385  * index 2: Cb plane, [7:0] Cb
386  */
387 #define DRM_FORMAT_YUV410	fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
388 #define DRM_FORMAT_YVU410	fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
389 #define DRM_FORMAT_YUV411	fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
390 #define DRM_FORMAT_YVU411	fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
391 #define DRM_FORMAT_YUV420	fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
392 #define DRM_FORMAT_YVU420	fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
393 #define DRM_FORMAT_YUV422	fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
394 #define DRM_FORMAT_YVU422	fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
395 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
396 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
397 
398 
399 /*
400  * Format Modifiers:
401  *
402  * Format modifiers describe, typically, a re-ordering or modification
403  * of the data in a plane of an FB.  This can be used to express tiled/
404  * swizzled formats, or compression, or a combination of the two.
405  *
406  * The upper 8 bits of the format modifier are a vendor-id as assigned
407  * below.  The lower 56 bits are assigned as vendor sees fit.
408  */
409 
410 /* Vendor Ids: */
411 #define DRM_FORMAT_MOD_VENDOR_NONE    0
412 #define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
413 #define DRM_FORMAT_MOD_VENDOR_AMD     0x02
414 #define DRM_FORMAT_MOD_VENDOR_NVIDIA  0x03
415 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
416 #define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
417 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
418 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
419 #define DRM_FORMAT_MOD_VENDOR_ARM     0x08
420 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
421 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
422 
423 /* add more to the end as needed */
424 
425 #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
426 
427 #define fourcc_mod_get_vendor(modifier) \
428 	(((modifier) >> 56) & 0xff)
429 
430 #define fourcc_mod_is_vendor(modifier, vendor) \
431 	(fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor)
432 
433 #define fourcc_mod_code(vendor, val) \
434 	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
435 
436 /*
437  * Format Modifier tokens:
438  *
439  * When adding a new token please document the layout with a code comment,
440  * similar to the fourcc codes above. drm_fourcc.h is considered the
441  * authoritative source for all of these.
442  *
443  * Generic modifier names:
444  *
445  * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
446  * for layouts which are common across multiple vendors. To preserve
447  * compatibility, in cases where a vendor-specific definition already exists and
448  * a generic name for it is desired, the common name is a purely symbolic alias
449  * and must use the same numerical value as the original definition.
450  *
451  * Note that generic names should only be used for modifiers which describe
452  * generic layouts (such as pixel re-ordering), which may have
453  * independently-developed support across multiple vendors.
454  *
455  * In future cases where a generic layout is identified before merging with a
456  * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
457  * 'NONE' could be considered. This should only be for obvious, exceptional
458  * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
459  * apply to a single vendor.
460  *
461  * Generic names should not be used for cases where multiple hardware vendors
462  * have implementations of the same standardised compression scheme (such as
463  * AFBC). In those cases, all implementations should use the same format
464  * modifier(s), reflecting the vendor of the standard.
465  */
466 
467 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
468 
469 /*
470  * Invalid Modifier
471  *
472  * This modifier can be used as a sentinel to terminate the format modifiers
473  * list, or to initialize a variable with an invalid modifier. It might also be
474  * used to report an error back to userspace for certain APIs.
475  */
476 #define DRM_FORMAT_MOD_INVALID	fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
477 
478 /*
479  * Linear Layout
480  *
481  * Just plain linear layout. Note that this is different from no specifying any
482  * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
483  * which tells the driver to also take driver-internal information into account
484  * and so might actually result in a tiled framebuffer.
485  */
486 #define DRM_FORMAT_MOD_LINEAR	fourcc_mod_code(NONE, 0)
487 
488 /*
489  * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
490  *
491  * The "none" format modifier doesn't actually mean that the modifier is
492  * implicit, instead it means that the layout is linear. Whether modifiers are
493  * used is out-of-band information carried in an API-specific way (e.g. in a
494  * flag for drm_mode_fb_cmd2).
495  */
496 #define DRM_FORMAT_MOD_NONE	0
497 
498 /* Intel framebuffer modifiers */
499 
500 /*
501  * Intel X-tiling layout
502  *
503  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
504  * in row-major layout. Within the tile bytes are laid out row-major, with
505  * a platform-dependent stride. On top of that the memory can apply
506  * platform-depending swizzling of some higher address bits into bit6.
507  *
508  * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
509  * On earlier platforms the is highly platforms specific and not useful for
510  * cross-driver sharing. It exists since on a given platform it does uniquely
511  * identify the layout in a simple way for i915-specific userspace, which
512  * facilitated conversion of userspace to modifiers. Additionally the exact
513  * format on some really old platforms is not known.
514  */
515 #define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 1)
516 
517 /*
518  * Intel Y-tiling layout
519  *
520  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
521  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
522  * chunks column-major, with a platform-dependent height. On top of that the
523  * memory can apply platform-depending swizzling of some higher address bits
524  * into bit6.
525  *
526  * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
527  * On earlier platforms the is highly platforms specific and not useful for
528  * cross-driver sharing. It exists since on a given platform it does uniquely
529  * identify the layout in a simple way for i915-specific userspace, which
530  * facilitated conversion of userspace to modifiers. Additionally the exact
531  * format on some really old platforms is not known.
532  */
533 #define I915_FORMAT_MOD_Y_TILED	fourcc_mod_code(INTEL, 2)
534 
535 /*
536  * Intel Yf-tiling layout
537  *
538  * This is a tiled layout using 4Kb tiles in row-major layout.
539  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
540  * are arranged in four groups (two wide, two high) with column-major layout.
541  * Each group therefore consits out of four 256 byte units, which are also laid
542  * out as 2x2 column-major.
543  * 256 byte units are made out of four 64 byte blocks of pixels, producing
544  * either a square block or a 2:1 unit.
545  * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
546  * in pixel depends on the pixel depth.
547  */
548 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
549 
550 /*
551  * Intel color control surface (CCS) for render compression
552  *
553  * The framebuffer format must be one of the 8:8:8:8 RGB formats.
554  * The main surface will be plane index 0 and must be Y/Yf-tiled,
555  * the CCS will be plane index 1.
556  *
557  * Each CCS tile matches a 1024x512 pixel area of the main surface.
558  * To match certain aspects of the 3D hardware the CCS is
559  * considered to be made up of normal 128Bx32 Y tiles, Thus
560  * the CCS pitch must be specified in multiples of 128 bytes.
561  *
562  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
563  * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
564  * But that fact is not relevant unless the memory is accessed
565  * directly.
566  */
567 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
568 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
569 
570 /*
571  * Intel color control surfaces (CCS) for Gen-12 render compression.
572  *
573  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
574  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
575  * main surface. In other words, 4 bits in CCS map to a main surface cache
576  * line pair. The main surface pitch is required to be a multiple of four
577  * Y-tile widths.
578  */
579 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
580 
581 /*
582  * Intel color control surfaces (CCS) for Gen-12 media compression
583  *
584  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
585  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
586  * main surface. In other words, 4 bits in CCS map to a main surface cache
587  * line pair. The main surface pitch is required to be a multiple of four
588  * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
589  * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
590  * planes 2 and 3 for the respective CCS.
591  */
592 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
593 
594 /*
595  * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
596  * compression.
597  *
598  * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
599  * and at index 1. The clear color is stored at index 2, and the pitch should
600  * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits
601  * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
602  * by 32 bits. The raw clear color is consumed by the 3d engine and generates
603  * the converted clear color of size 64 bits. The first 32 bits store the Lower
604  * Converted Clear Color value and the next 32 bits store the Higher Converted
605  * Clear Color value when applicable. The Converted Clear Color values are
606  * consumed by the DE. The last 64 bits are used to store Color Discard Enable
607  * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
608  * corresponds to an area of 4x1 tiles in the main surface. The main surface
609  * pitch is required to be a multiple of 4 tile widths.
610  */
611 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
612 
613 /*
614  * Intel Tile 4 layout
615  *
616  * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
617  * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
618  * only differs from Tile Y at the 256B granularity in between. At this
619  * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
620  * of 64B x 8 rows.
621  */
622 #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
623 
624 /*
625  * Intel color control surfaces (CCS) for DG2 render compression.
626  *
627  * The main surface is Tile 4 and at plane index 0. The CCS data is stored
628  * outside of the GEM object in a reserved memory area dedicated for the
629  * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
630  * main surface pitch is required to be a multiple of four Tile 4 widths.
631  */
632 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
633 
634 /*
635  * Intel color control surfaces (CCS) for DG2 media compression.
636  *
637  * The main surface is Tile 4 and at plane index 0. For semi-planar formats
638  * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
639  * 0 and 1, respectively. The CCS for all planes are stored outside of the
640  * GEM object in a reserved memory area dedicated for the storage of the
641  * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
642  * pitch is required to be a multiple of four Tile 4 widths.
643  */
644 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
645 
646 /*
647  * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
648  *
649  * The main surface is Tile 4 and at plane index 0. The CCS data is stored
650  * outside of the GEM object in a reserved memory area dedicated for the
651  * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
652  * main surface pitch is required to be a multiple of four Tile 4 widths. The
653  * clear color is stored at plane index 1 and the pitch should be 64 bytes
654  * aligned. The format of the 256 bits of clear color data matches the one used
655  * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
656  * for details.
657  */
658 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
659 
660 /*
661  * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
662  *
663  * The main surface is tile4 and at plane index 0, the CCS is linear and
664  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
665  * main surface. In other words, 4 bits in CCS map to a main surface cache
666  * line pair. The main surface pitch is required to be a multiple of four
667  * tile4 widths.
668  */
669 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
670 
671 /*
672  * Intel Color Control Surfaces (CCS) for display ver. 14 media compression
673  *
674  * The main surface is tile4 and at plane index 0, the CCS is linear and
675  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
676  * main surface. In other words, 4 bits in CCS map to a main surface cache
677  * line pair. The main surface pitch is required to be a multiple of four
678  * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
679  * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
680  * planes 2 and 3 for the respective CCS.
681  */
682 #define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
683 
684 /*
685  * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render
686  * compression.
687  *
688  * The main surface is tile4 and is at plane index 0 whereas CCS is linear
689  * and at index 1. The clear color is stored at index 2, and the pitch should
690  * be ignored. The clear color structure is 256 bits. The first 128 bits
691  * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
692  * by 32 bits. The raw clear color is consumed by the 3d engine and generates
693  * the converted clear color of size 64 bits. The first 32 bits store the Lower
694  * Converted Clear Color value and the next 32 bits store the Higher Converted
695  * Clear Color value when applicable. The Converted Clear Color values are
696  * consumed by the DE. The last 64 bits are used to store Color Discard Enable
697  * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
698  * corresponds to an area of 4x1 tiles in the main surface. The main surface
699  * pitch is required to be a multiple of 4 tile widths.
700  */
701 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
702 
703 /*
704  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
705  *
706  * Macroblocks are laid in a Z-shape, and each pixel data is following the
707  * standard NV12 style.
708  * As for NV12, an image is the result of two frame buffers: one for Y,
709  * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
710  * Alignment requirements are (for each buffer):
711  * - multiple of 128 pixels for the width
712  * - multiple of  32 pixels for the height
713  *
714  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
715  */
716 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
717 
718 /*
719  * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
720  *
721  * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
722  * layout. For YCbCr formats Cb/Cr components are taken in such a way that
723  * they correspond to their 16x16 luma block.
724  */
725 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE	fourcc_mod_code(SAMSUNG, 2)
726 
727 /*
728  * Qualcomm Compressed Format
729  *
730  * Refers to a compressed variant of the base format that is compressed.
731  * Implementation may be platform and base-format specific.
732  *
733  * Each macrotile consists of m x n (mostly 4 x 4) tiles.
734  * Pixel data pitch/stride is aligned with macrotile width.
735  * Pixel data height is aligned with macrotile height.
736  * Entire pixel data buffer is aligned with 4k(bytes).
737  */
738 #define DRM_FORMAT_MOD_QCOM_COMPRESSED	fourcc_mod_code(QCOM, 1)
739 
740 /*
741  * Qualcomm Tiled Format
742  *
743  * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
744  * Implementation may be platform and base-format specific.
745  *
746  * Each macrotile consists of m x n (mostly 4 x 4) tiles.
747  * Pixel data pitch/stride is aligned with macrotile width.
748  * Pixel data height is aligned with macrotile height.
749  * Entire pixel data buffer is aligned with 4k(bytes).
750  */
751 #define DRM_FORMAT_MOD_QCOM_TILED3	fourcc_mod_code(QCOM, 3)
752 
753 /*
754  * Qualcomm Alternate Tiled Format
755  *
756  * Alternate tiled format typically only used within GMEM.
757  * Implementation may be platform and base-format specific.
758  */
759 #define DRM_FORMAT_MOD_QCOM_TILED2	fourcc_mod_code(QCOM, 2)
760 
761 
762 /* Vivante framebuffer modifiers */
763 
764 /*
765  * Vivante 4x4 tiling layout
766  *
767  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
768  * layout.
769  */
770 #define DRM_FORMAT_MOD_VIVANTE_TILED		fourcc_mod_code(VIVANTE, 1)
771 
772 /*
773  * Vivante 64x64 super-tiling layout
774  *
775  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
776  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
777  * major layout.
778  *
779  * For more information: see
780  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
781  */
782 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED	fourcc_mod_code(VIVANTE, 2)
783 
784 /*
785  * Vivante 4x4 tiling layout for dual-pipe
786  *
787  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
788  * different base address. Offsets from the base addresses are therefore halved
789  * compared to the non-split tiled layout.
790  */
791 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED	fourcc_mod_code(VIVANTE, 3)
792 
793 /*
794  * Vivante 64x64 super-tiling layout for dual-pipe
795  *
796  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
797  * starts at a different base address. Offsets from the base addresses are
798  * therefore halved compared to the non-split super-tiled layout.
799  */
800 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
801 
802 /*
803  * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
804  * the color buffer tiling modifiers defined above. When TS is present it's a
805  * separate buffer containing the clear/compression status of each tile. The
806  * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer
807  * tile size in bytes covered by one entry in the status buffer and s is the
808  * number of status bits per entry.
809  * We reserve the top 8 bits of the Vivante modifier space for tile status
810  * clear/compression modifiers, as future cores might add some more TS layout
811  * variations.
812  */
813 #define VIVANTE_MOD_TS_64_4               (1ULL << 48)
814 #define VIVANTE_MOD_TS_64_2               (2ULL << 48)
815 #define VIVANTE_MOD_TS_128_4              (3ULL << 48)
816 #define VIVANTE_MOD_TS_256_4              (4ULL << 48)
817 #define VIVANTE_MOD_TS_MASK               (0xfULL << 48)
818 
819 /*
820  * Vivante compression modifiers. Those depend on a TS modifier being present
821  * as the TS bits get reinterpreted as compression tags instead of simple
822  * clear markers when compression is enabled.
823  */
824 #define VIVANTE_MOD_COMP_DEC400           (1ULL << 52)
825 #define VIVANTE_MOD_COMP_MASK             (0xfULL << 52)
826 
827 /* Masking out the extension bits will yield the base modifier. */
828 #define VIVANTE_MOD_EXT_MASK              (VIVANTE_MOD_TS_MASK | \
829                                            VIVANTE_MOD_COMP_MASK)
830 
831 /* NVIDIA frame buffer modifiers */
832 
833 /*
834  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
835  *
836  * Pixels are arranged in simple tiles of 16 x 16 bytes.
837  */
838 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
839 
840 /*
841  * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
842  * and Tegra GPUs starting with Tegra K1.
843  *
844  * Pixels are arranged in Groups of Bytes (GOBs).  GOB size and layout varies
845  * based on the architecture generation.  GOBs themselves are then arranged in
846  * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
847  * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
848  * a block depth or height of "4").
849  *
850  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
851  * in full detail.
852  *
853  *       Macro
854  * Bits  Param Description
855  * ----  ----- -----------------------------------------------------------------
856  *
857  *  3:0  h     log2(height) of each block, in GOBs.  Placed here for
858  *             compatibility with the existing
859  *             DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
860  *
861  *  4:4  -     Must be 1, to indicate block-linear layout.  Necessary for
862  *             compatibility with the existing
863  *             DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
864  *
865  *  8:5  -     Reserved (To support 3D-surfaces with variable log2(depth) block
866  *             size).  Must be zero.
867  *
868  *             Note there is no log2(width) parameter.  Some portions of the
869  *             hardware support a block width of two gobs, but it is impractical
870  *             to use due to lack of support elsewhere, and has no known
871  *             benefits.
872  *
873  * 11:9  -     Reserved (To support 2D-array textures with variable array stride
874  *             in blocks, specified via log2(tile width in blocks)).  Must be
875  *             zero.
876  *
877  * 19:12 k     Page Kind.  This value directly maps to a field in the page
878  *             tables of all GPUs >= NV50.  It affects the exact layout of bits
879  *             in memory and can be derived from the tuple
880  *
881  *               (format, GPU model, compression type, samples per pixel)
882  *
883  *             Where compression type is defined below.  If GPU model were
884  *             implied by the format modifier, format, or memory buffer, page
885  *             kind would not need to be included in the modifier itself, but
886  *             since the modifier should define the layout of the associated
887  *             memory buffer independent from any device or other context, it
888  *             must be included here.
889  *
890  * 21:20 g     GOB Height and Page Kind Generation.  The height of a GOB changed
891  *             starting with Fermi GPUs.  Additionally, the mapping between page
892  *             kind and bit layout has changed at various points.
893  *
894  *               0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
895  *               1 = Gob Height 4, G80 - GT2XX Page Kind mapping
896  *               2 = Gob Height 8, Turing+ Page Kind mapping
897  *               3 = Reserved for future use.
898  *
899  * 22:22 s     Sector layout.  On Tegra GPUs prior to Xavier, there is a further
900  *             bit remapping step that occurs at an even lower level than the
901  *             page kind and block linear swizzles.  This causes the layout of
902  *             surfaces mapped in those SOC's GPUs to be incompatible with the
903  *             equivalent mapping on other GPUs in the same system.
904  *
905  *               0 = Tegra K1 - Tegra Parker/TX2 Layout.
906  *               1 = Desktop GPU and Tegra Xavier+ Layout
907  *
908  * 25:23 c     Lossless Framebuffer Compression type.
909  *
910  *               0 = none
911  *               1 = ROP/3D, layout 1, exact compression format implied by Page
912  *                   Kind field
913  *               2 = ROP/3D, layout 2, exact compression format implied by Page
914  *                   Kind field
915  *               3 = CDE horizontal
916  *               4 = CDE vertical
917  *               5 = Reserved for future use
918  *               6 = Reserved for future use
919  *               7 = Reserved for future use
920  *
921  * 55:25 -     Reserved for future use.  Must be zero.
922  */
923 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
924 	fourcc_mod_code(NVIDIA, (0x10 | \
925 				 ((h) & 0xf) | \
926 				 (((k) & 0xff) << 12) | \
927 				 (((g) & 0x3) << 20) | \
928 				 (((s) & 0x1) << 22) | \
929 				 (((c) & 0x7) << 23)))
930 
931 /* To grandfather in prior block linear format modifiers to the above layout,
932  * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
933  * with block-linear layouts, is remapped within drivers to the value 0xfe,
934  * which corresponds to the "generic" kind used for simple single-sample
935  * uncompressed color formats on Fermi - Volta GPUs.
936  */
937 static inline __u64
drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)938 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
939 {
940 	if (!(modifier & 0x10) || (modifier & (0xff << 12)))
941 		return modifier;
942 	else
943 		return modifier | (0xfe << 12);
944 }
945 
946 /*
947  * 16Bx2 Block Linear layout, used by Tegra K1 and later
948  *
949  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
950  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
951  *
952  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
953  *
954  * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
955  * Valid values are:
956  *
957  * 0 == ONE_GOB
958  * 1 == TWO_GOBS
959  * 2 == FOUR_GOBS
960  * 3 == EIGHT_GOBS
961  * 4 == SIXTEEN_GOBS
962  * 5 == THIRTYTWO_GOBS
963  *
964  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
965  * in full detail.
966  */
967 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
968 	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
969 
970 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
971 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
972 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
973 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
974 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
975 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
976 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
977 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
978 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
979 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
980 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
981 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
982 
983 /*
984  * Some Broadcom modifiers take parameters, for example the number of
985  * vertical lines in the image. Reserve the lower 32 bits for modifier
986  * type, and the next 24 bits for parameters. Top 8 bits are the
987  * vendor code.
988  */
989 #define __fourcc_mod_broadcom_param_shift 8
990 #define __fourcc_mod_broadcom_param_bits 48
991 #define fourcc_mod_broadcom_code(val, params) \
992 	fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
993 #define fourcc_mod_broadcom_param(m) \
994 	((int)(((m) >> __fourcc_mod_broadcom_param_shift) &	\
995 	       ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
996 #define fourcc_mod_broadcom_mod(m) \
997 	((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) <<	\
998 		 __fourcc_mod_broadcom_param_shift))
999 
1000 /*
1001  * Broadcom VC4 "T" format
1002  *
1003  * This is the primary layout that the V3D GPU can texture from (it
1004  * can't do linear).  The T format has:
1005  *
1006  * - 64b utiles of pixels in a raster-order grid according to cpp.  It's 4x4
1007  *   pixels at 32 bit depth.
1008  *
1009  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1010  *   16x16 pixels).
1011  *
1012  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On
1013  *   even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
1014  *   they're (TR, BR, BL, TL), where bottom left is start of memory.
1015  *
1016  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1017  *   tiles) or right-to-left (odd rows of 4k tiles).
1018  */
1019 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
1020 
1021 /*
1022  * Broadcom SAND format
1023  *
1024  * This is the native format that the H.264 codec block uses.  For VC4
1025  * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
1026  *
1027  * The image can be considered to be split into columns, and the
1028  * columns are placed consecutively into memory.  The width of those
1029  * columns can be either 32, 64, 128, or 256 pixels, but in practice
1030  * only 128 pixel columns are used.
1031  *
1032  * The pitch between the start of each column is set to optimally
1033  * switch between SDRAM banks. This is passed as the number of lines
1034  * of column width in the modifier (we can't use the stride value due
1035  * to various core checks that look at it , so you should set the
1036  * stride to width*cpp).
1037  *
1038  * Note that the column height for this format modifier is the same
1039  * for all of the planes, assuming that each column contains both Y
1040  * and UV.  Some SAND-using hardware stores UV in a separate tiled
1041  * image from Y to reduce the column height, which is not supported
1042  * with these modifiers.
1043  *
1044  * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
1045  * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
1046  * wide, but as this is a 10 bpp format that translates to 96 pixels.
1047  */
1048 
1049 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
1050 	fourcc_mod_broadcom_code(2, v)
1051 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
1052 	fourcc_mod_broadcom_code(3, v)
1053 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
1054 	fourcc_mod_broadcom_code(4, v)
1055 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
1056 	fourcc_mod_broadcom_code(5, v)
1057 
1058 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
1059 	DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
1060 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
1061 	DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
1062 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
1063 	DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
1064 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
1065 	DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
1066 
1067 /* Broadcom UIF format
1068  *
1069  * This is the common format for the current Broadcom multimedia
1070  * blocks, including V3D 3.x and newer, newer video codecs, and
1071  * displays.
1072  *
1073  * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
1074  * and macroblocks (4x4 UIF blocks).  Those 4x4 UIF block groups are
1075  * stored in columns, with padding between the columns to ensure that
1076  * moving from one column to the next doesn't hit the same SDRAM page
1077  * bank.
1078  *
1079  * To calculate the padding, it is assumed that each hardware block
1080  * and the software driving it knows the platform's SDRAM page size,
1081  * number of banks, and XOR address, and that it's identical between
1082  * all blocks using the format.  This tiling modifier will use XOR as
1083  * necessary to reduce the padding.  If a hardware block can't do XOR,
1084  * the assumption is that a no-XOR tiling modifier will be created.
1085  */
1086 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
1087 
1088 /*
1089  * Arm Framebuffer Compression (AFBC) modifiers
1090  *
1091  * AFBC is a proprietary lossless image compression protocol and format.
1092  * It provides fine-grained random access and minimizes the amount of data
1093  * transferred between IP blocks.
1094  *
1095  * AFBC has several features which may be supported and/or used, which are
1096  * represented using bits in the modifier. Not all combinations are valid,
1097  * and different devices or use-cases may support different combinations.
1098  *
1099  * Further information on the use of AFBC modifiers can be found in
1100  * Documentation/gpu/afbc.rst
1101  */
1102 
1103 /*
1104  * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
1105  * modifiers) denote the category for modifiers. Currently we have three
1106  * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1107  * sixteen different categories.
1108  */
1109 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
1110 	fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
1111 
1112 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
1113 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
1114 
1115 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
1116 	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
1117 
1118 /*
1119  * AFBC superblock size
1120  *
1121  * Indicates the superblock size(s) used for the AFBC buffer. The buffer
1122  * size (in pixels) must be aligned to a multiple of the superblock size.
1123  * Four lowest significant bits(LSBs) are reserved for block size.
1124  *
1125  * Where one superblock size is specified, it applies to all planes of the
1126  * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
1127  * the first applies to the Luma plane and the second applies to the Chroma
1128  * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
1129  * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1130  */
1131 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK      0xf
1132 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16     (1ULL)
1133 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8      (2ULL)
1134 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4      (3ULL)
1135 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
1136 
1137 /*
1138  * AFBC lossless colorspace transform
1139  *
1140  * Indicates that the buffer makes use of the AFBC lossless colorspace
1141  * transform.
1142  */
1143 #define AFBC_FORMAT_MOD_YTR     (1ULL <<  4)
1144 
1145 /*
1146  * AFBC block-split
1147  *
1148  * Indicates that the payload of each superblock is split. The second
1149  * half of the payload is positioned at a predefined offset from the start
1150  * of the superblock payload.
1151  */
1152 #define AFBC_FORMAT_MOD_SPLIT   (1ULL <<  5)
1153 
1154 /*
1155  * AFBC sparse layout
1156  *
1157  * This flag indicates that the payload of each superblock must be stored at a
1158  * predefined position relative to the other superblocks in the same AFBC
1159  * buffer. This order is the same order used by the header buffer. In this mode
1160  * each superblock is given the same amount of space as an uncompressed
1161  * superblock of the particular format would require, rounding up to the next
1162  * multiple of 128 bytes in size.
1163  */
1164 #define AFBC_FORMAT_MOD_SPARSE  (1ULL <<  6)
1165 
1166 /*
1167  * AFBC copy-block restrict
1168  *
1169  * Buffers with this flag must obey the copy-block restriction. The restriction
1170  * is such that there are no copy-blocks referring across the border of 8x8
1171  * blocks. For the subsampled data the 8x8 limitation is also subsampled.
1172  */
1173 #define AFBC_FORMAT_MOD_CBR     (1ULL <<  7)
1174 
1175 /*
1176  * AFBC tiled layout
1177  *
1178  * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1179  * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1180  * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
1181  * larger bpp formats. The order between the tiles is scan line.
1182  * When the tiled layout is used, the buffer size (in pixels) must be aligned
1183  * to the tile size.
1184  */
1185 #define AFBC_FORMAT_MOD_TILED   (1ULL <<  8)
1186 
1187 /*
1188  * AFBC solid color blocks
1189  *
1190  * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1191  * can be reduced if a whole superblock is a single color.
1192  */
1193 #define AFBC_FORMAT_MOD_SC      (1ULL <<  9)
1194 
1195 /*
1196  * AFBC double-buffer
1197  *
1198  * Indicates that the buffer is allocated in a layout safe for front-buffer
1199  * rendering.
1200  */
1201 #define AFBC_FORMAT_MOD_DB      (1ULL << 10)
1202 
1203 /*
1204  * AFBC buffer content hints
1205  *
1206  * Indicates that the buffer includes per-superblock content hints.
1207  */
1208 #define AFBC_FORMAT_MOD_BCH     (1ULL << 11)
1209 
1210 /* AFBC uncompressed storage mode
1211  *
1212  * Indicates that the buffer is using AFBC uncompressed storage mode.
1213  * In this mode all superblock payloads in the buffer use the uncompressed
1214  * storage mode, which is usually only used for data which cannot be compressed.
1215  * The buffer layout is the same as for AFBC buffers without USM set, this only
1216  * affects the storage mode of the individual superblocks. Note that even a
1217  * buffer without USM set may use uncompressed storage mode for some or all
1218  * superblocks, USM just guarantees it for all.
1219  */
1220 #define AFBC_FORMAT_MOD_USM	(1ULL << 12)
1221 
1222 /*
1223  * Arm Fixed-Rate Compression (AFRC) modifiers
1224  *
1225  * AFRC is a proprietary fixed rate image compression protocol and format,
1226  * designed to provide guaranteed bandwidth and memory footprint
1227  * reductions in graphics and media use-cases.
1228  *
1229  * AFRC buffers consist of one or more planes, with the same components
1230  * and meaning as an uncompressed buffer using the same pixel format.
1231  *
1232  * Within each plane, the pixel/luma/chroma values are grouped into
1233  * "coding unit" blocks which are individually compressed to a
1234  * fixed size (in bytes). All coding units within a given plane of a buffer
1235  * store the same number of values, and have the same compressed size.
1236  *
1237  * The coding unit size is configurable, allowing different rates of compression.
1238  *
1239  * The start of each AFRC buffer plane must be aligned to an alignment granule which
1240  * depends on the coding unit size.
1241  *
1242  * Coding Unit Size   Plane Alignment
1243  * ----------------   ---------------
1244  * 16 bytes           1024 bytes
1245  * 24 bytes           512  bytes
1246  * 32 bytes           2048 bytes
1247  *
1248  * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned
1249  * to a multiple of the paging tile dimensions.
1250  * The dimensions of each paging tile depend on whether the buffer is optimised for
1251  * scanline (SCAN layout) or rotated (ROT layout) access.
1252  *
1253  * Layout   Paging Tile Width   Paging Tile Height
1254  * ------   -----------------   ------------------
1255  * SCAN     16 coding units     4 coding units
1256  * ROT      8  coding units     8 coding units
1257  *
1258  * The dimensions of each coding unit depend on the number of components
1259  * in the compressed plane and whether the buffer is optimised for
1260  * scanline (SCAN layout) or rotated (ROT layout) access.
1261  *
1262  * Number of Components in Plane   Layout      Coding Unit Width   Coding Unit Height
1263  * -----------------------------   ---------   -----------------   ------------------
1264  * 1                               SCAN        16 samples          4 samples
1265  * Example: 16x4 luma samples in a 'Y' plane
1266  *          16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1267  * -----------------------------   ---------   -----------------   ------------------
1268  * 1                               ROT         8 samples           8 samples
1269  * Example: 8x8 luma samples in a 'Y' plane
1270  *          8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1271  * -----------------------------   ---------   -----------------   ------------------
1272  * 2                               DONT CARE   8 samples           4 samples
1273  * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1274  * -----------------------------   ---------   -----------------   ------------------
1275  * 3                               DONT CARE   4 samples           4 samples
1276  * Example: 4x4 pixels in an RGB buffer without alpha
1277  * -----------------------------   ---------   -----------------   ------------------
1278  * 4                               DONT CARE   4 samples           4 samples
1279  * Example: 4x4 pixels in an RGB buffer with alpha
1280  */
1281 
1282 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
1283 
1284 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \
1285 	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
1286 
1287 /*
1288  * AFRC coding unit size modifier.
1289  *
1290  * Indicates the number of bytes used to store each compressed coding unit for
1291  * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance
1292  * is the same for both Cb and Cr, which may be stored in separate planes.
1293  *
1294  * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
1295  * each compressed coding unit in the first plane of the buffer. For RGBA buffers
1296  * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1297  * this corresponds to the luma plane.
1298  *
1299  * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
1300  * each compressed coding unit in the second and third planes in the buffer.
1301  * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1302  *
1303  * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1304  * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero.
1305  * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1306  * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified.
1307  */
1308 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
1309 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
1310 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
1311 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
1312 
1313 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
1314 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
1315 
1316 /*
1317  * AFRC scanline memory layout.
1318  *
1319  * Indicates if the buffer uses the scanline-optimised layout
1320  * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1321  * The memory layout is the same for all planes.
1322  */
1323 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1324 
1325 /*
1326  * Arm 16x16 Block U-Interleaved modifier
1327  *
1328  * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
1329  * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
1330  * in the block are reordered.
1331  */
1332 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
1333 	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1334 
1335 /*
1336  * Allwinner tiled modifier
1337  *
1338  * This tiling mode is implemented by the VPU found on all Allwinner platforms,
1339  * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1340  * planes.
1341  *
1342  * With this tiling, the luminance samples are disposed in tiles representing
1343  * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
1344  * The pixel order in each tile is linear and the tiles are disposed linearly,
1345  * both in row-major order.
1346  */
1347 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1348 
1349 /*
1350  * Amlogic Video Framebuffer Compression modifiers
1351  *
1352  * Amlogic uses a proprietary lossless image compression protocol and format
1353  * for their hardware video codec accelerators, either video decoders or
1354  * video input encoders.
1355  *
1356  * It considerably reduces memory bandwidth while writing and reading
1357  * frames in memory.
1358  *
1359  * The underlying storage is considered to be 3 components, 8bit or 10-bit
1360  * per component YCbCr 420, single plane :
1361  * - DRM_FORMAT_YUV420_8BIT
1362  * - DRM_FORMAT_YUV420_10BIT
1363  *
1364  * The first 8 bits of the mode defines the layout, then the following 8 bits
1365  * defines the options changing the layout.
1366  *
1367  * Not all combinations are valid, and different SoCs may support different
1368  * combinations of layout and options.
1369  */
1370 #define __fourcc_mod_amlogic_layout_mask 0xff
1371 #define __fourcc_mod_amlogic_options_shift 8
1372 #define __fourcc_mod_amlogic_options_mask 0xff
1373 
1374 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1375 	fourcc_mod_code(AMLOGIC, \
1376 			((__layout) & __fourcc_mod_amlogic_layout_mask) | \
1377 			(((__options) & __fourcc_mod_amlogic_options_mask) \
1378 			 << __fourcc_mod_amlogic_options_shift))
1379 
1380 /* Amlogic FBC Layouts */
1381 
1382 /*
1383  * Amlogic FBC Basic Layout
1384  *
1385  * The basic layout is composed of:
1386  * - a body content organized in 64x32 superblocks with 4096 bytes per
1387  *   superblock in default mode.
1388  * - a 32 bytes per 128x64 header block
1389  *
1390  * This layout is transferrable between Amlogic SoCs supporting this modifier.
1391  */
1392 #define AMLOGIC_FBC_LAYOUT_BASIC		(1ULL)
1393 
1394 /*
1395  * Amlogic FBC Scatter Memory layout
1396  *
1397  * Indicates the header contains IOMMU references to the compressed
1398  * frames content to optimize memory access and layout.
1399  *
1400  * In this mode, only the header memory address is needed, thus the
1401  * content memory organization is tied to the current producer
1402  * execution and cannot be saved/dumped neither transferrable between
1403  * Amlogic SoCs supporting this modifier.
1404  *
1405  * Due to the nature of the layout, these buffers are not expected to
1406  * be accessible by the user-space clients, but only accessible by the
1407  * hardware producers and consumers.
1408  *
1409  * The user-space clients should expect a failure while trying to mmap
1410  * the DMA-BUF handle returned by the producer.
1411  */
1412 #define AMLOGIC_FBC_LAYOUT_SCATTER		(2ULL)
1413 
1414 /* Amlogic FBC Layout Options Bit Mask */
1415 
1416 /*
1417  * Amlogic FBC Memory Saving mode
1418  *
1419  * Indicates the storage is packed when pixel size is multiple of word
1420  * boudaries, i.e. 8bit should be stored in this mode to save allocation
1421  * memory.
1422  *
1423  * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1424  * the basic layout and 3200 bytes per 64x32 superblock combined with
1425  * the scatter layout.
1426  */
1427 #define AMLOGIC_FBC_OPTION_MEM_SAVING		(1ULL << 0)
1428 
1429 /*
1430  * AMD modifiers
1431  *
1432  * Memory layout:
1433  *
1434  * without DCC:
1435  *   - main surface
1436  *
1437  * with DCC & without DCC_RETILE:
1438  *   - main surface in plane 0
1439  *   - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1440  *
1441  * with DCC & DCC_RETILE:
1442  *   - main surface in plane 0
1443  *   - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1444  *   - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1445  *
1446  * For multi-plane formats the above surfaces get merged into one plane for
1447  * each format plane, based on the required alignment only.
1448  *
1449  * Bits  Parameter                Notes
1450  * ----- ------------------------ ---------------------------------------------
1451  *
1452  *   7:0 TILE_VERSION             Values are AMD_FMT_MOD_TILE_VER_*
1453  *  12:8 TILE                     Values are AMD_FMT_MOD_TILE_<version>_*
1454  *    13 DCC
1455  *    14 DCC_RETILE
1456  *    15 DCC_PIPE_ALIGN
1457  *    16 DCC_INDEPENDENT_64B
1458  *    17 DCC_INDEPENDENT_128B
1459  * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
1460  *    20 DCC_CONSTANT_ENCODE
1461  * 23:21 PIPE_XOR_BITS            Only for some chips
1462  * 26:24 BANK_XOR_BITS            Only for some chips
1463  * 29:27 PACKERS                  Only for some chips
1464  * 32:30 RB                       Only for some chips
1465  * 35:33 PIPE                     Only for some chips
1466  * 55:36 -                        Reserved for future use, must be zero
1467  */
1468 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
1469 
1470 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
1471 
1472 /* Reserve 0 for GFX8 and older */
1473 #define AMD_FMT_MOD_TILE_VER_GFX9 1
1474 #define AMD_FMT_MOD_TILE_VER_GFX10 2
1475 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
1476 #define AMD_FMT_MOD_TILE_VER_GFX11 4
1477 
1478 /*
1479  * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
1480  * version.
1481  */
1482 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9
1483 
1484 /*
1485  * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1486  * GFX9 as canonical version.
1487  */
1488 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1489 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
1490 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
1491 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
1492 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
1493 
1494 #define AMD_FMT_MOD_DCC_BLOCK_64B 0
1495 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
1496 #define AMD_FMT_MOD_DCC_BLOCK_256B 2
1497 
1498 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
1499 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
1500 #define AMD_FMT_MOD_TILE_SHIFT 8
1501 #define AMD_FMT_MOD_TILE_MASK 0x1F
1502 
1503 /* Whether DCC compression is enabled. */
1504 #define AMD_FMT_MOD_DCC_SHIFT 13
1505 #define AMD_FMT_MOD_DCC_MASK 0x1
1506 
1507 /*
1508  * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
1509  * one which is not-aligned.
1510  */
1511 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
1512 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
1513 
1514 /* Only set if DCC_RETILE = false */
1515 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
1516 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
1517 
1518 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
1519 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
1520 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
1521 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
1522 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
1523 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
1524 
1525 /*
1526  * DCC supports embedding some clear colors directly in the DCC surface.
1527  * However, on older GPUs the rendering HW ignores the embedded clear color
1528  * and prefers the driver provided color. This necessitates doing a fastclear
1529  * eliminate operation before a process transfers control.
1530  *
1531  * If this bit is set that means the fastclear eliminate is not needed for these
1532  * embeddable colors.
1533  */
1534 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
1535 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
1536 
1537 /*
1538  * The below fields are for accounting for per GPU differences. These are only
1539  * relevant for GFX9 and later and if the tile field is *_X/_T.
1540  *
1541  * PIPE_XOR_BITS = always needed
1542  * BANK_XOR_BITS = only for TILE_VER_GFX9
1543  * PACKERS = only for TILE_VER_GFX10_RBPLUS
1544  * RB = only for TILE_VER_GFX9 & DCC
1545  * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
1546  */
1547 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
1548 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
1549 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
1550 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
1551 #define AMD_FMT_MOD_PACKERS_SHIFT 27
1552 #define AMD_FMT_MOD_PACKERS_MASK 0x7
1553 #define AMD_FMT_MOD_RB_SHIFT 30
1554 #define AMD_FMT_MOD_RB_MASK 0x7
1555 #define AMD_FMT_MOD_PIPE_SHIFT 33
1556 #define AMD_FMT_MOD_PIPE_MASK 0x7
1557 
1558 #define AMD_FMT_MOD_SET(field, value) \
1559 	((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
1560 #define AMD_FMT_MOD_GET(field, value) \
1561 	(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
1562 #define AMD_FMT_MOD_CLEAR(field) \
1563 	(~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
1564 
1565 #if defined(__cplusplus)
1566 }
1567 #endif
1568 
1569 #endif /* DRM_FOURCC_H */
1570