1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König
23 */
24 #ifndef __AMDGPU_VM_H__
25 #define __AMDGPU_VM_H__
26
27 #include <linux/idr.h>
28 #include <linux/kfifo.h>
29 #include <linux/rbtree.h>
30 #include <drm/gpu_scheduler.h>
31 #include <drm/drm_file.h>
32 #include <drm/ttm/ttm_bo_driver.h>
33 #include <linux/sched/mm.h>
34
35 #include "amdgpu_sync.h"
36 #include "amdgpu_ring.h"
37 #include "amdgpu_ids.h"
38
39 struct amdgpu_bo_va;
40 struct amdgpu_job;
41 struct amdgpu_bo_list_entry;
42 struct amdgpu_bo_vm;
43
44 /*
45 * GPUVM handling
46 */
47
48 /* Maximum number of PTEs the hardware can write with one command */
49 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
50
51 /* number of entries in page table */
52 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
53
54 #define AMDGPU_PTE_VALID (1ULL << 0)
55 #define AMDGPU_PTE_SYSTEM (1ULL << 1)
56 #define AMDGPU_PTE_SNOOPED (1ULL << 2)
57
58 /* RV+ */
59 #define AMDGPU_PTE_TMZ (1ULL << 3)
60
61 /* VI only */
62 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
63
64 #define AMDGPU_PTE_READABLE (1ULL << 5)
65 #define AMDGPU_PTE_WRITEABLE (1ULL << 6)
66
67 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
68
69 /* TILED for VEGA10, reserved for older ASICs */
70 #define AMDGPU_PTE_PRT (1ULL << 51)
71
72 /* PDE is handled as PTE for VEGA10 */
73 #define AMDGPU_PDE_PTE (1ULL << 54)
74
75 #define AMDGPU_PTE_LOG (1ULL << 55)
76
77 /* PTE is handled as PDE for VEGA10 (Translate Further) */
78 #define AMDGPU_PTE_TF (1ULL << 56)
79
80 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */
81 #define AMDGPU_PTE_NOALLOC (1ULL << 58)
82
83 /* PDE Block Fragment Size for VEGA10 */
84 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
85
86
87 /* For GFX9 */
88 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57)
89 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL)
90
91 #define AMDGPU_MTYPE_NC 0
92 #define AMDGPU_MTYPE_CC 2
93
94 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
95 | AMDGPU_PTE_SNOOPED \
96 | AMDGPU_PTE_EXECUTABLE \
97 | AMDGPU_PTE_READABLE \
98 | AMDGPU_PTE_WRITEABLE \
99 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
100
101 /* gfx10 */
102 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48)
103 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL)
104
105 /* How to program VM fault handling */
106 #define AMDGPU_VM_FAULT_STOP_NEVER 0
107 #define AMDGPU_VM_FAULT_STOP_FIRST 1
108 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
109
110 /* Reserve 4MB VRAM for page tables */
111 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20)
112
113 /* max number of VMHUB */
114 #define AMDGPU_MAX_VMHUBS 3
115 #define AMDGPU_GFXHUB_0 0
116 #define AMDGPU_MMHUB_0 1
117 #define AMDGPU_MMHUB_1 2
118
119 /* Reserve 2MB at top/bottom of address space for kernel use */
120 #define AMDGPU_VA_RESERVED_SIZE (2ULL << 20)
121
122 /* max vmids dedicated for process */
123 #define AMDGPU_VM_MAX_RESERVED_VMID 1
124
125 /* See vm_update_mode */
126 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
127 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
128
129 /* VMPT level enumerate, and the hiberachy is:
130 * PDB2->PDB1->PDB0->PTB
131 */
132 enum amdgpu_vm_level {
133 AMDGPU_VM_PDB2,
134 AMDGPU_VM_PDB1,
135 AMDGPU_VM_PDB0,
136 AMDGPU_VM_PTB
137 };
138
139 /* base structure for tracking BO usage in a VM */
140 struct amdgpu_vm_bo_base {
141 /* constant after initialization */
142 struct amdgpu_vm *vm;
143 struct amdgpu_bo *bo;
144
145 /* protected by bo being reserved */
146 struct amdgpu_vm_bo_base *next;
147
148 /* protected by spinlock */
149 struct list_head vm_status;
150
151 /* protected by the BO being reserved */
152 bool moved;
153 };
154
155 /* provided by hw blocks that can write ptes, e.g., sdma */
156 struct amdgpu_vm_pte_funcs {
157 /* number of dw to reserve per operation */
158 unsigned copy_pte_num_dw;
159
160 /* copy pte entries from GART */
161 void (*copy_pte)(struct amdgpu_ib *ib,
162 uint64_t pe, uint64_t src,
163 unsigned count);
164
165 /* write pte one entry at a time with addr mapping */
166 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
167 uint64_t value, unsigned count,
168 uint32_t incr);
169 /* for linear pte/pde updates without addr mapping */
170 void (*set_pte_pde)(struct amdgpu_ib *ib,
171 uint64_t pe,
172 uint64_t addr, unsigned count,
173 uint32_t incr, uint64_t flags);
174 };
175
176 struct amdgpu_task_info {
177 char process_name[TASK_COMM_LEN];
178 char task_name[TASK_COMM_LEN];
179 pid_t pid;
180 pid_t tgid;
181 };
182
183 /**
184 * struct amdgpu_vm_update_params
185 *
186 * Encapsulate some VM table update parameters to reduce
187 * the number of function parameters
188 *
189 */
190 struct amdgpu_vm_update_params {
191
192 /**
193 * @adev: amdgpu device we do this update for
194 */
195 struct amdgpu_device *adev;
196
197 /**
198 * @vm: optional amdgpu_vm we do this update for
199 */
200 struct amdgpu_vm *vm;
201
202 /**
203 * @immediate: if changes should be made immediately
204 */
205 bool immediate;
206
207 /**
208 * @unlocked: true if the root BO is not locked
209 */
210 bool unlocked;
211
212 /**
213 * @pages_addr:
214 *
215 * DMA addresses to use for mapping
216 */
217 dma_addr_t *pages_addr;
218
219 /**
220 * @job: job to used for hw submission
221 */
222 struct amdgpu_job *job;
223
224 /**
225 * @num_dw_left: number of dw left for the IB
226 */
227 unsigned int num_dw_left;
228
229 /**
230 * @table_freed: return true if page table is freed when updating
231 */
232 bool table_freed;
233 };
234
235 struct amdgpu_vm_update_funcs {
236 int (*map_table)(struct amdgpu_bo_vm *bo);
237 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv,
238 enum amdgpu_sync_mode sync_mode);
239 int (*update)(struct amdgpu_vm_update_params *p,
240 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,
241 unsigned count, uint32_t incr, uint64_t flags);
242 int (*commit)(struct amdgpu_vm_update_params *p,
243 struct dma_fence **fence);
244 };
245
246 struct amdgpu_vm {
247 /* tree of virtual addresses mapped */
248 struct rb_root_cached va;
249
250 /* Lock to prevent eviction while we are updating page tables
251 * use vm_eviction_lock/unlock(vm)
252 */
253 struct mutex eviction_lock;
254 bool evicting;
255 unsigned int saved_flags;
256
257 /* Lock to protect vm_bo add/del/move on all lists of vm */
258 spinlock_t status_lock;
259
260 /* BOs who needs a validation */
261 struct list_head evicted;
262
263 /* PT BOs which relocated and their parent need an update */
264 struct list_head relocated;
265
266 /* per VM BOs moved, but not yet updated in the PT */
267 struct list_head moved;
268
269 /* All BOs of this VM not currently in the state machine */
270 struct list_head idle;
271
272 /* regular invalidated BOs, but not yet updated in the PT */
273 struct list_head invalidated;
274
275 /* BO mappings freed, but not yet updated in the PT */
276 struct list_head freed;
277
278 /* BOs which are invalidated, has been updated in the PTs */
279 struct list_head done;
280
281 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */
282 struct list_head pt_freed;
283 struct work_struct pt_free_work;
284
285 /* contains the page directory */
286 struct amdgpu_vm_bo_base root;
287 struct dma_fence *last_update;
288
289 /* Scheduler entities for page table updates */
290 struct drm_sched_entity immediate;
291 struct drm_sched_entity delayed;
292
293 /* Last finished delayed update */
294 atomic64_t tlb_seq;
295 struct dma_fence *last_tlb_flush;
296
297 /* Last unlocked submission to the scheduler entities */
298 struct dma_fence *last_unlocked;
299
300 unsigned int pasid;
301 /* dedicated to vm */
302 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
303
304 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
305 bool use_cpu_for_update;
306
307 /* Functions to use for VM table updates */
308 const struct amdgpu_vm_update_funcs *update_funcs;
309
310 /* Flag to indicate ATS support from PTE for GFX9 */
311 bool pte_support_ats;
312
313 /* Up to 128 pending retry page faults */
314 DECLARE_KFIFO(faults, u64, 128);
315
316 /* Points to the KFD process VM info */
317 struct amdkfd_process_info *process_info;
318
319 /* List node in amdkfd_process_info.vm_list_head */
320 struct list_head vm_list_node;
321
322 /* Valid while the PD is reserved or fenced */
323 uint64_t pd_phys_addr;
324
325 /* Some basic info about the task */
326 struct amdgpu_task_info task_info;
327
328 /* Store positions of group of BOs */
329 struct ttm_lru_bulk_move lru_bulk_move;
330 /* Flag to indicate if VM is used for compute */
331 bool is_compute_context;
332 };
333
334 struct amdgpu_vm_manager {
335 /* Handling of VMIDs */
336 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
337 unsigned int first_kfd_vmid;
338 bool concurrent_flush;
339
340 /* Handling of VM fences */
341 u64 fence_context;
342 unsigned seqno[AMDGPU_MAX_RINGS];
343
344 uint64_t max_pfn;
345 uint32_t num_level;
346 uint32_t block_size;
347 uint32_t fragment_size;
348 enum amdgpu_vm_level root_level;
349 /* vram base address for page table entry */
350 u64 vram_base_offset;
351 /* vm pte handling */
352 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
353 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS];
354 unsigned vm_pte_num_scheds;
355 struct amdgpu_ring *page_fault;
356
357 /* partial resident texture handling */
358 spinlock_t prt_lock;
359 atomic_t num_prt_users;
360
361 /* controls how VM page tables are updated for Graphics and Compute.
362 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
363 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
364 */
365 int vm_update_mode;
366
367 /* PASID to VM mapping, will be used in interrupt context to
368 * look up VM of a page fault
369 */
370 struct xarray pasids;
371 };
372
373 struct amdgpu_bo_va_mapping;
374
375 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
376 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
377 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
378
379 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
380 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
381
382 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
383 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
384
385 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
386 u32 pasid);
387
388 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
389 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
390 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
391 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
392 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
393 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
394 struct list_head *validated,
395 struct amdgpu_bo_list_entry *entry);
396 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
397 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
398 int (*callback)(void *p, struct amdgpu_bo *bo),
399 void *param);
400 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
401 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
402 struct amdgpu_vm *vm, bool immediate);
403 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
404 struct amdgpu_vm *vm,
405 struct dma_fence **fence);
406 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
407 struct amdgpu_vm *vm);
408 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
409 struct amdgpu_vm *vm, struct amdgpu_bo *bo);
410 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
411 bool immediate, bool unlocked, bool flush_tlb,
412 struct dma_resv *resv, uint64_t start, uint64_t last,
413 uint64_t flags, uint64_t offset, uint64_t vram_base,
414 struct ttm_resource *res, dma_addr_t *pages_addr,
415 struct dma_fence **fence);
416 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
417 struct amdgpu_bo_va *bo_va,
418 bool clear);
419 bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
420 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
421 struct amdgpu_bo *bo, bool evicted);
422 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
423 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
424 struct amdgpu_bo *bo);
425 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
426 struct amdgpu_vm *vm,
427 struct amdgpu_bo *bo);
428 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
429 struct amdgpu_bo_va *bo_va,
430 uint64_t addr, uint64_t offset,
431 uint64_t size, uint64_t flags);
432 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
433 struct amdgpu_bo_va *bo_va,
434 uint64_t addr, uint64_t offset,
435 uint64_t size, uint64_t flags);
436 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
437 struct amdgpu_bo_va *bo_va,
438 uint64_t addr);
439 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
440 struct amdgpu_vm *vm,
441 uint64_t saddr, uint64_t size);
442 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
443 uint64_t addr);
444 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
445 void amdgpu_vm_bo_del(struct amdgpu_device *adev,
446 struct amdgpu_bo_va *bo_va);
447 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
448 uint32_t fragment_size_default, unsigned max_level,
449 unsigned max_bits);
450 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
451 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
452 struct amdgpu_job *job);
453 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
454
455 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
456 struct amdgpu_task_info *task_info);
457 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
458 uint64_t addr, bool write_fault);
459
460 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
461
462 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
463 struct amdgpu_vm *vm);
464 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
465 uint64_t *gtt_mem, uint64_t *cpu_mem);
466
467 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
468 struct amdgpu_bo_vm *vmbo, bool immediate);
469 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,
470 int level, bool immediate, struct amdgpu_bo_vm **vmbo);
471 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm);
472 bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev,
473 struct amdgpu_vm *vm);
474
475 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params,
476 struct amdgpu_vm_bo_base *entry);
477 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
478 uint64_t start, uint64_t end,
479 uint64_t dst, uint64_t flags);
480 void amdgpu_vm_pt_free_work(struct work_struct *work);
481
482 #if defined(CONFIG_DEBUG_FS)
483 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
484 #endif
485
486 /**
487 * amdgpu_vm_tlb_seq - return tlb flush sequence number
488 * @vm: the amdgpu_vm structure to query
489 *
490 * Returns the tlb flush sequence number which indicates that the VM TLBs needs
491 * to be invalidated whenever the sequence number change.
492 */
amdgpu_vm_tlb_seq(struct amdgpu_vm * vm)493 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm)
494 {
495 unsigned long flags;
496 spinlock_t *lock;
497
498 /*
499 * Workaround to stop racing between the fence signaling and handling
500 * the cb. The lock is static after initially setting it up, just make
501 * sure that the dma_fence structure isn't freed up.
502 */
503 rcu_read_lock();
504 lock = vm->last_tlb_flush->lock;
505 rcu_read_unlock();
506
507 spin_lock_irqsave(lock, flags);
508 spin_unlock_irqrestore(lock, flags);
509
510 return atomic64_read(&vm->tlb_seq);
511 }
512
513 /*
514 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
515 * happens while holding this lock anywhere to prevent deadlocks when
516 * an MMU notifier runs in reclaim-FS context.
517 */
amdgpu_vm_eviction_lock(struct amdgpu_vm * vm)518 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
519 {
520 mutex_lock(&vm->eviction_lock);
521 vm->saved_flags = memalloc_noreclaim_save();
522 }
523
amdgpu_vm_eviction_trylock(struct amdgpu_vm * vm)524 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
525 {
526 if (mutex_trylock(&vm->eviction_lock)) {
527 vm->saved_flags = memalloc_noreclaim_save();
528 return true;
529 }
530 return false;
531 }
532
amdgpu_vm_eviction_unlock(struct amdgpu_vm * vm)533 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
534 {
535 memalloc_noreclaim_restore(vm->saved_flags);
536 mutex_unlock(&vm->eviction_lock);
537 }
538
539 #endif
540