1 /*
2  * AM33XX CM offset macros
3  *
4  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
5  * Vaibhav Hiremath <hvaibhav@ti.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
16 
17 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
18 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
19 
20 #include "cm.h"
21 #include "cm-regbits-33xx.h"
22 #include "prcm-common.h"
23 
24 /* CM base address */
25 #define AM33XX_CM_BASE		0x44e00000
26 
27 #define AM33XX_CM_REGADDR(inst, reg)				\
28 	AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
29 
30 /* CM instances */
31 #define AM33XX_CM_PER_MOD		0x0000
32 #define AM33XX_CM_WKUP_MOD		0x0400
33 #define AM33XX_CM_DPLL_MOD		0x0500
34 #define AM33XX_CM_MPU_MOD		0x0600
35 #define AM33XX_CM_DEVICE_MOD		0x0700
36 #define AM33XX_CM_RTC_MOD		0x0800
37 #define AM33XX_CM_GFX_MOD		0x0900
38 #define AM33XX_CM_CEFUSE_MOD		0x0A00
39 
40 /* CM.PER_CM register offsets */
41 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET		0x0000
42 #define AM33XX_CM_PER_L4LS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
43 #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET		0x0004
44 #define AM33XX_CM_PER_L3S_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
45 #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET		0x0008
46 #define AM33XX_CM_PER_L4FW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
47 #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET		0x000c
48 #define AM33XX_CM_PER_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
49 #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET		0x0028
50 #define AM33XX_CM_PER_EMIF_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
51 #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET		0x011c
52 #define AM33XX_CM_PER_L4HS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
53 #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET		0x012c
54 #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
55 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET		0x0140
56 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
57 #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET		0x0144
58 #define AM33XX_CM_PER_CPSW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
59 #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET		0x0148
60 #define AM33XX_CM_PER_LCDC_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
61 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET	0x0150
62 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
63 
64 /* CM.WKUP_CM register offsets */
65 #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
66 #define AM33XX_CM_WKUP_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
67 #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET		0x0018
68 #define AM33XX_CM_L3_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
69 #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET		0x00cc
70 #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
71 
72 /* CM.DPLL_CM register offsets */
73 #define AM33XX_CLKSEL_GFX_FCLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
74 
75 /* CM.MPU_CM register offsets */
76 #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET			0x0000
77 #define AM33XX_CM_MPU_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
78 #define AM33XX_CM_MPU_MPU_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
79 
80 /* CM.DEVICE_CM register offsets */
81 
82 /* CM.RTC_CM register offsets */
83 #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET			0x0004
84 #define AM33XX_CM_RTC_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
85 
86 /* CM.GFX_CM register offsets */
87 #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET		0x0000
88 #define AM33XX_CM_GFX_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
89 #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET	0x000c
90 #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1		AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
91 
92 /* CM.CEFUSE_CM register offsets */
93 #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET		0x0000
94 #define AM33XX_CM_CEFUSE_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
95 
96 
97 #ifndef __ASSEMBLER__
98 int am33xx_cm_init(const struct omap_prcm_init_data *data);
99 #endif /* ASSEMBLER */
100 #endif
101