1 /*
2  * This file is part of wl1271
3  *
4  * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5  * Copyright (C) 2008-2010 Nokia Corporation
6  *
7  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * version 2 as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21  * 02110-1301 USA
22  *
23  */
24 
25 #ifndef __ACX_H__
26 #define __ACX_H__
27 
28 #include "wl12xx.h"
29 #include "cmd.h"
30 
31 /*************************************************************************
32 
33     Host Interrupt Register (WiLink -> Host)
34 
35 **************************************************************************/
36 /* HW Initiated interrupt Watchdog timer expiration */
37 #define WL1271_ACX_INTR_WATCHDOG           BIT(0)
38 /* Init sequence is done (masked interrupt, detection through polling only ) */
39 #define WL1271_ACX_INTR_INIT_COMPLETE      BIT(1)
40 /* Event was entered to Event MBOX #A*/
41 #define WL1271_ACX_INTR_EVENT_A            BIT(2)
42 /* Event was entered to Event MBOX #B*/
43 #define WL1271_ACX_INTR_EVENT_B            BIT(3)
44 /* Command processing completion*/
45 #define WL1271_ACX_INTR_CMD_COMPLETE       BIT(4)
46 /* Signaling the host on HW wakeup */
47 #define WL1271_ACX_INTR_HW_AVAILABLE       BIT(5)
48 /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
49 #define WL1271_ACX_INTR_DATA               BIT(6)
50 /* Trace message on MBOX #A */
51 #define WL1271_ACX_INTR_TRACE_A            BIT(7)
52 /* Trace message on MBOX #B */
53 #define WL1271_ACX_INTR_TRACE_B            BIT(8)
54 
55 #define WL1271_ACX_INTR_ALL		   0xFFFFFFFF
56 #define WL1271_ACX_ALL_EVENTS_VECTOR       (WL1271_ACX_INTR_WATCHDOG      | \
57 					    WL1271_ACX_INTR_INIT_COMPLETE | \
58 					    WL1271_ACX_INTR_EVENT_A       | \
59 					    WL1271_ACX_INTR_EVENT_B       | \
60 					    WL1271_ACX_INTR_CMD_COMPLETE  | \
61 					    WL1271_ACX_INTR_HW_AVAILABLE  | \
62 					    WL1271_ACX_INTR_DATA)
63 
64 #define WL1271_INTR_MASK                   (WL1271_ACX_INTR_WATCHDOG     | \
65 					    WL1271_ACX_INTR_EVENT_A      | \
66 					    WL1271_ACX_INTR_EVENT_B      | \
67 					    WL1271_ACX_INTR_HW_AVAILABLE | \
68 					    WL1271_ACX_INTR_DATA)
69 
70 /* Target's information element */
71 struct acx_header {
72 	struct wl1271_cmd_header cmd;
73 
74 	/* acx (or information element) header */
75 	__le16 id;
76 
77 	/* payload length (not including headers */
78 	__le16 len;
79 } __packed;
80 
81 struct acx_error_counter {
82 	struct acx_header header;
83 
84 	/* The number of PLCP errors since the last time this */
85 	/* information element was interrogated. This field is */
86 	/* automatically cleared when it is interrogated.*/
87 	__le32 PLCP_error;
88 
89 	/* The number of FCS errors since the last time this */
90 	/* information element was interrogated. This field is */
91 	/* automatically cleared when it is interrogated.*/
92 	__le32 FCS_error;
93 
94 	/* The number of MPDUs without PLCP header errors received*/
95 	/* since the last time this information element was interrogated. */
96 	/* This field is automatically cleared when it is interrogated.*/
97 	__le32 valid_frame;
98 
99 	/* the number of missed sequence numbers in the squentially */
100 	/* values of frames seq numbers */
101 	__le32 seq_num_miss;
102 } __packed;
103 
104 enum wl12xx_role {
105 	WL1271_ROLE_STA = 0,
106 	WL1271_ROLE_IBSS,
107 	WL1271_ROLE_AP,
108 	WL1271_ROLE_DEVICE,
109 	WL1271_ROLE_P2P_CL,
110 	WL1271_ROLE_P2P_GO,
111 
112 	WL12XX_INVALID_ROLE_TYPE = 0xff
113 };
114 
115 enum wl1271_psm_mode {
116 	/* Active mode */
117 	WL1271_PSM_CAM = 0,
118 
119 	/* Power save mode */
120 	WL1271_PSM_PS = 1,
121 
122 	/* Extreme low power */
123 	WL1271_PSM_ELP = 2,
124 };
125 
126 struct acx_sleep_auth {
127 	struct acx_header header;
128 
129 	/* The sleep level authorization of the device. */
130 	/* 0 - Always active*/
131 	/* 1 - Power down mode: light / fast sleep*/
132 	/* 2 - ELP mode: Deep / Max sleep*/
133 	u8  sleep_auth;
134 	u8  padding[3];
135 } __packed;
136 
137 enum {
138 	HOSTIF_PCI_MASTER_HOST_INDIRECT,
139 	HOSTIF_PCI_MASTER_HOST_DIRECT,
140 	HOSTIF_SLAVE,
141 	HOSTIF_PKT_RING,
142 	HOSTIF_DONTCARE = 0xFF
143 };
144 
145 #define DEFAULT_UCAST_PRIORITY          0
146 #define DEFAULT_RX_Q_PRIORITY           0
147 #define DEFAULT_RXQ_PRIORITY            0 /* low 0 .. 15 high  */
148 #define DEFAULT_RXQ_TYPE                0x07    /* All frames, Data/Ctrl/Mgmt */
149 #define TRACE_BUFFER_MAX_SIZE           256
150 
151 #define  DP_RX_PACKET_RING_CHUNK_SIZE 1600
152 #define  DP_TX_PACKET_RING_CHUNK_SIZE 1600
153 #define  DP_RX_PACKET_RING_CHUNK_NUM 2
154 #define  DP_TX_PACKET_RING_CHUNK_NUM 2
155 #define  DP_TX_COMPLETE_TIME_OUT 20
156 
157 #define TX_MSDU_LIFETIME_MIN       0
158 #define TX_MSDU_LIFETIME_MAX       3000
159 #define TX_MSDU_LIFETIME_DEF       512
160 #define RX_MSDU_LIFETIME_MIN       0
161 #define RX_MSDU_LIFETIME_MAX       0xFFFFFFFF
162 #define RX_MSDU_LIFETIME_DEF       512000
163 
164 struct acx_rx_msdu_lifetime {
165 	struct acx_header header;
166 
167 	/*
168 	 * The maximum amount of time, in TU, before the
169 	 * firmware discards the MSDU.
170 	 */
171 	__le32 lifetime;
172 } __packed;
173 
174 enum acx_slot_type {
175 	SLOT_TIME_LONG = 0,
176 	SLOT_TIME_SHORT = 1,
177 	DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
178 	MAX_SLOT_TIMES = 0xFF
179 };
180 
181 #define STATION_WONE_INDEX 0
182 
183 struct acx_slot {
184 	struct acx_header header;
185 
186 	u8 role_id;
187 	u8 wone_index; /* Reserved */
188 	u8 slot_time;
189 	u8 reserved[5];
190 } __packed;
191 
192 
193 #define ACX_MC_ADDRESS_GROUP_MAX	(8)
194 #define ADDRESS_GROUP_MAX_LEN	        (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
195 
196 struct acx_dot11_grp_addr_tbl {
197 	struct acx_header header;
198 
199 	u8 role_id;
200 	u8 enabled;
201 	u8 num_groups;
202 	u8 pad[1];
203 	u8 mac_table[ADDRESS_GROUP_MAX_LEN];
204 } __packed;
205 
206 struct acx_rx_timeout {
207 	struct acx_header header;
208 
209 	u8 role_id;
210 	u8 reserved;
211 	__le16 ps_poll_timeout;
212 	__le16 upsd_timeout;
213 	u8 padding[2];
214 } __packed;
215 
216 struct acx_rts_threshold {
217 	struct acx_header header;
218 
219 	u8 role_id;
220 	u8 reserved;
221 	__le16 threshold;
222 } __packed;
223 
224 struct acx_beacon_filter_option {
225 	struct acx_header header;
226 
227 	u8 role_id;
228 	u8 enable;
229 	/*
230 	 * The number of beacons without the unicast TIM
231 	 * bit set that the firmware buffers before
232 	 * signaling the host about ready frames.
233 	 * When set to 0 and the filter is enabled, beacons
234 	 * without the unicast TIM bit set are dropped.
235 	 */
236 	u8 max_num_beacons;
237 	u8 pad[1];
238 } __packed;
239 
240 /*
241  * ACXBeaconFilterEntry (not 221)
242  * Byte Offset     Size (Bytes)    Definition
243  * ===========     ============    ==========
244  * 0               1               IE identifier
245  * 1               1               Treatment bit mask
246  *
247  * ACXBeaconFilterEntry (221)
248  * Byte Offset     Size (Bytes)    Definition
249  * ===========     ============    ==========
250  * 0               1               IE identifier
251  * 1               1               Treatment bit mask
252  * 2               3               OUI
253  * 5               1               Type
254  * 6               2               Version
255  *
256  *
257  * Treatment bit mask - The information element handling:
258  * bit 0 - The information element is compared and transferred
259  * in case of change.
260  * bit 1 - The information element is transferred to the host
261  * with each appearance or disappearance.
262  * Note that both bits can be set at the same time.
263  */
264 #define	BEACON_FILTER_TABLE_MAX_IE_NUM		       (32)
265 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
266 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE	       (2)
267 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
268 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
269 			    BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
270 			   (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
271 			    BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
272 
273 struct acx_beacon_filter_ie_table {
274 	struct acx_header header;
275 
276 	u8 role_id;
277 	u8 num_ie;
278 	u8 pad[2];
279 	u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
280 } __packed;
281 
282 struct acx_conn_monit_params {
283        struct acx_header header;
284 
285 	   u8 role_id;
286 	   u8 padding[3];
287        __le32 synch_fail_thold; /* number of beacons missed */
288        __le32 bss_lose_timeout; /* number of TU's from synch fail */
289 } __packed;
290 
291 struct acx_bt_wlan_coex {
292 	struct acx_header header;
293 
294 	u8 enable;
295 	u8 pad[3];
296 } __packed;
297 
298 struct acx_bt_wlan_coex_param {
299 	struct acx_header header;
300 
301 	__le32 params[CONF_SG_PARAMS_MAX];
302 	u8 param_idx;
303 	u8 padding[3];
304 } __packed;
305 
306 struct acx_dco_itrim_params {
307 	struct acx_header header;
308 
309 	u8 enable;
310 	u8 padding[3];
311 	__le32 timeout;
312 } __packed;
313 
314 struct acx_energy_detection {
315 	struct acx_header header;
316 
317 	/* The RX Clear Channel Assessment threshold in the PHY */
318 	__le16 rx_cca_threshold;
319 	u8 tx_energy_detection;
320 	u8 pad;
321 } __packed;
322 
323 struct acx_beacon_broadcast {
324 	struct acx_header header;
325 
326 	u8 role_id;
327 	/* Enables receiving of broadcast packets in PS mode */
328 	u8 rx_broadcast_in_ps;
329 
330 	__le16 beacon_rx_timeout;
331 	__le16 broadcast_timeout;
332 
333 	/* Consecutive PS Poll failures before updating the host */
334 	u8 ps_poll_threshold;
335 	u8 pad[1];
336 } __packed;
337 
338 struct acx_event_mask {
339 	struct acx_header header;
340 
341 	__le32 event_mask;
342 	__le32 high_event_mask; /* Unused */
343 } __packed;
344 
345 #define SCAN_PASSIVE		BIT(0)
346 #define SCAN_5GHZ_BAND		BIT(1)
347 #define SCAN_TRIGGERED		BIT(2)
348 #define SCAN_PRIORITY_HIGH	BIT(3)
349 
350 /* When set, disable HW encryption */
351 #define DF_ENCRYPTION_DISABLE      0x01
352 #define DF_SNIFF_MODE_ENABLE       0x80
353 
354 struct acx_feature_config {
355 	struct acx_header header;
356 
357 	u8 role_id;
358 	u8 padding[3];
359 	__le32 options;
360 	__le32 data_flow_options;
361 } __packed;
362 
363 struct acx_current_tx_power {
364 	struct acx_header header;
365 
366 	u8  role_id;
367 	u8  current_tx_power;
368 	u8  padding[2];
369 } __packed;
370 
371 struct acx_wake_up_condition {
372 	struct acx_header header;
373 
374 	u8 role_id;
375 	u8 wake_up_event; /* Only one bit can be set */
376 	u8 listen_interval;
377 	u8 pad[1];
378 } __packed;
379 
380 struct acx_aid {
381 	struct acx_header header;
382 
383 	/*
384 	 * To be set when associated with an AP.
385 	 */
386 	u8 role_id;
387 	u8 reserved;
388 	__le16 aid;
389 } __packed;
390 
391 enum acx_preamble_type {
392 	ACX_PREAMBLE_LONG = 0,
393 	ACX_PREAMBLE_SHORT = 1
394 };
395 
396 struct acx_preamble {
397 	struct acx_header header;
398 
399 	/*
400 	 * When set, the WiLink transmits the frames with a short preamble and
401 	 * when cleared, the WiLink transmits the frames with a long preamble.
402 	 */
403 	u8 role_id;
404 	u8 preamble;
405 	u8 padding[2];
406 } __packed;
407 
408 enum acx_ctsprotect_type {
409 	CTSPROTECT_DISABLE = 0,
410 	CTSPROTECT_ENABLE = 1
411 };
412 
413 struct acx_ctsprotect {
414 	struct acx_header header;
415 	u8 role_id;
416 	u8 ctsprotect;
417 	u8 padding[2];
418 } __packed;
419 
420 struct acx_tx_statistics {
421 	__le32 internal_desc_overflow;
422 }  __packed;
423 
424 struct acx_rx_statistics {
425 	__le32 out_of_mem;
426 	__le32 hdr_overflow;
427 	__le32 hw_stuck;
428 	__le32 dropped;
429 	__le32 fcs_err;
430 	__le32 xfr_hint_trig;
431 	__le32 path_reset;
432 	__le32 reset_counter;
433 } __packed;
434 
435 struct acx_dma_statistics {
436 	__le32 rx_requested;
437 	__le32 rx_errors;
438 	__le32 tx_requested;
439 	__le32 tx_errors;
440 }  __packed;
441 
442 struct acx_isr_statistics {
443 	/* host command complete */
444 	__le32 cmd_cmplt;
445 
446 	/* fiqisr() */
447 	__le32 fiqs;
448 
449 	/* (INT_STS_ND & INT_TRIG_RX_HEADER) */
450 	__le32 rx_headers;
451 
452 	/* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
453 	__le32 rx_completes;
454 
455 	/* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
456 	__le32 rx_mem_overflow;
457 
458 	/* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
459 	__le32 rx_rdys;
460 
461 	/* irqisr() */
462 	__le32 irqs;
463 
464 	/* (INT_STS_ND & INT_TRIG_TX_PROC) */
465 	__le32 tx_procs;
466 
467 	/* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
468 	__le32 decrypt_done;
469 
470 	/* (INT_STS_ND & INT_TRIG_DMA0) */
471 	__le32 dma0_done;
472 
473 	/* (INT_STS_ND & INT_TRIG_DMA1) */
474 	__le32 dma1_done;
475 
476 	/* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
477 	__le32 tx_exch_complete;
478 
479 	/* (INT_STS_ND & INT_TRIG_COMMAND) */
480 	__le32 commands;
481 
482 	/* (INT_STS_ND & INT_TRIG_RX_PROC) */
483 	__le32 rx_procs;
484 
485 	/* (INT_STS_ND & INT_TRIG_PM_802) */
486 	__le32 hw_pm_mode_changes;
487 
488 	/* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
489 	__le32 host_acknowledges;
490 
491 	/* (INT_STS_ND & INT_TRIG_PM_PCI) */
492 	__le32 pci_pm;
493 
494 	/* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
495 	__le32 wakeups;
496 
497 	/* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
498 	__le32 low_rssi;
499 } __packed;
500 
501 struct acx_wep_statistics {
502 	/* WEP address keys configured */
503 	__le32 addr_key_count;
504 
505 	/* default keys configured */
506 	__le32 default_key_count;
507 
508 	__le32 reserved;
509 
510 	/* number of times that WEP key not found on lookup */
511 	__le32 key_not_found;
512 
513 	/* number of times that WEP key decryption failed */
514 	__le32 decrypt_fail;
515 
516 	/* WEP packets decrypted */
517 	__le32 packets;
518 
519 	/* WEP decrypt interrupts */
520 	__le32 interrupt;
521 } __packed;
522 
523 #define ACX_MISSED_BEACONS_SPREAD 10
524 
525 struct acx_pwr_statistics {
526 	/* the amount of enters into power save mode (both PD & ELP) */
527 	__le32 ps_enter;
528 
529 	/* the amount of enters into ELP mode */
530 	__le32 elp_enter;
531 
532 	/* the amount of missing beacon interrupts to the host */
533 	__le32 missing_bcns;
534 
535 	/* the amount of wake on host-access times */
536 	__le32 wake_on_host;
537 
538 	/* the amount of wake on timer-expire */
539 	__le32 wake_on_timer_exp;
540 
541 	/* the number of packets that were transmitted with PS bit set */
542 	__le32 tx_with_ps;
543 
544 	/* the number of packets that were transmitted with PS bit clear */
545 	__le32 tx_without_ps;
546 
547 	/* the number of received beacons */
548 	__le32 rcvd_beacons;
549 
550 	/* the number of entering into PowerOn (power save off) */
551 	__le32 power_save_off;
552 
553 	/* the number of entries into power save mode */
554 	__le16 enable_ps;
555 
556 	/*
557 	 * the number of exits from power save, not including failed PS
558 	 * transitions
559 	 */
560 	__le16 disable_ps;
561 
562 	/*
563 	 * the number of times the TSF counter was adjusted because
564 	 * of drift
565 	 */
566 	__le32 fix_tsf_ps;
567 
568 	/* Gives statistics about the spread continuous missed beacons.
569 	 * The 16 LSB are dedicated for the PS mode.
570 	 * The 16 MSB are dedicated for the PS mode.
571 	 * cont_miss_bcns_spread[0] - single missed beacon.
572 	 * cont_miss_bcns_spread[1] - two continuous missed beacons.
573 	 * cont_miss_bcns_spread[2] - three continuous missed beacons.
574 	 * ...
575 	 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
576 	*/
577 	__le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
578 
579 	/* the number of beacons in awake mode */
580 	__le32 rcvd_awake_beacons;
581 } __packed;
582 
583 struct acx_mic_statistics {
584 	__le32 rx_pkts;
585 	__le32 calc_failure;
586 } __packed;
587 
588 struct acx_aes_statistics {
589 	__le32 encrypt_fail;
590 	__le32 decrypt_fail;
591 	__le32 encrypt_packets;
592 	__le32 decrypt_packets;
593 	__le32 encrypt_interrupt;
594 	__le32 decrypt_interrupt;
595 } __packed;
596 
597 struct acx_event_statistics {
598 	__le32 heart_beat;
599 	__le32 calibration;
600 	__le32 rx_mismatch;
601 	__le32 rx_mem_empty;
602 	__le32 rx_pool;
603 	__le32 oom_late;
604 	__le32 phy_transmit_error;
605 	__le32 tx_stuck;
606 } __packed;
607 
608 struct acx_ps_statistics {
609 	__le32 pspoll_timeouts;
610 	__le32 upsd_timeouts;
611 	__le32 upsd_max_sptime;
612 	__le32 upsd_max_apturn;
613 	__le32 pspoll_max_apturn;
614 	__le32 pspoll_utilization;
615 	__le32 upsd_utilization;
616 } __packed;
617 
618 struct acx_rxpipe_statistics {
619 	__le32 rx_prep_beacon_drop;
620 	__le32 descr_host_int_trig_rx_data;
621 	__le32 beacon_buffer_thres_host_int_trig_rx_data;
622 	__le32 missed_beacon_host_int_trig_rx_data;
623 	__le32 tx_xfr_host_int_trig_rx_data;
624 } __packed;
625 
626 struct acx_statistics {
627 	struct acx_header header;
628 
629 	struct acx_tx_statistics tx;
630 	struct acx_rx_statistics rx;
631 	struct acx_dma_statistics dma;
632 	struct acx_isr_statistics isr;
633 	struct acx_wep_statistics wep;
634 	struct acx_pwr_statistics pwr;
635 	struct acx_aes_statistics aes;
636 	struct acx_mic_statistics mic;
637 	struct acx_event_statistics event;
638 	struct acx_ps_statistics ps;
639 	struct acx_rxpipe_statistics rxpipe;
640 } __packed;
641 
642 struct acx_rate_class {
643 	__le32 enabled_rates;
644 	u8 short_retry_limit;
645 	u8 long_retry_limit;
646 	u8 aflags;
647 	u8 reserved;
648 };
649 
650 struct acx_rate_policy {
651 	struct acx_header header;
652 
653 	__le32 rate_policy_idx;
654 	struct acx_rate_class rate_policy;
655 } __packed;
656 
657 struct acx_ac_cfg {
658 	struct acx_header header;
659 	u8 role_id;
660 	u8 ac;
661 	u8 aifsn;
662 	u8 cw_min;
663 	__le16 cw_max;
664 	__le16 tx_op_limit;
665 } __packed;
666 
667 struct acx_tid_config {
668 	struct acx_header header;
669 	u8 role_id;
670 	u8 queue_id;
671 	u8 channel_type;
672 	u8 tsid;
673 	u8 ps_scheme;
674 	u8 ack_policy;
675 	u8 padding[2];
676 	__le32 apsd_conf[2];
677 } __packed;
678 
679 struct acx_frag_threshold {
680 	struct acx_header header;
681 	__le16 frag_threshold;
682 	u8 padding[2];
683 } __packed;
684 
685 struct acx_tx_config_options {
686 	struct acx_header header;
687 	__le16 tx_compl_timeout;     /* msec */
688 	__le16 tx_compl_threshold;   /* number of packets */
689 } __packed;
690 
691 struct wl12xx_acx_config_memory {
692 	struct acx_header header;
693 
694 	u8 rx_mem_block_num;
695 	u8 tx_min_mem_block_num;
696 	u8 num_stations;
697 	u8 num_ssid_profiles;
698 	__le32 total_tx_descriptors;
699 	u8 dyn_mem_enable;
700 	u8 tx_free_req;
701 	u8 rx_free_req;
702 	u8 tx_min;
703 	u8 fwlog_blocks;
704 	u8 padding[3];
705 } __packed;
706 
707 struct wl1271_acx_mem_map {
708 	struct acx_header header;
709 
710 	__le32 code_start;
711 	__le32 code_end;
712 
713 	__le32 wep_defkey_start;
714 	__le32 wep_defkey_end;
715 
716 	__le32 sta_table_start;
717 	__le32 sta_table_end;
718 
719 	__le32 packet_template_start;
720 	__le32 packet_template_end;
721 
722 	/* Address of the TX result interface (control block) */
723 	__le32 tx_result;
724 	__le32 tx_result_queue_start;
725 
726 	__le32 queue_memory_start;
727 	__le32 queue_memory_end;
728 
729 	__le32 packet_memory_pool_start;
730 	__le32 packet_memory_pool_end;
731 
732 	__le32 debug_buffer1_start;
733 	__le32 debug_buffer1_end;
734 
735 	__le32 debug_buffer2_start;
736 	__le32 debug_buffer2_end;
737 
738 	/* Number of blocks FW allocated for TX packets */
739 	__le32 num_tx_mem_blocks;
740 
741 	/* Number of blocks FW allocated for RX packets */
742 	__le32 num_rx_mem_blocks;
743 
744 	/* the following 4 fields are valid in SLAVE mode only */
745 	u8 *tx_cbuf;
746 	u8 *rx_cbuf;
747 	__le32 rx_ctrl;
748 	__le32 tx_ctrl;
749 } __packed;
750 
751 struct wl1271_acx_rx_config_opt {
752 	struct acx_header header;
753 
754 	__le16 mblk_threshold;
755 	__le16 threshold;
756 	__le16 timeout;
757 	u8 queue_type;
758 	u8 reserved;
759 } __packed;
760 
761 
762 struct wl1271_acx_bet_enable {
763 	struct acx_header header;
764 
765 	u8 role_id;
766 	u8 enable;
767 	u8 max_consecutive;
768 	u8 padding[1];
769 } __packed;
770 
771 #define ACX_IPV4_VERSION 4
772 #define ACX_IPV6_VERSION 6
773 #define ACX_IPV4_ADDR_SIZE 4
774 
775 /* bitmap of enabled arp_filter features */
776 #define ACX_ARP_FILTER_ARP_FILTERING	BIT(0)
777 #define ACX_ARP_FILTER_AUTO_ARP		BIT(1)
778 
779 struct wl1271_acx_arp_filter {
780 	struct acx_header header;
781 	u8 role_id;
782 	u8 version;         /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
783 	u8 enable;          /* bitmap of enabled ARP filtering features */
784 	u8 padding[1];
785 	u8 address[16];     /* The configured device IP address - all ARP
786 			       requests directed to this IP address will pass
787 			       through. For IPv4, the first four bytes are
788 			       used. */
789 } __packed;
790 
791 struct wl1271_acx_pm_config {
792 	struct acx_header header;
793 
794 	__le32 host_clk_settling_time;
795 	u8 host_fast_wakeup_support;
796 	u8 padding[3];
797 } __packed;
798 
799 struct wl1271_acx_keep_alive_mode {
800 	struct acx_header header;
801 
802 	u8 role_id;
803 	u8 enabled;
804 	u8 padding[2];
805 } __packed;
806 
807 enum {
808 	ACX_KEEP_ALIVE_NO_TX = 0,
809 	ACX_KEEP_ALIVE_PERIOD_ONLY
810 };
811 
812 enum {
813 	ACX_KEEP_ALIVE_TPL_INVALID = 0,
814 	ACX_KEEP_ALIVE_TPL_VALID
815 };
816 
817 struct wl1271_acx_keep_alive_config {
818 	struct acx_header header;
819 
820 	u8 role_id;
821 	u8 index;
822 	u8 tpl_validation;
823 	u8 trigger;
824 	__le32 period;
825 } __packed;
826 
827 #define HOST_IF_CFG_RX_FIFO_ENABLE     BIT(0)
828 #define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1)
829 #define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3)
830 
831 struct wl1271_acx_host_config_bitmap {
832 	struct acx_header header;
833 
834 	__le32 host_cfg_bitmap;
835 } __packed;
836 
837 enum {
838 	WL1271_ACX_TRIG_TYPE_LEVEL = 0,
839 	WL1271_ACX_TRIG_TYPE_EDGE,
840 };
841 
842 enum {
843 	WL1271_ACX_TRIG_DIR_LOW = 0,
844 	WL1271_ACX_TRIG_DIR_HIGH,
845 	WL1271_ACX_TRIG_DIR_BIDIR,
846 };
847 
848 enum {
849 	WL1271_ACX_TRIG_ENABLE = 1,
850 	WL1271_ACX_TRIG_DISABLE,
851 };
852 
853 enum {
854 	WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0,
855 	WL1271_ACX_TRIG_METRIC_RSSI_DATA,
856 	WL1271_ACX_TRIG_METRIC_SNR_BEACON,
857 	WL1271_ACX_TRIG_METRIC_SNR_DATA,
858 };
859 
860 enum {
861 	WL1271_ACX_TRIG_IDX_RSSI = 0,
862 	WL1271_ACX_TRIG_COUNT = 8,
863 };
864 
865 struct wl1271_acx_rssi_snr_trigger {
866 	struct acx_header header;
867 
868 	u8 role_id;
869 	u8 metric;
870 	u8 type;
871 	u8 dir;
872 	__le16 threshold;
873 	__le16 pacing; /* 0 - 60000 ms */
874 	u8 hysteresis;
875 	u8 index;
876 	u8 enable;
877 	u8 padding[1];
878 };
879 
880 struct wl1271_acx_rssi_snr_avg_weights {
881 	struct acx_header header;
882 
883 	u8 role_id;
884 	u8 padding[3];
885 	u8 rssi_beacon;
886 	u8 rssi_data;
887 	u8 snr_beacon;
888 	u8 snr_data;
889 };
890 
891 
892 /* special capability bit (not employed by the 802.11n spec) */
893 #define WL12XX_HT_CAP_HT_OPERATION BIT(16)
894 
895 /*
896  * ACX_PEER_HT_CAP
897  * Configure HT capabilities - declare the capabilities of the peer
898  * we are connected to.
899  */
900 struct wl1271_acx_ht_capabilities {
901 	struct acx_header header;
902 
903 	/* bitmask of capability bits supported by the peer */
904 	__le32 ht_capabilites;
905 
906 	/* Indicates to which link these capabilities apply. */
907 	u8 hlid;
908 
909 	/*
910 	 * This the maximum A-MPDU length supported by the AP. The FW may not
911 	 * exceed this length when sending A-MPDUs
912 	 */
913 	u8 ampdu_max_length;
914 
915 	/* This is the minimal spacing required when sending A-MPDUs to the AP*/
916 	u8 ampdu_min_spacing;
917 
918 	u8 padding;
919 } __packed;
920 
921 /*
922  * ACX_HT_BSS_OPERATION
923  * Configure HT capabilities - AP rules for behavior in the BSS.
924  */
925 struct wl1271_acx_ht_information {
926 	struct acx_header header;
927 
928 	u8 role_id;
929 
930 	/* Values: 0 - RIFS not allowed, 1 - RIFS allowed */
931 	u8 rifs_mode;
932 
933 	/* Values: 0 - 3 like in spec */
934 	u8 ht_protection;
935 
936 	/* Values: 0 - GF protection not required, 1 - GF protection required */
937 	u8 gf_protection;
938 
939 	/*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/
940 	u8 ht_tx_burst_limit;
941 
942 	/*
943 	 * Values: 0 - Dual CTS protection not required,
944 	 *         1 - Dual CTS Protection required
945 	 * Note: When this value is set to 1 FW will protect all TXOP with RTS
946 	 * frame and will not use CTS-to-self regardless of the value of the
947 	 * ACX_CTS_PROTECTION information element
948 	 */
949 	u8 dual_cts_protection;
950 
951 	u8 padding[2];
952 } __packed;
953 
954 #define RX_BA_MAX_SESSIONS 2
955 
956 struct wl1271_acx_ba_initiator_policy {
957 	struct acx_header header;
958 
959 	/* Specifies role Id, Range 0-7, 0xFF means ANY role. */
960 	u8 role_id;
961 
962 	/*
963 	 * Per TID setting for allowing TX BA. Set a bit to 1 to allow
964 	 * TX BA sessions for the corresponding TID.
965 	 */
966 	u8 tid_bitmap;
967 
968 	/* Windows size in number of packets */
969 	u8 win_size;
970 
971 	u8 padding1[1];
972 
973 	/* As initiator inactivity timeout in time units(TU) of 1024us */
974 	u16 inactivity_timeout;
975 
976 	u8 padding[2];
977 } __packed;
978 
979 struct wl1271_acx_ba_receiver_setup {
980 	struct acx_header header;
981 
982 	/* Specifies link id, range 0-31 */
983 	u8 hlid;
984 
985 	u8 tid;
986 
987 	u8 enable;
988 
989 	/* Windows size in number of packets */
990 	u8 win_size;
991 
992 	/* BA session starting sequence number.  RANGE 0-FFF */
993 	u16 ssn;
994 
995 	u8 padding[2];
996 } __packed;
997 
998 struct wl12xx_acx_fw_tsf_information {
999 	struct acx_header header;
1000 
1001 	u8 role_id;
1002 	u8 padding1[3];
1003 	__le32 current_tsf_high;
1004 	__le32 current_tsf_low;
1005 	__le32 last_bttt_high;
1006 	__le32 last_tbtt_low;
1007 	u8 last_dtim_count;
1008 	u8 padding2[3];
1009 } __packed;
1010 
1011 struct wl1271_acx_ps_rx_streaming {
1012 	struct acx_header header;
1013 
1014 	u8 role_id;
1015 	u8 tid;
1016 	u8 enable;
1017 
1018 	/* interval between triggers (10-100 msec) */
1019 	u8 period;
1020 
1021 	/* timeout before first trigger (0-200 msec) */
1022 	u8 timeout;
1023 	u8 padding[3];
1024 } __packed;
1025 
1026 struct wl1271_acx_ap_max_tx_retry {
1027 	struct acx_header header;
1028 
1029 	u8 role_id;
1030 	u8 padding_1;
1031 
1032 	/*
1033 	 * the number of frames transmission failures before
1034 	 * issuing the aging event.
1035 	 */
1036 	__le16 max_tx_retry;
1037 } __packed;
1038 
1039 struct wl1271_acx_config_ps {
1040 	struct acx_header header;
1041 
1042 	u8 exit_retries;
1043 	u8 enter_retries;
1044 	u8 padding[2];
1045 	__le32 null_data_rate;
1046 } __packed;
1047 
1048 struct wl1271_acx_inconnection_sta {
1049 	struct acx_header header;
1050 
1051 	u8 addr[ETH_ALEN];
1052 	u8 padding1[2];
1053 } __packed;
1054 
1055 /*
1056  * ACX_FM_COEX_CFG
1057  * set the FM co-existence parameters.
1058  */
1059 struct wl1271_acx_fm_coex {
1060 	struct acx_header header;
1061 	/* enable(1) / disable(0) the FM Coex feature */
1062 	u8 enable;
1063 	/*
1064 	 * Swallow period used in COEX PLL swallowing mechanism.
1065 	 * 0xFF = use FW default
1066 	 */
1067 	u8 swallow_period;
1068 	/*
1069 	 * The N divider used in COEX PLL swallowing mechanism for Fref of
1070 	 * 38.4/19.2 Mhz. 0xFF = use FW default
1071 	 */
1072 	u8 n_divider_fref_set_1;
1073 	/*
1074 	 * The N divider used in COEX PLL swallowing mechanism for Fref of
1075 	 * 26/52 Mhz. 0xFF = use FW default
1076 	 */
1077 	u8 n_divider_fref_set_2;
1078 	/*
1079 	 * The M divider used in COEX PLL swallowing mechanism for Fref of
1080 	 * 38.4/19.2 Mhz. 0xFFFF = use FW default
1081 	 */
1082 	__le16 m_divider_fref_set_1;
1083 	/*
1084 	 * The M divider used in COEX PLL swallowing mechanism for Fref of
1085 	 * 26/52 Mhz. 0xFFFF = use FW default
1086 	 */
1087 	__le16 m_divider_fref_set_2;
1088 	/*
1089 	 * The time duration in uSec required for COEX PLL to stabilize.
1090 	 * 0xFFFFFFFF = use FW default
1091 	 */
1092 	__le32 coex_pll_stabilization_time;
1093 	/*
1094 	 * The time duration in uSec required for LDO to stabilize.
1095 	 * 0xFFFFFFFF = use FW default
1096 	 */
1097 	__le16 ldo_stabilization_time;
1098 	/*
1099 	 * The disturbed frequency band margin around the disturbed frequency
1100 	 * center (single sided).
1101 	 * For example, if 2 is configured, the following channels will be
1102 	 * considered disturbed channel:
1103 	 *   80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH
1104 	 * 0xFF = use FW default
1105 	 */
1106 	u8 fm_disturbed_band_margin;
1107 	/*
1108 	 * The swallow clock difference of the swallowing mechanism.
1109 	 * 0xFF = use FW default
1110 	 */
1111 	u8 swallow_clk_diff;
1112 } __packed;
1113 
1114 #define ACX_RATE_MGMT_ALL_PARAMS 0xff
1115 struct wl12xx_acx_set_rate_mgmt_params {
1116 	struct acx_header header;
1117 
1118 	u8 index; /* 0xff to configure all params */
1119 	u8 padding1;
1120 	__le16 rate_retry_score;
1121 	__le16 per_add;
1122 	__le16 per_th1;
1123 	__le16 per_th2;
1124 	__le16 max_per;
1125 	u8 inverse_curiosity_factor;
1126 	u8 tx_fail_low_th;
1127 	u8 tx_fail_high_th;
1128 	u8 per_alpha_shift;
1129 	u8 per_add_shift;
1130 	u8 per_beta1_shift;
1131 	u8 per_beta2_shift;
1132 	u8 rate_check_up;
1133 	u8 rate_check_down;
1134 	u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES];
1135 	u8 padding2[2];
1136 } __packed;
1137 
1138 struct wl12xx_acx_config_hangover {
1139 	struct acx_header header;
1140 
1141 	__le32 recover_time;
1142 	u8 hangover_period;
1143 	u8 dynamic_mode;
1144 	u8 early_termination_mode;
1145 	u8 max_period;
1146 	u8 min_period;
1147 	u8 increase_delta;
1148 	u8 decrease_delta;
1149 	u8 quiet_time;
1150 	u8 increase_time;
1151 	u8 window_size;
1152 	u8 padding[2];
1153 } __packed;
1154 
1155 enum {
1156 	ACX_WAKE_UP_CONDITIONS           = 0x0000,
1157 	ACX_MEM_CFG                      = 0x0001,
1158 	ACX_SLOT                         = 0x0002,
1159 	ACX_AC_CFG                       = 0x0003,
1160 	ACX_MEM_MAP                      = 0x0004,
1161 	ACX_AID                          = 0x0005,
1162 	ACX_MEDIUM_USAGE                 = 0x0006,
1163 	ACX_STATISTICS                   = 0x0007,
1164 	ACX_PWR_CONSUMPTION_STATISTICS   = 0x0008,
1165 	ACX_TID_CFG                      = 0x0009,
1166 	ACX_PS_RX_STREAMING              = 0x000A,
1167 	ACX_BEACON_FILTER_OPT            = 0x000B,
1168 	ACX_NOISE_HIST                   = 0x000C,
1169 	ACX_HDK_VERSION                  = 0x000D,
1170 	ACX_PD_THRESHOLD                 = 0x000E,
1171 	ACX_TX_CONFIG_OPT                = 0x000F,
1172 	ACX_CCA_THRESHOLD                = 0x0010,
1173 	ACX_EVENT_MBOX_MASK              = 0x0011,
1174 	ACX_CONN_MONIT_PARAMS            = 0x0012,
1175 	ACX_DISABLE_BROADCASTS           = 0x0013,
1176 	ACX_BCN_DTIM_OPTIONS             = 0x0014,
1177 	ACX_SG_ENABLE                    = 0x0015,
1178 	ACX_SG_CFG                       = 0x0016,
1179 	ACX_FM_COEX_CFG                  = 0x0017,
1180 	ACX_BEACON_FILTER_TABLE          = 0x0018,
1181 	ACX_ARP_IP_FILTER                = 0x0019,
1182 	ACX_ROAMING_STATISTICS_TBL       = 0x001A,
1183 	ACX_RATE_POLICY                  = 0x001B,
1184 	ACX_CTS_PROTECTION               = 0x001C,
1185 	ACX_SLEEP_AUTH                   = 0x001D,
1186 	ACX_PREAMBLE_TYPE                = 0x001E,
1187 	ACX_ERROR_CNT                    = 0x001F,
1188 	ACX_IBSS_FILTER                  = 0x0020,
1189 	ACX_SERVICE_PERIOD_TIMEOUT       = 0x0021,
1190 	ACX_TSF_INFO                     = 0x0022,
1191 	ACX_CONFIG_PS_WMM                = 0x0023,
1192 	ACX_ENABLE_RX_DATA_FILTER        = 0x0024,
1193 	ACX_SET_RX_DATA_FILTER           = 0x0025,
1194 	ACX_GET_DATA_FILTER_STATISTICS   = 0x0026,
1195 	ACX_RX_CONFIG_OPT                = 0x0027,
1196 	ACX_FRAG_CFG                     = 0x0028,
1197 	ACX_BET_ENABLE                   = 0x0029,
1198 	ACX_RSSI_SNR_TRIGGER             = 0x002A,
1199 	ACX_RSSI_SNR_WEIGHTS             = 0x002B,
1200 	ACX_KEEP_ALIVE_MODE              = 0x002C,
1201 	ACX_SET_KEEP_ALIVE_CONFIG        = 0x002D,
1202 	ACX_BA_SESSION_INIT_POLICY       = 0x002E,
1203 	ACX_BA_SESSION_RX_SETUP          = 0x002F,
1204 	ACX_PEER_HT_CAP                  = 0x0030,
1205 	ACX_HT_BSS_OPERATION             = 0x0031,
1206 	ACX_COEX_ACTIVITY                = 0x0032,
1207 	ACX_BURST_MODE                   = 0x0033,
1208 	ACX_SET_RATE_MGMT_PARAMS         = 0x0034,
1209 	ACX_GET_RATE_MGMT_PARAMS         = 0x0035,
1210 	ACX_SET_RATE_ADAPT_PARAMS        = 0x0036,
1211 	ACX_SET_DCO_ITRIM_PARAMS         = 0x0037,
1212 	ACX_GEN_FW_CMD                   = 0x0038,
1213 	ACX_HOST_IF_CFG_BITMAP           = 0x0039,
1214 	ACX_MAX_TX_FAILURE               = 0x003A,
1215 	ACX_UPDATE_INCONNECTION_STA_LIST = 0x003B,
1216 	DOT11_RX_MSDU_LIFE_TIME          = 0x003C,
1217 	DOT11_CUR_TX_PWR                 = 0x003D,
1218 	DOT11_RTS_THRESHOLD              = 0x003E,
1219 	DOT11_GROUP_ADDRESS_TBL          = 0x003F,
1220 	ACX_PM_CONFIG                    = 0x0040,
1221 	ACX_CONFIG_PS                    = 0x0041,
1222 	ACX_CONFIG_HANGOVER              = 0x0042,
1223 	ACX_FEATURE_CFG                  = 0x0043,
1224 	ACX_PROTECTION_CFG               = 0x0044,
1225 };
1226 
1227 
1228 int wl1271_acx_wake_up_conditions(struct wl1271 *wl,
1229 				  struct wl12xx_vif *wlvif,
1230 				  u8 wake_up_event, u8 listen_interval);
1231 int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1232 int wl1271_acx_tx_power(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1233 			int power);
1234 int wl1271_acx_feature_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1235 int wl1271_acx_mem_map(struct wl1271 *wl,
1236 		       struct acx_header *mem_map, size_t len);
1237 int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
1238 int wl1271_acx_slot(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1239 		    enum acx_slot_type slot_time);
1240 int wl1271_acx_group_address_tbl(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1241 				 bool enable, void *mc_list, u32 mc_list_len);
1242 int wl1271_acx_service_period_timeout(struct wl1271 *wl,
1243 				      struct wl12xx_vif *wlvif);
1244 int wl1271_acx_rts_threshold(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1245 			     u32 rts_threshold);
1246 int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
1247 int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1248 				 bool enable_filter);
1249 int wl1271_acx_beacon_filter_table(struct wl1271 *wl,
1250 				   struct wl12xx_vif *wlvif);
1251 int wl1271_acx_conn_monit_params(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1252 				 bool enable);
1253 int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable);
1254 int wl12xx_acx_sg_cfg(struct wl1271 *wl);
1255 int wl1271_acx_cca_threshold(struct wl1271 *wl);
1256 int wl1271_acx_bcn_dtim_options(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1257 int wl1271_acx_aid(struct wl1271 *wl, struct wl12xx_vif *wlvif, u16 aid);
1258 int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1259 int wl1271_acx_set_preamble(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1260 			    enum acx_preamble_type preamble);
1261 int wl1271_acx_cts_protect(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1262 			   enum acx_ctsprotect_type ctsprotect);
1263 int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats);
1264 int wl1271_acx_sta_rate_policies(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1265 int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c,
1266 		      u8 idx);
1267 int wl1271_acx_ac_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1268 		      u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop);
1269 int wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1270 		       u8 queue_id, u8 channel_type,
1271 		       u8 tsid, u8 ps_scheme, u8 ack_policy,
1272 		       u32 apsd_conf0, u32 apsd_conf1);
1273 int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold);
1274 int wl1271_acx_tx_config_options(struct wl1271 *wl);
1275 int wl12xx_acx_mem_cfg(struct wl1271 *wl);
1276 int wl1271_acx_init_mem_config(struct wl1271 *wl);
1277 int wl1271_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap);
1278 int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1279 int wl1271_acx_smart_reflex(struct wl1271 *wl);
1280 int wl1271_acx_bet_enable(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1281 			  bool enable);
1282 int wl1271_acx_arp_ip_filter(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1283 			     u8 enable, __be32 address);
1284 int wl1271_acx_pm_config(struct wl1271 *wl);
1285 int wl1271_acx_keep_alive_mode(struct wl1271 *wl, struct wl12xx_vif *vif,
1286 			       bool enable);
1287 int wl1271_acx_keep_alive_config(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1288 				 u8 index, u8 tpl_valid);
1289 int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1290 				bool enable, s16 thold, u8 hyst);
1291 int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl,
1292 				    struct wl12xx_vif *wlvif);
1293 int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
1294 				    struct ieee80211_sta_ht_cap *ht_cap,
1295 				    bool allow_ht_operation, u8 hlid);
1296 int wl1271_acx_set_ht_information(struct wl1271 *wl,
1297 				   struct wl12xx_vif *wlvif,
1298 				   u16 ht_operation_mode);
1299 int wl12xx_acx_set_ba_initiator_policy(struct wl1271 *wl,
1300 				       struct wl12xx_vif *wlvif);
1301 int wl12xx_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index,
1302 				       u16 ssn, bool enable, u8 peer_hlid);
1303 int wl12xx_acx_tsf_info(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1304 			u64 *mactime);
1305 int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1306 			       bool enable);
1307 int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1308 int wl12xx_acx_config_ps(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1309 int wl1271_acx_set_inconnection_sta(struct wl1271 *wl, u8 *addr);
1310 int wl1271_acx_fm_coex(struct wl1271 *wl);
1311 int wl12xx_acx_set_rate_mgmt_params(struct wl1271 *wl);
1312 int wl12xx_acx_config_hangover(struct wl1271 *wl);
1313 
1314 #endif /* __WL1271_ACX_H__ */
1315