1 /* 2 * Copyright (c) 2010 Nuvoton technology corporation. 3 * 4 * Wan ZongShun <mcuos.com@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation;version 2 of the License. 9 * 10 */ 11 12 #ifndef _NUC900_AUDIO_H 13 #define _NUC900_AUDIO_H 14 15 #include <linux/io.h> 16 17 /* Audio Control Registers */ 18 #define ACTL_CON 0x00 19 #define ACTL_RESET 0x04 20 #define ACTL_RDSTB 0x08 21 #define ACTL_RDST_LENGTH 0x0C 22 #define ACTL_RDSTC 0x10 23 #define ACTL_RSR 0x14 24 #define ACTL_PDSTB 0x18 25 #define ACTL_PDST_LENGTH 0x1C 26 #define ACTL_PDSTC 0x20 27 #define ACTL_PSR 0x24 28 #define ACTL_IISCON 0x28 29 #define ACTL_ACCON 0x2C 30 #define ACTL_ACOS0 0x30 31 #define ACTL_ACOS1 0x34 32 #define ACTL_ACOS2 0x38 33 #define ACTL_ACIS0 0x3C 34 #define ACTL_ACIS1 0x40 35 #define ACTL_ACIS2 0x44 36 #define ACTL_COUNTER 0x48 37 38 /* bit definition of REG_ACTL_CON register */ 39 #define R_DMA_IRQ 0x1000 40 #define T_DMA_IRQ 0x0800 41 #define IIS_AC_PIN_SEL 0x0100 42 #define FIFO_TH 0x0080 43 #define ADC_EN 0x0010 44 #define M80_EN 0x0008 45 #define ACLINK_EN 0x0004 46 #define IIS_EN 0x0002 47 48 /* bit definition of REG_ACTL_RESET register */ 49 #define W5691_PLAY 0x20000 50 #define ACTL_RESET_BIT 0x10000 51 #define RECORD_RIGHT_CHNNEL 0x08000 52 #define RECORD_LEFT_CHNNEL 0x04000 53 #define PLAY_RIGHT_CHNNEL 0x02000 54 #define PLAY_LEFT_CHNNEL 0x01000 55 #define DAC_PLAY 0x00800 56 #define ADC_RECORD 0x00400 57 #define M80_PLAY 0x00200 58 #define AC_RECORD 0x00100 59 #define AC_PLAY 0x00080 60 #define IIS_RECORD 0x00040 61 #define IIS_PLAY 0x00020 62 #define DAC_RESET 0x00010 63 #define ADC_RESET 0x00008 64 #define M80_RESET 0x00004 65 #define AC_RESET 0x00002 66 #define IIS_RESET 0x00001 67 68 /* bit definition of REG_ACTL_ACCON register */ 69 #define AC_BCLK_PU_EN 0x20 70 #define AC_R_FINISH 0x10 71 #define AC_W_FINISH 0x08 72 #define AC_W_RES 0x04 73 #define AC_C_RES 0x02 74 75 /* bit definition of ACTL_RSR register */ 76 #define R_FIFO_EMPTY 0x04 77 #define R_DMA_END_IRQ 0x02 78 #define R_DMA_MIDDLE_IRQ 0x01 79 80 /* bit definition of ACTL_PSR register */ 81 #define P_FIFO_EMPTY 0x04 82 #define P_DMA_END_IRQ 0x02 83 #define P_DMA_MIDDLE_IRQ 0x01 84 85 /* bit definition of ACTL_ACOS0 register */ 86 #define SLOT1_VALID 0x01 87 #define SLOT2_VALID 0x02 88 #define SLOT3_VALID 0x04 89 #define SLOT4_VALID 0x08 90 #define VALID_FRAME 0x10 91 92 /* bit definition of ACTL_ACOS1 register */ 93 #define R_WB 0x80 94 95 #define CODEC_READY 0x10 96 #define RESET_PRSR 0x00 97 #define AUDIO_WRITE(addr, val) __raw_writel(val, addr) 98 #define AUDIO_READ(addr) __raw_readl(addr) 99 100 struct nuc900_audio { 101 void __iomem *mmio; 102 spinlock_t lock; 103 dma_addr_t dma_addr[2]; 104 unsigned long buffersize[2]; 105 unsigned long irq_num; 106 struct snd_pcm_substream *substream; 107 struct resource *res; 108 struct clk *clk; 109 struct device *dev; 110 111 }; 112 113 extern struct nuc900_audio *nuc900_ac97_data; 114 115 #endif /*end _NUC900_AUDIO_H */ 116