1 /* 2 * TXx9 SoC AC Link Controller 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef __TXX9ACLC_H 10 #define __TXX9ACLC_H 11 12 #include <linux/interrupt.h> 13 #include <asm/txx9/dmac.h> 14 15 #define ACCTLEN 0x00 /* control enable */ 16 #define ACCTLDIS 0x04 /* control disable */ 17 #define ACCTL_ENLINK 0x00000001 /* enable/disable AC-link */ 18 #define ACCTL_AUDODMA 0x00000100 /* AUDODMA enable/disable */ 19 #define ACCTL_AUDIDMA 0x00001000 /* AUDIDMA enable/disable */ 20 #define ACCTL_AUDOEHLT 0x00010000 /* AUDO error halt 21 enable/disable */ 22 #define ACCTL_AUDIEHLT 0x00100000 /* AUDI error halt 23 enable/disable */ 24 #define ACREGACC 0x08 /* codec register access */ 25 #define ACREGACC_DAT_SHIFT 0 /* data field */ 26 #define ACREGACC_REG_SHIFT 16 /* address field */ 27 #define ACREGACC_CODECID_SHIFT 24 /* CODEC ID field */ 28 #define ACREGACC_READ 0x80000000 /* CODEC read */ 29 #define ACREGACC_WRITE 0x00000000 /* CODEC write */ 30 #define ACINTSTS 0x10 /* interrupt status */ 31 #define ACINTMSTS 0x14 /* interrupt masked status */ 32 #define ACINTEN 0x18 /* interrupt enable */ 33 #define ACINTDIS 0x1c /* interrupt disable */ 34 #define ACINT_CODECRDY(n) (0x00000001 << (n)) /* CODECn ready */ 35 #define ACINT_REGACCRDY 0x00000010 /* ACREGACC ready */ 36 #define ACINT_AUDOERR 0x00000100 /* AUDO underrun error */ 37 #define ACINT_AUDIERR 0x00001000 /* AUDI overrun error */ 38 #define ACDMASTS 0x80 /* DMA request status */ 39 #define ACDMA_AUDO 0x00000001 /* AUDODMA pending */ 40 #define ACDMA_AUDI 0x00000010 /* AUDIDMA pending */ 41 #define ACAUDODAT 0xa0 /* audio out data */ 42 #define ACAUDIDAT 0xb0 /* audio in data */ 43 #define ACREVID 0xfc /* revision ID */ 44 45 struct txx9aclc_dmadata { 46 struct resource *dma_res; 47 struct txx9dmac_slave dma_slave; 48 struct dma_chan *dma_chan; 49 struct tasklet_struct tasklet; 50 spinlock_t dma_lock; 51 int stream; /* SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE */ 52 struct snd_pcm_substream *substream; 53 unsigned long pos; 54 dma_addr_t dma_addr; 55 unsigned long buffer_bytes; 56 unsigned long period_bytes; 57 unsigned long frag_bytes; 58 int frags; 59 int frag_count; 60 int dmacount; 61 }; 62 63 struct txx9aclc_plat_drvdata { 64 void __iomem *base; 65 u64 physbase; 66 }; 67 txx9aclc_get_plat_drvdata(struct snd_soc_dai * dai)68static inline struct txx9aclc_plat_drvdata *txx9aclc_get_plat_drvdata( 69 struct snd_soc_dai *dai) 70 { 71 return dev_get_drvdata(dai->dev); 72 } 73 74 #endif /* __TXX9ACLC_H */ 75