Lines Matching refs:msr
37 static bool is_write_only_msr(uint32_t msr) in is_write_only_msr() argument
39 return msr == HV_X64_MSR_EOI; in is_write_only_msr()
42 static void guest_msr(struct msr_data *msr) in guest_msr() argument
47 GUEST_ASSERT(msr->idx); in guest_msr()
49 if (msr->write) in guest_msr()
50 vector = wrmsr_safe(msr->idx, msr->write_val); in guest_msr()
52 if (!vector && (!msr->write || !is_write_only_msr(msr->idx))) in guest_msr()
53 vector = rdmsr_safe(msr->idx, &msr_val); in guest_msr()
55 if (msr->fault_expected) in guest_msr()
58 msr->idx, msr->write ? "WR" : "RD", vector); in guest_msr()
62 msr->idx, msr->write ? "WR" : "RD", vector); in guest_msr()
64 if (vector || is_write_only_msr(msr->idx)) in guest_msr()
67 if (msr->write) in guest_msr()
70 msr->idx, msr->write_val, msr_val); in guest_msr()
73 if (msr->idx == HV_X64_MSR_TSC_INVARIANT_CONTROL) { in guest_msr()
138 struct msr_data *msr; in guest_test_msrs_access() local
146 msr = addr_gva2hva(vm, msr_gva); in guest_test_msrs_access()
171 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
172 msr->write = false; in guest_test_msrs_access()
173 msr->fault_expected = true; in guest_test_msrs_access()
176 msr->idx = HV_X64_MSR_HYPERCALL; in guest_test_msrs_access()
177 msr->write = false; in guest_test_msrs_access()
178 msr->fault_expected = true; in guest_test_msrs_access()
186 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
187 msr->write = true; in guest_test_msrs_access()
188 msr->write_val = HYPERV_LINUX_OS_ID; in guest_test_msrs_access()
189 msr->fault_expected = false; in guest_test_msrs_access()
192 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
193 msr->write = false; in guest_test_msrs_access()
194 msr->fault_expected = false; in guest_test_msrs_access()
197 msr->idx = HV_X64_MSR_HYPERCALL; in guest_test_msrs_access()
198 msr->write = false; in guest_test_msrs_access()
199 msr->fault_expected = false; in guest_test_msrs_access()
203 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
204 msr->write = false; in guest_test_msrs_access()
205 msr->fault_expected = true; in guest_test_msrs_access()
209 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
210 msr->write = false; in guest_test_msrs_access()
211 msr->fault_expected = false; in guest_test_msrs_access()
215 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
216 msr->write = true; in guest_test_msrs_access()
217 msr->write_val = 1; in guest_test_msrs_access()
218 msr->fault_expected = true; in guest_test_msrs_access()
222 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
223 msr->write = false; in guest_test_msrs_access()
224 msr->fault_expected = true; in guest_test_msrs_access()
228 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
229 msr->write = false; in guest_test_msrs_access()
230 msr->fault_expected = false; in guest_test_msrs_access()
234 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
235 msr->write = true; in guest_test_msrs_access()
236 msr->write_val = 1; in guest_test_msrs_access()
237 msr->fault_expected = true; in guest_test_msrs_access()
241 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
242 msr->write = false; in guest_test_msrs_access()
243 msr->fault_expected = true; in guest_test_msrs_access()
247 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
248 msr->write = false; in guest_test_msrs_access()
249 msr->fault_expected = false; in guest_test_msrs_access()
253 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
254 msr->write = true; in guest_test_msrs_access()
255 msr->write_val = 1; in guest_test_msrs_access()
256 msr->fault_expected = true; in guest_test_msrs_access()
260 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
261 msr->write = false; in guest_test_msrs_access()
262 msr->fault_expected = true; in guest_test_msrs_access()
266 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
267 msr->write = false; in guest_test_msrs_access()
268 msr->fault_expected = false; in guest_test_msrs_access()
271 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
272 msr->write = true; in guest_test_msrs_access()
279 msr->write_val = 0; in guest_test_msrs_access()
280 msr->fault_expected = false; in guest_test_msrs_access()
284 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
285 msr->write = false; in guest_test_msrs_access()
286 msr->fault_expected = true; in guest_test_msrs_access()
290 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
291 msr->write = false; in guest_test_msrs_access()
292 msr->fault_expected = false; in guest_test_msrs_access()
295 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
296 msr->write = true; in guest_test_msrs_access()
297 msr->write_val = 0; in guest_test_msrs_access()
298 msr->fault_expected = false; in guest_test_msrs_access()
302 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
303 msr->write = false; in guest_test_msrs_access()
304 msr->fault_expected = true; in guest_test_msrs_access()
311 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
312 msr->write = false; in guest_test_msrs_access()
313 msr->fault_expected = true; in guest_test_msrs_access()
317 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
318 msr->write = false; in guest_test_msrs_access()
319 msr->fault_expected = false; in guest_test_msrs_access()
322 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
323 msr->write = true; in guest_test_msrs_access()
324 msr->write_val = 0; in guest_test_msrs_access()
325 msr->fault_expected = false; in guest_test_msrs_access()
329 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
330 msr->write = false; in guest_test_msrs_access()
331 msr->fault_expected = true; in guest_test_msrs_access()
335 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
336 msr->write = false; in guest_test_msrs_access()
337 msr->fault_expected = false; in guest_test_msrs_access()
340 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
341 msr->write = true; in guest_test_msrs_access()
342 msr->write_val = 0; in guest_test_msrs_access()
343 msr->fault_expected = false; in guest_test_msrs_access()
347 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
348 msr->write = true; in guest_test_msrs_access()
349 msr->write_val = 1 << 12; in guest_test_msrs_access()
350 msr->fault_expected = true; in guest_test_msrs_access()
354 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
355 msr->write = true; in guest_test_msrs_access()
356 msr->write_val = 1 << 12; in guest_test_msrs_access()
357 msr->fault_expected = false; in guest_test_msrs_access()
361 msr->idx = HV_X64_MSR_EOI; in guest_test_msrs_access()
362 msr->write = false; in guest_test_msrs_access()
363 msr->fault_expected = true; in guest_test_msrs_access()
367 msr->idx = HV_X64_MSR_EOI; in guest_test_msrs_access()
368 msr->write = true; in guest_test_msrs_access()
369 msr->write_val = 1; in guest_test_msrs_access()
370 msr->fault_expected = false; in guest_test_msrs_access()
374 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
375 msr->write = false; in guest_test_msrs_access()
376 msr->fault_expected = true; in guest_test_msrs_access()
380 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
381 msr->write = false; in guest_test_msrs_access()
382 msr->fault_expected = false; in guest_test_msrs_access()
386 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
387 msr->write = true; in guest_test_msrs_access()
388 msr->write_val = 1; in guest_test_msrs_access()
389 msr->fault_expected = true; in guest_test_msrs_access()
393 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
394 msr->write = false; in guest_test_msrs_access()
395 msr->fault_expected = true; in guest_test_msrs_access()
399 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
400 msr->write = false; in guest_test_msrs_access()
401 msr->fault_expected = false; in guest_test_msrs_access()
404 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
405 msr->write = true; in guest_test_msrs_access()
406 msr->write_val = 1; in guest_test_msrs_access()
407 msr->fault_expected = false; in guest_test_msrs_access()
411 msr->idx = HV_X64_MSR_TSC_EMULATION_STATUS; in guest_test_msrs_access()
412 msr->write = true; in guest_test_msrs_access()
413 msr->write_val = 1; in guest_test_msrs_access()
414 msr->fault_expected = true; in guest_test_msrs_access()
418 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
419 msr->write = false; in guest_test_msrs_access()
420 msr->fault_expected = true; in guest_test_msrs_access()
424 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
425 msr->write = false; in guest_test_msrs_access()
426 msr->fault_expected = false; in guest_test_msrs_access()
429 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
430 msr->write = true; in guest_test_msrs_access()
431 msr->write_val = 1; in guest_test_msrs_access()
432 msr->fault_expected = false; in guest_test_msrs_access()
436 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
437 msr->write = false; in guest_test_msrs_access()
438 msr->fault_expected = true; in guest_test_msrs_access()
443 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
444 msr->write = false; in guest_test_msrs_access()
445 msr->fault_expected = false; in guest_test_msrs_access()
448 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
449 msr->write = true; in guest_test_msrs_access()
450 msr->write_val = 0; in guest_test_msrs_access()
451 msr->fault_expected = false; in guest_test_msrs_access()
458 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
459 msr->write = false; in guest_test_msrs_access()
460 msr->fault_expected = true; in guest_test_msrs_access()
467 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
468 msr->write = false; in guest_test_msrs_access()
469 msr->fault_expected = false; in guest_test_msrs_access()
475 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
476 msr->write = true; in guest_test_msrs_access()
477 msr->write_val = 0xdeadbeef; in guest_test_msrs_access()
478 msr->fault_expected = true; in guest_test_msrs_access()
484 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
485 msr->write = true; in guest_test_msrs_access()
486 msr->write_val = 1; in guest_test_msrs_access()
487 msr->fault_expected = false; in guest_test_msrs_access()
500 msr->idx, msr->write ? "write" : "read"); in guest_test_msrs_access()